JP2003174056A - Electronic part element, manufacturing method therefor and electronic part device - Google Patents
Electronic part element, manufacturing method therefor and electronic part deviceInfo
- Publication number
- JP2003174056A JP2003174056A JP2001374516A JP2001374516A JP2003174056A JP 2003174056 A JP2003174056 A JP 2003174056A JP 2001374516 A JP2001374516 A JP 2001374516A JP 2001374516 A JP2001374516 A JP 2001374516A JP 2003174056 A JP2003174056 A JP 2003174056A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- electronic component
- alloy
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品素子の素
子基板上に形成された金属バンプをセラミック等からな
るパッケージや回路基板等の電極パターンに押し付けて
接続するフェースダウン実装に好適な電子部品素子及び
その製造方法、並びに電子部品装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component suitable for face-down mounting in which a metal bump formed on an element substrate of an electronic component element is pressed against an electrode pattern of a package made of ceramic or the like or a circuit board to connect. The present invention relates to an element, a method for manufacturing the element, and an electronic component device.
【０００２】[0002]
【従来の技術】近年、携帯電話などの電子部品装置の小
型化、低背化に伴い、電子部品装置に用いられる電子部
品素子の電極パッドとパッケージの電極パターンとの接
続方法として、ワイヤによる接続方法に代えて、電子部
品素子の機能面をパッケージの接続面に対向させ直接実
装する、フェースダウン方式による接続方法が開発され
ている。このようなフェースダウン方式における、電子
部品素子の電極パッドとパッケージの電極パターンとの
接続には、接続の容易性や寸法制御性からＡｕバンプが
良く用いられている。2. Description of the Related Art In recent years, with the downsizing and height reduction of electronic component devices such as mobile phones, wire connection is used as a method for connecting the electrode pads of the electronic component elements used in the electronic component device and the electrode patterns of the package. Instead of the method, a connection method by a face-down method has been developed, in which the functional surface of the electronic component element is opposed to the connection surface of the package and directly mounted. In such a face-down method, Au bumps are often used for connection between the electrode pads of the electronic component element and the electrode patterns of the package because of their ease of connection and dimensional controllability.
【０００３】このような電子部品素子である弾性表面波
装置（以下、ＳＡＷデバイスという）としては、例えば
特開２０００−９１８７０号公報に記載のＳＡＷデバイ
スが知られている。上記ＳＡＷデバイスは、圧電基板
（素子基板、酸化物基板）と、この圧電基板の主面にそ
れぞれ配設されたくし型電極部（以下、ＩＤＴという）
及び外部接続端子を備えた弾性表面波素子（素子部）を
有し、外部接続端子がＩＤＴを構成する、アルミニウム
（Ａｌ）又はＡｌ合金からなる第１の電極金属層上に、
Ａｌ等からなる第２の電極金属層が積層された二層構造
を有する第１の領域と、第２の電極金属層が圧電基板上
に直接配設された第２の領域とを有している。As a surface acoustic wave device (hereinafter referred to as a SAW device) which is such an electronic component element, for example, a SAW device described in Japanese Patent Laid-Open No. 2000-91870 is known. The SAW device includes a piezoelectric substrate (element substrate, oxide substrate) and comb-shaped electrode portions (hereinafter referred to as IDTs) arranged on the main surface of the piezoelectric substrate.
And a surface acoustic wave element (element part) having an external connection terminal, the external connection terminal constituting an IDT, on the first electrode metal layer made of aluminum (Al) or Al alloy,
A first region having a two-layer structure in which a second electrode metal layer made of Al or the like is laminated, and a second region in which the second electrode metal layer is directly disposed on the piezoelectric substrate. There is.
【０００４】しかしながら、上記従来の二層構造の電極
では、デュプレクサなど高耐電力化が要求される、電子
部品素子としての弾性表面波（以下、ＳＡＷと記す）フ
ィルタの素子部や、電極パッドに電極として用いた場
合、高耐電力化に対応できないという問題を生じてい
る。However, in the above-mentioned conventional two-layer structure electrode, the element portion of the surface acoustic wave (hereinafter referred to as SAW) filter as an electronic component element and the electrode pad, which are required to have high power resistance such as a duplexer. When it is used as an electrode, there is a problem that it cannot cope with high power resistance.
【０００５】そこで、本発明者は、上記問題を回避する
ために、上記公報の構造を、耐電力性向上のために用い
られている、Ａｌ／Ｔｉ構造の電極に用いることを考え
た。Therefore, in order to avoid the above problem, the present inventor considered using the structure of the above-mentioned publication for an electrode of Al / Ti structure which is used for improving the power resistance.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記公
報の構造を、Ａｌ／Ｔｉ構造の電極に用いたところ、バ
ンプ下の圧電基板にクラックが発生するという不具合が
生じることを見出した。これは、電極の下地にＴｉを用
いて、フェースダウン方式で実装すると、パッケージの
封止時の熱応力を、固いＴｉが緩和しきれないためであ
ることが分かった。However, it has been found that when the structure of the above publication is used for an electrode having an Al / Ti structure, a crack occurs in the piezoelectric substrate under the bump. It has been found that when Ti is used as the base of the electrode and mounting is performed by the face-down method, the hard Ti cannot fully absorb the thermal stress when the package is sealed.
【０００７】[0007]
【課題を解決するための手段】本発明に係る電子部品素
子は、上記課題を解決するために、電子回路のための素
子部が素子基板上に形成され、上記素子部を外部と電気
的に接続するための電極パッドが金属バンプを用いたフ
ェースダウン実装用に設けられ、上記電極パッドは、素
子部から延びるＡｌ又はＡl合金／Ｔｉ下地の二層構造
の引き出し電極上に電極パッドの一部が重ね合わされて
おり、Ａｌ又はＡl合金からなるパッド電極層と電極パ
ッド上に設けられる金属バンプの拡散を抑制するための
バリア層とを有し、バリア層はパッド電極層の中間に設
けられていることを特徴としている。In order to solve the above-mentioned problems, an electronic component element according to the present invention has an element portion for an electronic circuit formed on an element substrate, and the element portion is electrically connected to the outside. An electrode pad for connection is provided for face-down mounting using a metal bump, and the electrode pad is a part of the electrode pad on a lead-out electrode having a two-layer structure of Al or Al alloy / Ti base that extends from the element portion. And a pad electrode layer made of Al or Al alloy and a barrier layer for suppressing diffusion of metal bumps provided on the electrode pad, the barrier layer being provided in the middle of the pad electrode layer. It is characterized by being.
【０００８】上記構成によれば、デュプレクサなど高耐
電力化が要求される、電子部品素子としての弾性表面波
（以下、ＳＡＷと記す）フィルタの素子部の電極や、電
極パッドに、Ｔｉを下地としてＡｌ（合金）膜を形成す
ることで、Ａｌ（合金）膜の配向性を高める効果と電極
ボトムの静電応力が集中する部分を硬い金属で補強でき
ると言う効果により、耐電力性を飛躍的に向上できる。According to the above construction, Ti is used as an underlayer on the electrodes and electrode pads of the element portion of the surface acoustic wave (hereinafter referred to as SAW) filter as an electronic component element that requires high power resistance such as a duplexer. As a result of forming an Al (alloy) film as a material, the effect of enhancing the orientation of the Al (alloy) film and the effect that the portion of the electrode bottom where the electrostatic stress is concentrated can be reinforced with a hard metal will lead to a dramatic increase in power resistance. Can be improved.
【０００９】また、上記構成では、電極パッド上に設け
られる金属バンプの拡散を抑制するためのバリア層をパ
ッド電極層の中間に設けたことによって、金属バンプの
金属が電極パッド内に拡散することを上記バリア層によ
り抑制できる。Further, in the above structure, since the barrier layer for suppressing the diffusion of the metal bumps provided on the electrode pads is provided in the middle of the pad electrode layers, the metal of the metal bumps diffuses into the electrode pads. Can be suppressed by the barrier layer.
【００１０】これにより、上記構成は、上記拡散に勤す
る体積膨張を伴う金属間化合物の形成領域を素子基板か
ら離すことができて、上記金属間化合物による悪影響を
軽減でき、素子基板にクラックが発生することを回避で
きる。As a result, in the above structure, the formation region of the intermetallic compound which is involved in the diffusion and is accompanied by the volume expansion can be separated from the element substrate, the adverse effect of the intermetallic compound can be reduced, and the element substrate is not cracked. It can be avoided.
【００１１】上記電子部品素子では、Ａｌ又はＡl合金
からなるパッド電極層とバリア層とにおける、素子基板
側の界面にＡｌ酸化層をさらに有していることが好まし
い。In the electronic component element, it is preferable that the pad electrode layer and the barrier layer made of Al or Al alloy further have an Al oxide layer at the interface on the element substrate side.
【００１２】上記構成によれば、さらに、Ａｌ酸化層を
設けたことにより、バリア層の金属が電極パッド内に拡
散することを上記Ａｌ酸化層により抑制できる。According to the above structure, since the Al oxide layer is further provided, the diffusion of the metal of the barrier layer into the electrode pad can be suppressed by the Al oxide layer.
【００１３】上記電子部品素子においては、バリア層
が、ＮｉＣｒ、Ｃｒ、Ｔｉ、Ｎｉ、Ｔａ及びＷからなる
群から選択される少なくとも１種からなることが望まし
い。In the above electronic component element, it is desirable that the barrier layer is made of at least one selected from the group consisting of NiCr, Cr, Ti, Ni, Ta and W.
【００１４】また、高耐電力性を有する上記構成におい
ては、素子基板（圧電基板）上にドライエッチング法又
はリフトオフ法で形成されたＡｌ／Ｔｉ電極パッドとな
るアース及び入出力用電極上にリフトオフ蒸着法により
さらに厚さ１μｍ程度の純Ａｌ又は略Ａｌ−１ｗｔ％Ｃ
ｕ合金からなるパッド電極層の中間に、Ａｌとの接着強
度の良いＮｉＣｒ合金やＴｉ等からなるバリア層（中間
電極層）と共に設けることにより、接合に十分な電極パ
ッドの厚さを確保できる。Further, in the above-mentioned structure having high power resistance, lift-off is performed on the ground and input / output electrodes which become Al / Ti electrode pads formed on the element substrate (piezoelectric substrate) by the dry etching method or the lift-off method. Pure Al having a thickness of about 1 μm or approximately Al-1 wt% C by the vapor deposition method
The thickness of the electrode pad sufficient for bonding can be ensured by providing it in the middle of the pad electrode layer made of the u alloy together with the barrier layer (intermediate electrode layer) made of NiCr alloy or Ti having good adhesive strength with Al.
【００１５】上記電子部品素子では、電極パッド上に設
けられる金属バンプが、Ａｕ又はＰｔからなることが好
ましい。In the above electronic component element, the metal bumps provided on the electrode pads are preferably made of Au or Pt.
【００１６】上記電子部品素子においては、電極パッド
上に設けられる金属バンプが、はんだからなっていても
よい。In the above electronic component element, the metal bumps provided on the electrode pads may be made of solder.
【００１７】上記構成によれば、金属バンプが、接合性
には優れているＡｕ、Ｐｔ、はんだ、特に、金属間化合
物を形成し易いＡｕ又はＰｔからなることで、バリア層
の効果をより有効に発揮できる。According to the above structure, the metal bumps are made of Au, Pt, and solder, which have excellent bonding properties, and in particular Au or Pt that easily forms an intermetallic compound, so that the effect of the barrier layer is more effective. Can be demonstrated.
【００１８】上記電子部品素子では、素子基板とＡｌ又
はＡl合金／Ｔｉ下地の二層構造の素子部及び引き出し
電極との間に、酸素含有Ｔｉ層が設けられていることが
望ましい。In the above electronic component element, it is desirable that an oxygen-containing Ti layer is provided between the element substrate and the element portion having a two-layer structure of Al or Al alloy / Ti base and the extraction electrode.
【００１９】上記構成によれば、酸素含有Ｔｉ層を有す
ることによって、封止の熱工程において、素子基板中の
酸素がＴｉにより吸い取られるために、素子基板の結晶
性がみだれて、破壊強度が低下することが上記酸素含有
Ｔｉ層により抑制されて、電極パッド下の素子基板にお
けるクラックの発生を低減できる。According to the above construction, by having the oxygen-containing Ti layer, oxygen in the element substrate is absorbed by Ti in the encapsulation heat step, so that the crystallinity of the element substrate is exaggerated and the fracture strength is increased. The decrease is suppressed by the oxygen-containing Ti layer, and the occurrence of cracks in the element substrate under the electrode pad can be reduced.
【００２０】上記電子部品素子においては、前記素子部
のＡｌ又はＡl合金／Ｔｉ下地の二層構造の素子部及び
引き出し電極はリフトオフ法を用いて作成されているこ
とが好ましい。In the above electronic component element, it is preferable that the element portion having a two-layer structure of Al or Al alloy / Ti base of the element portion and the extraction electrode are formed by a lift-off method.
【００２１】上記構成によれば、Ａｌ又はＡl合金／Ｔ
ｉ下地の二層構造の電極をリフトオフ法により作成した
ので、素子基板に対するダメージを軽減できて、上記素
子基板でのクラック発生を抑制できる。According to the above constitution, Al or Al alloy / T
Since the two-layer electrode of the i base is formed by the lift-off method, damage to the element substrate can be reduced, and the occurrence of cracks on the element substrate can be suppressed.
【００２２】本発明の電子部品素子の製造方法は、前記
の課題を解決するために、酸化物基板上に、Ａl又はＡl
合金／Ｔｉの二層電極からなる素子部及び引き出し電極
を作成し、その後、該素子部と異なる領域にバンプパッ
ドのパターンをレジストにより形成し、減圧状態でイオ
ンクリーニングを施した後、Ａl又はＡl合金を真空蒸着
により成膜した後、酸素雰囲気にさらすことにより、表
面を酸化し、再び真空状態でバリア層とＡ１又はＡl合
金とをそれぞれ蒸着し、しかる後にレジストを不要な金
属と共に除去することを特徴としている。In order to solve the above-mentioned problems, the method of manufacturing an electronic component element of the present invention comprises Al or Al on an oxide substrate.
An element part and an extraction electrode composed of a two-layer alloy / Ti electrode are formed, and then a bump pad pattern is formed in a region different from the element part with a resist, and ion cleaning is performed under reduced pressure, and then Al or Al is used. After forming the alloy by vacuum evaporation, oxidize the surface by exposing it to an oxygen atmosphere, and again evaporate the barrier layer and A1 or Al alloy in a vacuum state, and then remove the resist together with unnecessary metal. Is characterized by.
【００２３】上記電子部品素子の製造方法では、バリア
層を、ＮｉＣｒ、Ｃｒ、Ｔｉ、Ｎｉ、Ｔａ及びＷからな
る群から選択される少なくとも１種を用いて作製するこ
とが好ましい。In the method of manufacturing the electronic component element, it is preferable that the barrier layer is made of at least one selected from the group consisting of NiCr, Cr, Ti, Ni, Ta and W.
【００２４】上記電子部品素子の製造方法においては、
前記イオンクリーニング→Ａｌ又はＡl合金蒸着→酸素
雰囲気による表面酸化→バリア層蒸着→Ａｌ又はＡl合
金蒸着の一連の各工程を１台の真空蒸着装置で連続処理
してもよい。In the method of manufacturing the electronic component element,
A series of steps of the above-mentioned ion cleaning → Al or Al alloy vapor deposition → surface oxidation in an oxygen atmosphere → barrier layer vapor deposition → Al or Al alloy vapor deposition may be continuously processed by one vacuum vapor deposition apparatus.
【００２５】本発明の電子部品装置は、前記の課題を解
決するために、前記の何れかに記載の電子部品素子をパ
ッケージ内にフェースダウン実装で収納したことを特徴
としている。In order to solve the above-mentioned problems, the electronic component device of the present invention is characterized in that the electronic component element according to any one of the above is housed in a package by face-down mounting.
【００２６】上記製造方法では、ＩＤＴ等の素子部を形
成する時に、引き出し電極までを同時に形成するが、バ
ンプ用の電極パッド部分は、その後で、別体にてリフト
オフ法で形成する様にすることが好ましい。In the above-mentioned manufacturing method, even when the element portion such as the IDT is formed, the lead-out electrode is formed at the same time, but the bump electrode pad portion is formed separately thereafter by the lift-off method. It is preferable.
【００２７】電極パッド部分の電極構造は最下層をＡｌ
合金とし、その表面を一旦酸化したあと、引き続きＮｉ
Ｃｒ（又はＴｉ）等のバリア層→Ａｌ合金を連続成膜し
て形成する。結局、Ａｌ合金／バリア層／ＡＩ酸化層／
Ａｌ合金／素子基板（酸化物基板、圧電基板）と言う四
層構造となる。In the electrode structure of the electrode pad portion, the lowermost layer is made of Al.
After alloying and oxidizing its surface once, continue to Ni
A barrier layer of Cr (or Ti) or the like is formed by continuously forming an Al alloy. After all, Al alloy / barrier layer / AI oxide layer /
It has a four-layer structure of Al alloy / element substrate (oxide substrate, piezoelectric substrate).
【００２８】更にこの電極パッドから延びる引き回し電
極の一部分を先に形成したＩＤＴ等の素子部から延びる
引き出し電極の一部に重ね合わせることで、両者の導通
をとった。Further, a part of the lead-out electrode extending from the electrode pad is overlapped with a part of the lead-out electrode extending from the previously formed element portion such as the IDT to establish electrical connection between them.
【００２９】ここで、電極パッドを単層のＡｌ（合金）
としない理由は、Ａｕ等の金属バンプとＡｌ又はＡｌ合
金が金属間化合物を生成するため、金属間化合物形成→
体積膨張（化合物Ａｌ2Ａｕの体積はＡｌ2＋Ａｕの約２
倍）→応力蓄積→クラック発生と言うメカニズムでクラ
ックが発生しやすくなるからである。Here, the electrode pad is a single layer of Al (alloy).
The reason for not doing this is that since metal bumps such as Au and Al or Al alloy form intermetallic compounds, intermetallic compound formation →
Volume expansion (volume of compound Al 2 Au is about 2 of Al 2 + Au)
This is because cracks are likely to occur due to the mechanism of (multiplication) → stress accumulation → cracking.
【００３０】従って金属間化合物の形成領域をできるだ
け、素子基板から遠ざけるために、Ａｕのバリア層とし
て、ＮｉＣｒあるいはＴｉの中間電極層を設けることが
望ましい。また、ＮｉＣｒ（Ｔｉ）中間電極層と下地の
Ａｌ層との間に、わざわざＡｌ酸化層を設けることが好
ましいのは、ＴｉやＮｉＣｒのバリア層が下地のＡｌ合
金中に拡散し金属間化合物を形成することを防止するた
めである。Therefore, in order to keep the formation region of the intermetallic compound as far as possible from the element substrate, it is desirable to provide an intermediate electrode layer of NiCr or Ti as a barrier layer of Au. In addition, it is preferable to purposely provide an Al oxide layer between the NiCr (Ti) intermediate electrode layer and the underlying Al layer, because the barrier layer of Ti or NiCr diffuses into the underlying Al alloy to form an intermetallic compound. This is to prevent formation.
【００３１】Ａｌ酸化層の上に直接Ａｌ（合金）を形成
する場合には、密着性が確保できない上に、Ａｕの拡散
を防ぐことはできなかった。ＩＤＴ等の素子部とバンプ
用の電極パッドとの導通を取る為に、ＩＤＴ等の素子部
と同時に形成した引き出し電極と、バンプ用の電極パッ
ドと同時に形成した引き回し電極の一部を重ね合わせた
部分は、チップ状の電子部品素子をパッケージと接合す
る領域ではないため、機械的な接合強度は不要である。When Al (alloy) was formed directly on the Al oxide layer, the adhesion could not be secured and the diffusion of Au could not be prevented. In order to establish electrical continuity between the element part such as the IDT and the electrode pad for the bump, the lead-out electrode formed at the same time as the element part such as the IDT and a part of the lead-out electrode formed at the same time as the electrode pad for the bump are overlapped. Since the portion is not a region for joining the chip-shaped electronic component element to the package, mechanical joining strength is unnecessary.
【００３２】したがって、Ａｌ酸化膜の上に直接Ａｌを
成膜しても、何ら差し支えない。ＮｉＣｒ（Ｔｉ）等の
バリア層がＡｕ等の金属バンプのバリアとしての効果を
発揮するためには、少なくとも１０ｎｍの膜厚が必要で
ある。Ａｌ自然酸化膜はせいぜい数ｎｍしか成長しない
ため、Ａｕ等の金属バンプのバリア層としての効果は期
待できない。Therefore, there is no problem even if Al is directly formed on the Al oxide film. In order for the barrier layer such as NiCr (Ti) to exert the effect as the barrier of the metal bump such as Au, a film thickness of at least 10 nm is necessary. Since the Al natural oxide film grows only a few nm at most, it cannot be expected to be effective as a barrier layer for a metal bump such as Au.
【００３３】フリップチップ工法を用いたＳＡＷデバイ
スといった、本発明の電子部品素子は、圧電基板上に形
成された、チタンなどを下地膜として高配向化された高
耐電力性アルミニウム（Ａｌ−Ｃｕ合金）／Ｔｉ多層膜
から形成されているＩＤＴ素子部及び引き出し電極の一
部が先に形成され、外部電極と接続するためのバンプを
形成するための電極パッドと引き回し電極の一部が圧電
基板上の該ＩＤＴ素子以外の領域に形成されており、両
者（素子部とパッド部）を、電気的に接続するために素
子電極である引き出し電極の上に引き回し電極の一部を
重ね合わせる構成を有している。The electronic component element of the present invention, such as a SAW device using the flip chip method, is a highly power-resistant aluminum (Al-Cu alloy) formed on a piezoelectric substrate and highly oriented with titanium or the like as a base film. ) / Ti multi-layered film, the IDT element portion and a part of the lead-out electrode are formed first, and the electrode pad for forming a bump for connecting to an external electrode and a part of the lead-out electrode are formed on the piezoelectric substrate. Is formed in a region other than the IDT element, and has a structure in which a part of the lead-out electrode is superposed on the lead-out electrode which is an element electrode for electrically connecting both (the element part and the pad part). is doing.
【００３４】これにより、高耐電力性と電極バンプ下に
圧電基板のクラック発生が低減された高い信頼性とを合
わせて備えた弾性表面波装置を提供できるようになる。
上記構成では、Ｔｉ層を圧電基板上に形成するとき、Ｔ
ｉ層と圧電基板との界面には酸素含有Ｔｉ層が形成され
ていることが望ましい。As a result, it is possible to provide a surface acoustic wave device having both high power resistance and high reliability in which cracking of the piezoelectric substrate under the electrode bumps is reduced.
In the above structure, when the Ti layer is formed on the piezoelectric substrate, T
It is desirable that an oxygen-containing Ti layer is formed at the interface between the i layer and the piezoelectric substrate.
【００３５】外部接続用の電極パッドはリフトオフ法で
形成されていることが望ましい。ＩＤＴ素子部はリフト
オフ法やドライエッチング法を利用できるが、リフトオ
フ法の方がダメージフリーとなるためより好ましい。It is desirable that the electrode pads for external connection be formed by a lift-off method. A lift-off method or a dry etching method can be used for the IDT element portion, but the lift-off method is more preferable because it is damage-free.
【００３６】[0036]
【発明の実施の形態】本発明の電子部品装置としての弾
性表面波装置について、図１ないし図６に基づいて説明
すると以下の通りである。図２に示すように、弾性表面
波装置１は、セラミックからなるパッケージ９内に、電
子部品素子としての弾性表面波素子２がフェースダウン
実装されたものである。BEST MODE FOR CARRYING OUT THE INVENTION A surface acoustic wave device as an electronic component device of the present invention will be described below with reference to FIGS. As shown in FIG. 2, the surface acoustic wave device 1 has a surface acoustic wave element 2 as an electronic component element mounted face down in a package 9 made of ceramic.
【００３７】弾性表面波素子２は、パッケージ９の内底
面上に形成されたＡｕからなる電極パターン９ａ、９ｂ
に対してそれぞれＡｕバンプ１０により電気的かつ機械
的に接続されている。なお、外部電極９ｃ、９ｄはＡｕ
からなるものであり、電極パターン９ａ、９ｂにそれぞ
れ接続されている。The surface acoustic wave element 2 has electrode patterns 9a and 9b made of Au formed on the inner bottom surface of the package 9.
Are electrically and mechanically connected to each other by Au bumps 10. The external electrodes 9c and 9d are Au.
And is connected to the electrode patterns 9a and 9b, respectively.
【００３８】弾性表面波素子２は、図３に示すように、
タンタル酸リチウム（ＬＴ）等の圧電基板（素子基板、
酸化物基板）３と、圧電基板３上に各弾性表面波フィル
タ（素子部）４、５の各ＩＤＴ４ａ、５ａ及び各反射器
４ｂ、５ｂと、それらＩＤＴ４ａ、５ａの各引き出し電
極４ｃ、５ｃとそれぞれ接続された入力電極６、出力電
極７及びアース電極８とで構成されている。The surface acoustic wave element 2 is, as shown in FIG.
Piezoelectric substrate (element substrate, such as lithium tantalate (LT))
(Oxide substrate) 3, each surface acoustic wave filter (element part) 4, 5 IDTs 4a, 5a and reflectors 4b, 5b on the piezoelectric substrate 3, and lead electrodes 4c, 5c of the IDTs 4a, 5a. The input electrode 6, the output electrode 7 and the ground electrode 8 are connected to each other.
【００３９】各ＩＤＴ４ａ、５ａ及び各反射器４ｂ、５
ｂは、弾性表面波の伝搬方向に沿って設けられている。
ＩＤＴ４ａ、５ａの各引き出し電極４ｃ、５ｃは、弾性
表面波の伝搬方向に対して直交する方向に延びるように
それぞれ設けられている。ＩＤＴ４ａ、５ａと、入力電
極６、出力電極７及びアース電極８との導通は、ＩＤＴ
４ａ、５ａの各引き出し電極４ｃ、５ｃの端部と、入力
電極６、出力電極７及びアース電極８の各引き回し電極
６ａ、７ａ、８ａの端部とが互いに重なり合って当接す
ることにより確保されている。Each IDT 4a, 5a and each reflector 4b, 5
b is provided along the propagation direction of the surface acoustic wave.
The extraction electrodes 4c and 5c of the IDTs 4a and 5a are provided so as to extend in a direction orthogonal to the propagation direction of the surface acoustic waves. The IDTs 4a and 5a are electrically connected to the input electrode 6, the output electrode 7, and the ground electrode 8 by the IDT.
It is ensured by the end portions of the lead-out electrodes 4c and 5c of 4a and 5a and the end portions of the lead-out electrodes 6a, 7a and 8a of the input electrode 6, the output electrode 7 and the ground electrode 8 overlapping and abutting against each other. There is.
【００４０】各ＩＤＴ４ａ、５ａ、各反射器４ｂ、５
ｂ、及び各引き出し電極４ｃ、５ｃは、図１にも示すよ
うに、下地層として５ｎｍ〜ｌ００ｎｍの膜厚のＴｉ層
１１と、Ｔｉ層１１上に積層された１００ｎｍ〜３００
ｎｍの膜厚のＡｌ層１２とからなる厚さ１００ｎｍ〜４
００ｎｍ程度の薄膜によって形成されている。なお、Ａ
ｌ層１２は、例えば、銅が１重量％添加されたＡｌ合金
であってもよい。Each IDT 4a, 5a, each reflector 4b, 5
b and each of the extraction electrodes 4c and 5c, as shown in FIG. 1, a Ti layer 11 having a film thickness of 5 nm to 100 nm as a base layer, and 100 nm to 300 stacked on the Ti layer 11.
the Al layer 12 having a thickness of 100 nm and a thickness of 100 nm to 4
It is formed of a thin film of about 00 nm. In addition, A
The l-layer 12 may be, for example, an Al alloy containing 1% by weight of copper.
【００４１】Ｔｉ層１１と圧電基板３との間には図示し
ないが酸素含有Ｔｉ層が形成されている。酸素含有Ｔｉ
層は、酸素を含有するものであればよく、例えばＴｉ結
晶中に酸素を取り込んだものでもよいし、また、Ｔｉ酸
化物となっていてもよい。An oxygen-containing Ti layer (not shown) is formed between the Ti layer 11 and the piezoelectric substrate 3. Oxygen-containing Ti
The layer only needs to contain oxygen, and may be, for example, a Ti crystal in which oxygen is incorporated, or may be a Ti oxide.
【００４２】これらの電極のうち、弾性表面波フィルタ
４、５のＩＤＴ４ａ、５ａ、各反射器４ｂ、５ｂ、及び
各引き出し電極４ｃ、５ｃは弾性表面波素子２が機能す
るための素子電極（素子部）であり、入力電極６、出力
電極７、アース電極８は、回路基板やパッケージ９と電
気的かつ物理的に接続するための電極パッドである。Among these electrodes, the IDTs 4a and 5a of the surface acoustic wave filters 4 and 5, the reflectors 4b and 5b, and the extraction electrodes 4c and 5c are element electrodes (elements) for the surface acoustic wave element 2 to function. The input electrode 6, the output electrode 7, and the ground electrode 8 are electrode pads for electrically and physically connecting to the circuit board and the package 9.
【００４３】入力電極６、出力電極７、及びアース電極
８は、圧電基板３上に形成された、膜厚１．５μｍ程度
の、Ａｌ又はＡｌ合金からなるパッド電極層１３、１６
を有している。The input electrode 6, the output electrode 7, and the ground electrode 8 are formed on the piezoelectric substrate 3 and have a thickness of about 1.5 μm and are made of Al or an Al alloy and are pad electrode layers 13 and 16.
have.
【００４４】そして、入力電極６、出力電極７、及びア
ース電極８の各パッド電極層１３、１６では、パッド電
極層１３、１６の中間にバリア層としてのＮｉＣｒ（あ
るいはＴｉ）層１５が互いに積層されて設けられてい
る。よって、パッド電極層１３、１６は、膜厚５００ｎ
ｍ程度の、Ａｌ又はＡｌ合金からなる下部電極層１３
と、下部電極層１３より膜厚が大きい、膜厚１μｍ程度
の、Ａｌ又はＡｌ合金からなる上部電極層１６とを有す
ることになる。In each of the pad electrode layers 13 and 16 of the input electrode 6, the output electrode 7 and the ground electrode 8, a NiCr (or Ti) layer 15 as a barrier layer is laminated between the pad electrode layers 13 and 16. Is provided. Therefore, the pad electrode layers 13 and 16 have a film thickness of 500 n.
m or lower electrode layer 13 made of Al or Al alloy
And an upper electrode layer 16 made of Al or an Al alloy having a film thickness larger than that of the lower electrode layer 13 and having a film thickness of about 1 μm.
【００４５】さらに、パッド電極層１３、１６とＮｉＣ
ｒ（あるいはＴｉ）層１５とにおける、圧電基板３側の
界面、つまり下部電極層１３とＮｉＣｒ（あるいはＴ
ｉ）層１５との間に、Ａｌ酸化層１４が設けられている
ことが好ましい。Further, the pad electrode layers 13 and 16 and NiC are used.
The interface of the r (or Ti) layer 15 on the piezoelectric substrate 3 side, that is, the lower electrode layer 13 and the NiCr (or T
i) The Al oxide layer 14 is preferably provided between the layer 15 and the layer 15.
【００４６】次に、本発明における弾性表面波素子２の
製造方法を図１及び図４のフローチャートを参照しなが
ら説明する。まず、ＬＴやニオブ酸リチウム（ＬＮ）な
どの圧電基板３上にレジストパターンを形成し、Ｔｉ層
１１（約１０ｎｍ）とＡｌ（合金）層１２（約２００ｎ
ｍ）とを真空を破らずに（維持して）連続蒸着により順
次それぞれ成膜する（ステップ１、以下、ステップをＳ
と記す）。Ｔｉ層１１を形成したとき、Ｔｉ層１１と圧
電基板３との界面では、Ｔｉ層１１が圧電基板３に含ま
れる酸素を奪って、酸素含有Ｔｉ層が形成されている。Next, a method of manufacturing the surface acoustic wave element 2 according to the present invention will be described with reference to the flow charts of FIGS. First, a resist pattern is formed on a piezoelectric substrate 3 such as LT or lithium niobate (LN), and a Ti layer 11 (about 10 nm) and an Al (alloy) layer 12 (about 200 n) are formed.
m) and () are sequentially formed by continuous vapor deposition without breaking (maintaining) the vacuum (step 1, hereinafter, step S
Note). When the Ti layer 11 is formed, the Ti layer 11 deprives oxygen contained in the piezoelectric substrate 3 at the interface between the Ti layer 11 and the piezoelectric substrate 3 to form an oxygen-containing Ti layer.
【００４７】こうすることによって、Ｔｉ層１１とＡｌ
層１２との界面に酸化膜が形成されないため、Ａｌ層１
２は、その［１１１］結晶軸が圧電基板３の表面方向に
対して垂直方向にそろった一軸配向膜となる（図５参
照）。配向性のそろったＡｌ層１２はＳＡＷのストレス
に強くなり、ストレスマイグレーションが発生しにくく
なる。なお、Ｔｉ層１１を設けない場合、図６に示すよ
うに、Ａｌ層１２の配向性は悪化した。By doing so, the Ti layer 11 and the Al
Since no oxide film is formed at the interface with the layer 12, the Al layer 1
2 is a uniaxially oriented film having its [111] crystal axes aligned in the direction perpendicular to the surface direction of the piezoelectric substrate 3 (see FIG. 5). The Al layer 12 with uniform orientation is resistant to the stress of SAW, and stress migration is less likely to occur. When the Ti layer 11 was not provided, the orientation of the Al layer 12 deteriorated as shown in FIG.
【００４８】その後、有機溶剤でレジストを剥離するリ
フトオフ法により、Ａｌ（合金）層１２／Ｔｉ層１１か
らなるＩＤＴ、反射器及び引き出し電極を形成する。こ
の部分はＡｌ（合金）／Ｔｉ電極をウェハ全面に成膜し
た後、レジストパターン形成→ドライエッチング→レジ
ストハクリというプロセスで形成してもよい。ただし、
この場合は、リフトオフ法に比べてスペース部のダメー
ジの影響を完全に排除することはできない。このため、
本願発明では、リフトオフ法が好ましい。After that, the IDT composed of the Al (alloy) layer 12 / Ti layer 11, the reflector and the extraction electrode are formed by the lift-off method of peeling the resist with an organic solvent. This portion may be formed by a process of forming a resist pattern → dry etching → resist peeling after forming an Al (alloy) / Ti electrode on the entire surface of the wafer. However,
In this case, it is not possible to completely eliminate the influence of damage on the space portion as compared with the lift-off method. For this reason,
In the present invention, the lift-off method is preferable.
【００４９】次に、再度、リフトオフ法によって、引き
回し電極の一部分とバンプパッド用電極を形成する。具
体的には以下の手順に従う。まず、ＩＤＴと反射器と引
き出し電極とを形成した後、引き出し電極とバンプパッ
ドパターン部分が開口したレジストパターンを圧電基板
３上に作成する（Ｓ２）。Next, a part of the lead-out electrode and the bump pad electrode are formed again by the lift-off method. Specifically, follow the procedure below. First, after forming the IDT, the reflector, and the extraction electrode, a resist pattern in which the extraction electrode and the bump pad pattern portion are opened is formed on the piezoelectric substrate 3 (S2).
【００５０】その後、圧電基板３上に、Ａｌ（合金）
（膜厚約５００ｎｍ）を真空蒸着により形成した（Ｓ
３）後、一旦酸素を真空装置内に導入し、Ａｌ表面に自
然酸化膜であるＡｌ酸化層１４を膜厚１ｎｍ〜７ｎｍに
て形成する（Ｓ４）。これは大気を導入して形成しても
よい。この程度の膜厚を有するＡｌ酸化層１４は、バリ
ア機能を発揮できるが、導電性にほとんど影響しないこ
とが確認されている。Then, Al (alloy) is formed on the piezoelectric substrate 3.
(Film thickness of about 500 nm) was formed by vacuum deposition (S
3) After that, oxygen is once introduced into the vacuum apparatus to form an Al oxide layer 14 that is a natural oxide film with a film thickness of 1 nm to 7 nm on the Al surface (S4). It may be formed by introducing air. It has been confirmed that the Al oxide layer 14 having such a film thickness can exert a barrier function, but has almost no effect on conductivity.
【００５１】次に、真空装置内を、再び、１０-2（１Ｅ
−２）Ｐａ程度の真空まで排気を行い、一旦Ａｒガスを
導入し、Ａｒイオンボンバードでイオンクリーニングを
実施した（Ｓ５）後、真空装置内を、１０-5（１Ｅ−
５）Ｐａ程度まで真空排気して、ＮｉＣｒ（あるいはＴ
ｉ）層１５（２０ｎｍ）とＡｌ（合金）（１μｍ）を連
続成膜し（Ｓ６、Ｓ７）、最後にレジストを有機溶剤で
溶出させて不要部分の金属を剥離により除去して（Ｓ
８）、電極構造が完成する。Next, the inside of the vacuum apparatus is again set to 10 -2 (1E).
-2) Evacuation to about Pa is performed, Ar gas is once introduced, and ion cleaning is performed with Ar ion bombardment (S5). Then, the inside of the vacuum apparatus is set to 10 -5 (1E-
5) Evacuate to about Pa and apply NiCr (or T
i) Layer 15 (20 nm) and Al (alloy) (1 μm) are continuously formed (S6, S7), and finally the resist is eluted with an organic solvent to remove the metal in unnecessary portions by peeling (S).
8), the electrode structure is completed.
【００５２】引き回し電極の一部を、先に形成した引き
出し電極の上部に重ね合わせることで、ＩＤＴと電極パ
ッドとの導通が確保できる。By superimposing a part of the lead-out electrode on the upper portion of the lead-out electrode previously formed, the conduction between the IDT and the electrode pad can be secured.
【００５３】このようにして、形成された上部電極層１
６上にボールボンディング法により、Ａｕバンプ１０を
形成する。具体的には、Ａｕワイヤの先端部に形成され
たボールに超音波を印加しながら上記ボールを上部電極
層１６上に圧着し、その後、ボールの部分からＡｕワイ
ヤを切断してＡｕバンプ１０を上記上部電極層１６上に
形成する。The upper electrode layer 1 thus formed
Au bumps 10 are formed on the surface 6 by a ball bonding method. Specifically, while applying ultrasonic waves to the ball formed at the tip of the Au wire, the ball is pressure-bonded onto the upper electrode layer 16, and then the Au wire is cut from the ball portion to form the Au bump 10. It is formed on the upper electrode layer 16.
【００５４】以上のような工程を経て形成された弾性表
面波素子２を、その表面（ＩＤＴ喉の形成面）をパッケ
ージ９上に形成された電極パターン９ａ、９ｂにＡｕバ
ンプ１０を介して対向させ、超音波及び熱を加えながら
押圧して、上記パッケージ９に接続する。次いで、パッ
ケージ９を、はんだを用いて蓋９ｅ部分により気密封止
することによって弾性表面波装置１が完成する。このと
き、はんだによる気密封止のときに弾性表面波素子２に
は３００℃程度の熱が印加される。The surface acoustic wave device 2 formed through the above-described steps faces the surface (IDT throat forming surface) of the electrode patterns 9a and 9b formed on the package 9 via the Au bumps 10. Then, it is pressed while applying ultrasonic waves and heat to connect to the package 9. Next, the surface acoustic wave device 1 is completed by hermetically sealing the package 9 with the lid 9e using solder. At this time, heat of about 300 ° C. is applied to the surface acoustic wave element 2 during airtight sealing with solder.
【００５５】なお、上記の実施の形態では、圧電基板
（素子基板）３として、タンタル酸リチウムやニオブ酸
リチウムからなる圧電基板を用いて説明したが、これに
限るものではなく、例えば、酸化亜鉛膜を設けた絶縁基
板、水晶、ランガサイト等の圧電基板でも同様な効果が
得られるものである。In the above embodiment, the piezoelectric substrate (element substrate) 3 is a piezoelectric substrate made of lithium tantalate or lithium niobate. However, the present invention is not limited to this, and zinc oxide may be used. The same effect can be obtained with an insulating substrate provided with a film, a piezoelectric substrate such as quartz, Langasite, or the like.
【００５６】下記の対策を用いることにより、はんだに
よる気密封止のときの弾性表面波素子２に対する加熱の
影響に関する、本願発明の効果をそれぞれ表１に示すよ
うに確認できた。By using the following measures, the effects of the present invention on the influence of heating on the surface acoustic wave element 2 at the time of hermetically sealing with solder can be confirmed as shown in Table 1.
【００５７】モニタ（比較例）：バンプ下の下層電極が
Ａｌ／Ｔｉであり、その上にＮｉＣｒ→Ａｌ（合金）を
連続成膜した場合。
対策１：バンプ下の電極をＩＤＴ部のＡｌ／Ｔｉと異な
るプロセスで別に形成し、Ａｌ（合金）単層とした場
合。
対策２：対策１のバンプ用の電極パッドをＡｌ（合金）
／ＮｉＣｒ（Ｔｉ）／Ａｌ（合金）／基板の３層膜とし
た場合。
対策３：最下層のＡｌ（合金）を真空蒸着で形成後、一
旦表面を酸化してさらにその上にＮｉＣｒ→Ａｌ（合
金）を連続成膜した場合。Monitor (Comparative Example): The lower layer electrode under the bump is Al / Ti, and NiCr → Al (alloy) is continuously formed thereon. Countermeasure 1: When the electrode under the bump is separately formed by a process different from that of Al / Ti of the IDT portion to form an Al (alloy) single layer. Countermeasure 2: The electrode pad for the bump in Countermeasure 1 is Al (alloy)
In the case of a three-layer film of / NiCr (Ti) / Al (alloy) / substrate. Countermeasure 3: When the lowermost layer Al (alloy) is formed by vacuum evaporation, the surface is once oxidized, and then NiCr → Al (alloy) is continuously formed thereon.
【００５８】[0058]
【表１】 [Table 1]
【００５９】このように電極パッドをＩＤＴ部等の素子
部と別体に設けることにより、クラック発生を抑制でき
て、歩留りを改善できる。また、ＮｉＣｒ（Ｔｉ）層１
５を設けたことによって、クラック発生をより一層抑制
できて、歩留りを改善できる。さらに、Ａｌ酸化層１４
を設けたことで、クラック発生をより一層抑制できて、
歩留りを改善できる。特に、対策３については、大量に
サンプルを作成してその効果の再現性を確認している。By thus providing the electrode pad separately from the element portion such as the IDT portion, the occurrence of cracks can be suppressed and the yield can be improved. In addition, the NiCr (Ti) layer 1
By providing No. 5, crack generation can be further suppressed, and the yield can be improved. Further, the Al oxide layer 14
By providing, it is possible to further suppress the occurrence of cracks,
The yield can be improved. In particular, for Measure 3, a large number of samples are created and the reproducibility of the effect is confirmed.
【００６０】なお、上記では、電子部品装置や電子部品
素子として、弾性表面波装置１や弾性表面波素子２の例
を挙げたが、酸化物基板上にバンプボンディング用に電
極パッドを有するものであれば、特に限定されるもので
はなく、酸化物基板として誘電体基板を用いる積層コン
デンサや、積層インダクタにも本発明は適用可能であ
る。Although the surface acoustic wave device 1 and the surface acoustic wave device 2 are given as examples of the electronic component device and the electronic component element in the above description, the electronic component device and the electronic component element have electrode pads for bump bonding on the oxide substrate. The present invention is not particularly limited, and the present invention can be applied to a multilayer capacitor and a multilayer inductor using a dielectric substrate as an oxide substrate.
【００６１】[0061]
【発明の効果】本発明の電子部品素子は、以上のよう
に、電子回路のための素子部が素子基板上に形成され、
上記素子部を外部と電気的に接続するための電極パッド
が金属バンプを用いたフェースダウン実装用に設けら
れ、上記電極パッドは、素子部から延びるＡｌ又はＡl
合金／Ｔｉ下地の二層構造の引き出し電極上に電極パッ
ドの一部が重ね合わされており、Ａｌ又はＡl合金から
なるパッド電極層と、電極パッド上に設けられる金属バ
ンプの拡散を抑制するためのバリア層とを有し、バリア
層は、パッド電極層の中間に設けられている構成であ
る。As described above, in the electronic component element of the present invention, the element portion for the electronic circuit is formed on the element substrate,
An electrode pad for electrically connecting the element portion to the outside is provided for face-down mounting using a metal bump, and the electrode pad is Al or Al extending from the element portion.
A part of the electrode pad is superposed on the lead-out electrode of the two-layer structure of the alloy / Ti base, and the pad electrode layer made of Al or Al alloy and the diffusion of the metal bump provided on the electrode pad are suppressed. A barrier layer, and the barrier layer is provided in the middle of the pad electrode layer.
【００６２】それゆえ、上記構成は、電極パッド上に設
けられる金属バンプの拡散を抑制するためのバリア層を
パッド電極層の中間に設けたことによって、金属バンプ
の金属が電極パッド内に拡散することを上記バリア層に
より抑制できる。Therefore, in the above structure, the barrier layer for suppressing the diffusion of the metal bump provided on the electrode pad is provided in the middle of the pad electrode layer, so that the metal of the metal bump diffuses into the electrode pad. This can be suppressed by the barrier layer.
【００６３】これにより、上記構成は、上記拡散に勤す
る体積膨張を伴う金属間化合物の形成領域を素子基板か
ら離すことができて、上記金属間化合物による悪影響を
軽減でき、素子基板にクラックが発生することを軽減で
きるという効果を奏する。As a result, in the above-mentioned structure, the formation region of the intermetallic compound accompanied by the volume expansion which is involved in the diffusion can be separated from the element substrate, the adverse effect of the intermetallic compound can be reduced, and the element substrate is not cracked. This has the effect of reducing the occurrence.
【図１】本発明の実施の形態にかかる弾性表面波素子の
要部断面図である。FIG. 1 is a sectional view of an essential part of a surface acoustic wave device according to an embodiment of the present invention.
【図２】上記弾性表面波素子を、パッケージに収納した
弾性表面波装置の概略断面図である。FIG. 2 is a schematic cross-sectional view of a surface acoustic wave device in which the surface acoustic wave element is housed in a package.
【図３】上記弾性表面波素子の平面図である。FIG. 3 is a plan view of the surface acoustic wave device.
【図４】上記弾性表面波素子の製造方法を示す、フロー
チャートである。FIG. 4 is a flowchart showing a method for manufacturing the surface acoustic wave element.
【図５】上記弾性表面波素子における、下地にＴｉ層を
設けたことによるＡｌ層の配向性を示すための、Ｘ線回
折図である。FIG. 5 is an X-ray diffraction diagram for showing the orientation of an Al layer in the surface acoustic wave device, which is obtained by providing a Ti layer as a base.
【図６】下地にＴｉ層を設けない場合の、Ａｌ層の配向
性を示すための、Ｘ線回折図である。FIG. 6 is an X-ray diffraction diagram showing the orientation of an Al layer when a Ti layer is not provided as a base.
１ 弾性表面波装置 ２ 弾性表面波素子 ３ 圧電基板（素子基板、酸化物基板） ４、５ 弾性表面波フィルタ（素子部） ４ｃ、５ｃ 引き出し電極 ６ 入力電極（電極パッド） ７ 出力電極（電極パッド） ８ アース電極（電極パッド） ６ａ、７ａ、８ａ 引き回し電極 １５ ＮｉＣｒ（Ｔｉ）層（バリア層） １６ Ａｌ酸化層 1 Surface acoustic wave device 2 Surface acoustic wave element 3 Piezoelectric substrate (element substrate, oxide substrate) 4, 5 surface acoustic wave filter (element part) 4c, 5c Extraction electrode 6 Input electrodes (electrode pads) 7 Output electrode (electrode pad) 8 ground electrode (electrode pad) 6a, 7a, 8a routing electrodes 15 NiCr (Ti) layer (barrier layer) 16 Al oxide layer
Claims (11)
成され、 上記素子部を外部と電気的に接続するための電極パッド
が金属バンプを用いたフェースダウン実装用に設けら
れ、 上記電極パッドは、素子部から延びるＡｌ又はＡl合金
／Ｔｉ下地の二層構造の引き出し電極上に電極パッドの
一部が重ね合わされており、Ａｌ又はＡl合金からなる
パッド電極層と、電極パッド上に設けられる金属バンプ
の拡散を抑制するためのバリア層とを有し、 バリア層は、パッド電極層の中間に設けられていること
を特徴とする電子部品素子。1. An element portion for an electronic circuit is formed on an element substrate, and electrode pads for electrically connecting the element portion to the outside are provided for face-down mounting using metal bumps. The electrode pad is such that a part of the electrode pad is superposed on the lead electrode of a two-layer structure of Al or Al alloy / Ti base that extends from the element part. The electrode electrode pad made of Al or Al alloy and the electrode pad An electronic component element, comprising: a barrier layer for suppressing diffusion of metal bumps provided, the barrier layer being provided in the middle of the pad electrode layer.
バリア層とにおける、素子基板側の界面にＡｌ酸化層を
さらに有していることを特徴とする請求項１記載の電子
部品素子。2. The electronic component element according to claim 1, further comprising an Al oxide layer at the interface between the pad electrode layer and the barrier layer made of Al or Al alloy on the element substrate side.
ｉ、Ｔａ及びＷからなる群から選択される少なくとも１
種からなることを特徴とする請求項１又は２記載の電子
部品素子。3. The barrier layer comprises NiCr, Cr, Ti, N
at least one selected from the group consisting of i, Ta and W
The electronic component element according to claim 1 or 2, wherein the electronic component element comprises a seed.
Ａｕ又はＰｔからなることを特徴とする請求項１乃至３
の何れか１項に記載の電子部品素子。4. A metal bump provided on an electrode pad,
It consists of Au or Pt, It is characterized by the above-mentioned.
The electronic component element according to any one of 1.
はんだからなることを特徴とする請求項１乃至３の何れ
か１項に記載の電子部品素子。5. A metal bump provided on an electrode pad,
It consists of solder, The electronic component element in any one of Claim 1 thru | or 3 characterized by the above-mentioned.
二層構造の素子部及び引き出し電極との間に、酸素含有
Ｔｉ層が設けられていることを特徴とする請求項１乃至
５の何れか１項に記載の電子部品素子。6. An oxygen-containing Ti layer is provided between an element substrate and an element portion having a two-layer structure of Al or Al alloy / Ti base and an extraction electrode. The electronic component element according to any one of items.
の二層構造の素子部及び引き出し電極はリフトオフ法を
用いて作成されていることを特徴とする請求項１乃至６
の何れか１項に記載の電子部品素子。7. The element portion and the extraction electrode having a two-layer structure of Al or Al alloy / Ti underlayer of the element portion are formed by a lift-off method.
The electronic component element according to any one of 1.
の二層電極からなる素子部及び引き出し電極を作成し、
その後、該素子部と異なる領域にバンプパッドのパター
ンをレジストにより形成し、減圧状態でイオンクリーニ
ングを施した後、Ａl又はＡl合金を真空蒸着により成膜
した後、酸素雰囲気にさらすことにより、表面を酸化
し、再び真空状態でバリア層とＡ１又はＡl合金とをそ
れぞれ蒸着し、しかる後に、レジストを不要な金属と共
に除去することを特徴とする電子部品素子の製造方法。8. An element part and a lead-out electrode comprising a two-layer electrode of Al or Al alloy / Ti is formed on an oxide substrate,
After that, a pattern of a bump pad is formed in a region different from the element portion with a resist, ion cleaning is performed under a reduced pressure, Al or an Al alloy is vacuum-deposited, and then exposed to an oxygen atmosphere. Is oxidized, the barrier layer and A1 or Al alloy are respectively vapor-deposited again in a vacuum state, and then the resist is removed together with unnecessary metal, and a method for manufacturing an electronic component element.
ｉ、Ｔａ及びＷからなる群から選択される少なくとも１
種を用いて作製することを特徴とする請求項８記載の電
子部品素子の製造方法。9. A barrier layer comprising NiCr, Cr, Ti, N
at least one selected from the group consisting of i, Ta and W
9. The method for manufacturing an electronic component element according to claim 8, wherein the electronic component element is manufactured by using a seed.
合金蒸着→酸素雰囲気による表面酸化→バリア層蒸着→
Ａｌ又はＡl合金蒸着の一連の各工程を１台の真空蒸着
装置で連続処理することを特徴とする請求項８又は９記
載の電子部品素子の製造方法。10. The ion cleaning → Al or Al
Alloy deposition → Surface oxidation in oxygen atmosphere → Barrier layer deposition →
The method for manufacturing an electronic component element according to claim 8 or 9, wherein a series of steps of the Al or Al alloy vapor deposition are continuously processed by one vacuum vapor deposition apparatus.
の電子部品素子をパッケージ内にフェースダウン実装で
収納したことを特徴とする電子部品装置。11. An electronic component device in which the electronic component element according to any one of claims 1 to 7 is housed in a package by face-down mounting.
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