JP2003101195A - Substrate for semiconductor device and production method therefor - Google Patents
Substrate for semiconductor device and production method thereforInfo
- Publication number
- JP2003101195A JP2003101195A JP2001293183A JP2001293183A JP2003101195A JP 2003101195 A JP2003101195 A JP 2003101195A JP 2001293183 A JP2001293183 A JP 2001293183A JP 2001293183 A JP2001293183 A JP 2001293183A JP 2003101195 A JP2003101195 A JP 2003101195A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- pattern
- plating
- main conductor
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】高密度配線を形成した半導体
装置用基板とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device substrate having high-density wiring and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】高密度配線を形成した半導体装置用基板
において、導体パターンの保護と半導体装置搭載に不都
合を及ぼさないため、導体パターン露出部に金めっきを
施す必要があるが、高密度配線を形成した後では電解金
めっきを行うためのリードが引き出せないため、無電解
金めっきで代替するか、電解金めっきを行うためのめっ
き用導体接続パターンを形成し、電解金めっきを行った
後にめっき用導体接続パターンを除去する方法がとられ
ている。しかし、無電解金めっきにて形成した金めっき
皮膜の品質は電解金めっきには及ばず、めっき液やめっ
き皮膜の不安定性、めっきコストがかさむという問題か
ら、電解金めっきにて金めっき皮膜を形成することが行
われており、高密度配線を形成した後では上記のめっき
用導体接続パターンの形成、除去の工程が別途発生する
という問題を有している。2. Description of the Related Art In a semiconductor device substrate having a high-density wiring formed, it is necessary to apply gold plating to the exposed portion of the conductor pattern in order to protect the conductor pattern and mount the semiconductor device. Since the lead for performing electrolytic gold plating cannot be pulled out after forming, substitute electroless gold plating or form a conductor connection pattern for plating for performing electrolytic gold plating, and then perform plating after performing electrolytic gold plating. A method of removing the conductor connecting pattern is used. However, the quality of the gold plating film formed by electroless gold plating is inferior to that of electrolytic gold plating, and the instability of the plating solution and plating film and the cost of plating increase the gold plating film. However, after forming the high-density wiring, there is a problem that the steps of forming and removing the conductor connection pattern for plating described above occur separately.
【０００３】また、独立する各端子から金めっき用リー
ドを基板端面部に引き出すと、基板を外形加工して個片
に切り離した時に引き出したリードが端面で露出してし
まうので、端面にレジストを塗布してリード端面を覆う
こともテープベースの一部の品種では行われている。Further, when the gold-plating leads are pulled out from the independent terminals to the end face portion of the substrate, the lead lead out is exposed at the end face when the substrate is subjected to the outer shape processing and separated into individual pieces. Therefore, a resist is applied to the end face. The coating of the end surface of the lead by coating is also performed in some tape-based products.
【０００４】[0004]
【発明が解決しようとする課題】しかし、従来の高密度
配線を形成した後の電解金めっき方法では、めっき用導
体パターンの形成、除去工程を追加する必要があり、複
雑で、通常工程にいくつかの工程を追加しなければなら
ない。そのため、製造コストがかさんで工期が長くなる
だけでなく、収率の低下を招きやすいという問題を有す
る。また、最初に形成した配線パターンに対しめっき用
導体接続パターンの形成、除去プロセスにおいて位置ズ
レが発生しやすいという問題があり、高密度配線パター
ンがまばらな部分を選択してめっき用導体接続パターン
を設けなければならず、高密度配線パターンに接近した
部分にめっき用導体接続パターンを設けると、めっき用
導体接続パターンがずれて高密度配線パターンの方に欠
けや突起状の形状不良を発生させたり、ひどい場合には
高密度配線パターンを断線させてしまうこともある。However, in the conventional electrolytic gold plating method after forming the high-density wiring, it is necessary to add the step of forming and removing the conductor pattern for plating, which is complicated, and the number of steps in the normal step is increased. That process must be added. Therefore, there is a problem that not only the manufacturing cost is high and the construction period is long, but also the yield is likely to be lowered. In addition, there is a problem that positional deviation easily occurs in the formation / removal process of the conductor connection pattern for plating with respect to the wiring pattern formed first. If a conductor connection pattern for plating is provided in a portion close to the high-density wiring pattern, the conductor connection pattern for plating will be displaced, resulting in chipping or protruding shape defects in the high-density wiring pattern. In a severe case, the high density wiring pattern may be broken.
【０００５】そのため、高密度配線パターンの接続パタ
ーン部のピッチを狭めることができず、２００μｍピッ
チ以上のパターンが限界となっていた。また、インピー
ダンスをコントロールする必要のあるラインがあると、
信号の反射が起こり誤動作を招きやすいことから、その
部分にめっき用導体接続パターンを形成できないといっ
た不都合もあった。したがって、余分なスペースがなく
パターン間が接近した高密度配線や高速回路が多い配線
パターンには対応できない。Therefore, the pitch of the connection pattern portion of the high-density wiring pattern cannot be narrowed, and the pattern having a pitch of 200 μm or more is the limit. Also, if there is a line that needs to control impedance,
There is also a disadvantage that the conductor connection pattern for plating cannot be formed in that portion because a signal is reflected and a malfunction is likely to occur. Therefore, it cannot be applied to high-density wiring in which there are no extra spaces and the patterns are close to each other or a wiring pattern having many high-speed circuits.
【０００６】さらに、めっき用導体接続パターンを周囲
に引き出した場合、そのままでは絶縁性低下の危険性が
あったり、これを避けるため端面にレジストを塗布する
場合には、端面の塗布が難しく工数もかかることからあ
まり普及していない。Further, when the conductor connecting pattern for plating is drawn out to the surroundings, there is a risk of deterioration of the insulation as it is, and when resist is applied to the end face in order to avoid this, it is difficult to apply the end face, and the number of steps is also increased. Because of this, it is not widely used.
【０００７】本発明は上記問題点に鑑み考案されたもの
で、高密度配線が形成された半導体装置用基板と半導体
装置用基板の導体パターンの一部表面に電解めっきにて
容易、且つ確実に金被膜等の導電性物質皮膜を形成でき
る半導体装置用基板の製造方法を提供することを目的と
する。The present invention has been devised in view of the above problems, and it is possible to easily and surely perform electrolytic plating on a surface of a semiconductor device substrate on which high-density wiring is formed and a part of a conductor pattern of the semiconductor device substrate by electrolytic plating. An object of the present invention is to provide a method for manufacturing a substrate for a semiconductor device capable of forming a conductive material film such as a gold film.
【０００８】[0008]
【課題を解決するための手段】本発明に於いて上記問題
を解決するため、まず請求項１においては、従たる導体
層上に厚みの異なる主たる導体層が直接積み重ねられて
一つの導体層が形成されており、前記一つの導体層をパ
ターニング処理して形成された配線パターンの主たる導
体層の少なくとも一部表面が主たる導体層とは異なる導
電性物質で覆われている半導体装置用基板であって、前
記配線パターンの少なくとも一つ以上が電気的に絶縁さ
れていることを特徴とする半導体装置用基板としたもの
である。In order to solve the above problems in the present invention, first, in claim 1, a main conductor layer having a different thickness is directly stacked on a subordinate conductor layer to form one conductor layer. A substrate for a semiconductor device in which at least a part of the surface of the main conductor layer of the wiring pattern formed by patterning the one conductor layer is covered with a conductive material different from that of the main conductor layer. And at least one or more of the wiring patterns are electrically insulated.
【０００９】また、請求項２においては、前記主たる導
体層は銅を主成分とする導電性物質で、前記従たる導体
層は銅もしくは銅以外の導電性物質で、前記主たる導体
層とは異なる導電性物質はニッケル、パラジウム、金、
白金、ロジウム、銀及び錫のうち少なくとも１種類から
なる導電性物質で形成されていることを特徴とする請求
項１に記載の半導体装置用基板としたものである。Further, in the present invention, the main conductor layer is a conductive substance containing copper as a main component, and the sub conductor layer is a conductive substance other than copper or copper, which is different from the main conductor layer. Conductive substances are nickel, palladium, gold,
The semiconductor device substrate according to claim 1, wherein the substrate is formed of a conductive material made of at least one of platinum, rhodium, silver and tin.
【００１０】また、請求項３においては、前記主たる導
体層は３μｍ以上の厚みを有し、前記従たる導体層は主
たる導体層以下の厚みからなり、前記配線パターンの少
なくとも一部が１００μｍピッチ以下の微細かつ高密度
な導体パターンであることを特徴とする請求項１または
２に記載の半導体装置用基板としたものである。Further, in the present invention, the main conductor layer has a thickness of 3 μm or more, the sub conductor layer has a thickness of the main conductor layer or less, and at least a part of the wiring pattern has a pitch of 100 μm or less. 3. The semiconductor device substrate according to claim 1 or 2, wherein the conductor pattern is a fine and high-density conductor pattern.
【００１１】また、請求項４においては、少なくとも以
下の工程を備えていることを特徴とする請求項１乃至３
のいずれか一項に記載の半導体装置用基板の製造方法と
したものである。
（ａ）絶縁基板の両面に従たる導体層を形成する工程。
（ｂ）前記従たる導体層上にレジストパターンを形成
し、前記レジストパターンをマスクにして主たる導体
層、主たる導体パターン及びビアホールを形成し、前記
レジストパターンを剥離する工程。
（ｃ）前記従たる導体層及び主たる導体パターン上の所
定位置にレジストパターンを形成する工程。
（ｄ）前記レジストパターンをエッチングマスクにして
従たる導体層をエッチングし、前記レジストパターンを
剥離し、電気的に絶縁された主たる導体パターンを電気
的に接続するめっき用導通リードを従たる導体層で形成
する工程。
（ｅ）前記主たる導体層構成物質とは異なる導電性物質
を主たる導体パターンの少なくとも一部表面に形成する
ためのレジストマスクを形成する工程。
（ｆ）前記レジストマスクをめっきマスクにして電解め
っきを行い、めっき用導通リードで接続された主たる導
体層の一部表面に主たる導体層構成物質とは異なる導電
性物質被膜を形成する工程。
（ｇ）前記レジストマスクを専用の剥離液で除去し、前
記めっき用導通リードをエッチングで除去する工程。
（ｈ）基板上にソルダーレジストパターンを形成する工
程。Further, in claim 4, at least the following steps are provided:
The method for manufacturing a substrate for a semiconductor device according to any one of 1. (A) A step of forming conductor layers on both sides of the insulating substrate. (B) A step of forming a resist pattern on the subordinate conductor layer, forming a main conductor layer, a main conductor pattern and a via hole using the resist pattern as a mask, and peeling off the resist pattern. (C) A step of forming a resist pattern at predetermined positions on the subordinate conductor layer and the main conductor pattern. (D) A conductive layer that is a subordinate conductive layer for plating that etches the subordinate conductor layer using the resist pattern as an etching mask to peel off the resist pattern and electrically connect the electrically insulated main conductive pattern. Forming process. (E) A step of forming a resist mask for forming a conductive substance different from the main conductor layer constituent substance on at least a part of the surface of the main conductor pattern. (F) A step of performing electrolytic plating by using the resist mask as a plating mask to form a conductive substance film different from the main conductor layer constituent substance on a part of the surface of the main conductor layer connected by the conductive lead for plating. (G) A step of removing the resist mask with a dedicated stripping solution, and removing the conductive lead for plating by etching. (H) A step of forming a solder resist pattern on the substrate.
【００１２】また、請求項５においては、少なくとも以
下の工程を備えていることを特徴とする請求項１乃至３
のいずれか一項に記載の半導体装置用基板の製造方法と
したものである。
（ａ）絶縁基板の両面に主たる導体層を形成する工程。
（ｂ）前記主たる導体層をパターニング処理し、主たる
導体パターンを形成する工程。
（ｃ）前記絶縁基板及び前記主たる導体パターン上に従
たる導体層を形成する工程。
（ｄ）前記従たる導体層上の所定位置にレジストパター
ンを形成する工程。
（ｅ）前記レジストパターンをエッチングマスクにして
従たる導体層をエッチングし、めっき用導通リードを形
成する工程。
（ｆ）前記レジストパターンを専用の剥離液で剥離し、
前記主たる導体層構成物質とは異なる導電性物質を主た
る導体パターンの少なくとも一部表面に形成するための
レジストマスクを形成する工程。
（ｇ）前記レジストマスクをめっきマスクにして電解め
っきを行い、めっき用導通リードで接続された主たる導
体層の一部表面に主たる導体層構成物質とは異なる導電
性物質被膜を形成する工程。
（ｈ）前記レジストマスクを専用の剥離液で除去し、前
記めっき用導通リードをエッチングで除去する工程。
（ｉ）基板上にソルダーレジストパターンを形成する工
程。Further, in claim 5, at least the following steps are provided:
The method for manufacturing a substrate for a semiconductor device according to any one of 1. (A) A step of forming main conductor layers on both surfaces of the insulating substrate. (B) A step of patterning the main conductor layer to form a main conductor pattern. (C) A step of forming a conductive layer on the insulating substrate and the main conductive pattern. (D) A step of forming a resist pattern at a predetermined position on the subordinate conductor layer. (E) A step of forming a conductive lead for plating by etching a subordinate conductor layer using the resist pattern as an etching mask. (F) The resist pattern is stripped with a dedicated stripping solution,
A step of forming a resist mask for forming a conductive substance different from the main conductor layer constituent substance on at least a part of the surface of the main conductor pattern. (G) A step of performing electrolytic plating by using the resist mask as a plating mask to form a conductive material film different from the main conductor layer constituent material on a part of the surface of the main conductor layer connected by the conductive lead for plating. (H) A step of removing the resist mask with a dedicated stripping solution and removing the plating conductive leads by etching. (I) A step of forming a solder resist pattern on the substrate.
【００１３】さらにまた、請求項６においては、少なく
とも以下の工程を備えていることを特徴とする請求項１
乃至３のいずれか一項に記載の半導体装置用基板の製造
方法としたものである。
（ａ）絶縁基板の両面に主たる導体層を形成する工程。
（ｂ）前記主たる導体層をパターニング処理し、主たる
導体パターンを形成する工程。
（ｃ）前記絶縁基板及び前記主たる導体パターン上の所
定位置に開口領域を有するレジストパターンを形成する
工程。
（ｄ）前記開口領域を導電化処理する工程。
（ｅ）前記レジストマスクを専用の剥離液で剥離し、無
電解、電解銅めっきを行い、導電化処理された前記開口
領域に従たる導体層からなるめっき用導通リードを形成
する工程。
（ｆ）前記主たる導体層構成物質とは異なる導電性物質
を主たる導体パターンの少なくとも一部表面に形成する
ためのレジストマスクを形成する工程。
（ｇ）前記レジストマスクをめっきマスクにして電解め
っきを行い、めっき用導通リードで接続された主たる導
体層の一部表面に主たる導体層構成物質とは異なる導電
性物質被膜を形成する工程。
（ｈ）前記レジストマスクを専用の剥離液で除去し、前
記めっき用導通リードをエッチングで除去する工程。
（ｉ）基板上にソルダーレジストパターンを形成する工
程。Further, in claim 6, at least the following steps are provided.
The method for manufacturing a semiconductor device substrate according to any one of items 1 to 3. (A) A step of forming main conductor layers on both surfaces of the insulating substrate. (B) A step of patterning the main conductor layer to form a main conductor pattern. (C) A step of forming a resist pattern having an opening region at a predetermined position on the insulating substrate and the main conductor pattern. (D) A step of electrically conducting the opening region. (E) A step of stripping the resist mask with a dedicated stripping solution, performing electroless and electrolytic copper plating, and forming a conductive lead for plating made of a conductor layer according to the opening region subjected to the conductivity treatment. (F) A step of forming a resist mask for forming a conductive substance different from the main conductor layer constituent substance on at least a part of the surface of the main conductor pattern. (G) A step of performing electrolytic plating by using the resist mask as a plating mask to form a conductive material film different from the main conductor layer constituent material on a part of the surface of the main conductor layer connected by the conductive lead for plating. (H) A step of removing the resist mask with a dedicated stripping solution and removing the plating conductive leads by etching. (I) A step of forming a solder resist pattern on the substrate.
【００１４】[0014]
【発明の実施の形態】請求項１〜３に係わる本発明の半
導体装置用基板は図１（ａ）及び（ｂ）に示すように、
絶縁基板１１の両面に配線層１２を有するコア基板１０
に樹脂フィルムを積層して絶縁層２１が形成されてお
り、配線パターン３１は従たる導体パターン２３ａ及び
主たる導体パターン２５ａの２層構成で形成されてお
り、配線パターン３１の主たる導体層２５一部表面が主
たる導体層構成物質とは異なる導電性物質２９で覆われ
ており、少なくとも配線パターンの一つ以上が他の配線
パターンから電気的に絶縁されている。主たる導体層２
５は、銅を主成分とする導電性物質で、従たる導体層２
３は、銅もしくは銅以外の導電性物質で、主たる導体層
構成物質とは異なる導電性物質２９は、主たる導体層２
５とは異なるニッケル、パラジウム、金、白金、ロジウ
ム、銀及び錫のうち少なくとも１種類からなる導電性物
質でそれぞれ形成されており、さらに、１００μｍピッ
チ以下の微細かつ高密度な配線パターン３１から構成さ
れ、ソルダーレジストパターン３２が形成されている。
ここで、半導体装置用基板は、４層配線板の事例につい
て説明したが、これに限定されるものではなく、両面配
線板、４層以上の配線板にも適用可能である。BEST MODE FOR CARRYING OUT THE INVENTION A substrate for a semiconductor device of the present invention according to claims 1 to 3 is as shown in FIGS. 1 (a) and 1 (b).
Core board 10 having wiring layers 12 on both sides of insulating board 11
An insulating layer 21 is formed by laminating a resin film on the wiring pattern 31, and the wiring pattern 31 is formed of a two-layer structure of a subordinate conductor pattern 23a and a main conductor pattern 25a. A part of the main conductor layer 25 of the wiring pattern 31 is formed. The surface is covered with a conductive substance 29 different from the main conductor layer constituent substance, and at least one or more wiring patterns are electrically insulated from other wiring patterns. Main conductor layer 2
Reference numeral 5 denotes a conductive material containing copper as a main component, which is a subordinate conductor layer 2
3 is copper or a conductive substance other than copper, and the conductive substance 29 different from the main conductor layer constituent substance is the main conductor layer 2
5, a conductive material made of at least one of nickel, palladium, gold, platinum, rhodium, silver, and tin, each of which is composed of a fine and high-density wiring pattern 31 having a pitch of 100 μm or less. Thus, the solder resist pattern 32 is formed.
Here, the semiconductor device substrate has been described with respect to a case of a four-layer wiring board, but the present invention is not limited to this, and it is also applicable to a double-sided wiring board and a wiring board having four or more layers.
【００１５】以下、請求項４に係わる本発明の半導体装
置用基板の製造方法について説明する。図２〜図７に本
発明の半導体装置用基板の製造工程の一実施例を工程順
に示す模式平面図及び模式構成断面図をそれぞれ示す。
まず、絶縁基板１１の両面に配線層１２を有するコア基
板１０に樹脂フィルムを積層して絶縁層２１を形成する
（図２（ａ−１）及び（ａ−２）参照）。ここで、図２
（ａ−１）〜（ｎ−１）は途中工程の模式平面図、図２
（ａ−２）〜（ｎ−２）は平面図をＡ−Ａ’線で切断し
た模式構成断面図で、以下模式構成断面図は片側のみの
表示とする。A method of manufacturing a semiconductor device substrate according to the fourth aspect of the present invention will be described below. 2 to 7 are respectively a schematic plan view and a schematic cross-sectional view showing an embodiment of the steps for manufacturing a semiconductor device substrate of the present invention in the order of steps.
First, a resin film is laminated on the core substrate 10 having the wiring layers 12 on both sides of the insulating substrate 11 to form the insulating layer 21 (see FIGS. 2A-1 and 2A-2). Here, FIG.
2 (a-1) to (n-1) are schematic plan views of an intermediate step, FIG.
(A-2) to (n-2) are schematic configuration cross-sectional views obtained by cutting the plan view along the line AA ′, and the schematic configuration cross-sectional views are shown only on one side below.
【００１６】次に、絶縁層２１を介して配線層１２と電
気的接続を行うビアホールを形成するためのビア用孔２
２を絶縁層２１の所定位置にレーザー加工等にて形成す
る（図２（ｂ−１）及び（ｂ−２）参照）。次に、無電
解銅めっきにて絶縁層２１上及びビア用孔２２側面に所
定厚の従たる導体層２３を形成する（図３（ｃ−２）参
照）。Next, a via hole 2 for forming a via hole for electrically connecting to the wiring layer 12 through the insulating layer 21.
2 is formed at a predetermined position on the insulating layer 21 by laser processing or the like (see FIGS. 2B-1 and 2B-2). Next, a subordinate conductor layer 23 having a predetermined thickness is formed on the insulating layer 21 and on the side surface of the via hole 22 by electroless copper plating (see FIG. 3C-2).
【００１７】次に、基板全面に感光性樹脂を塗布する
か、もしくはドライフィルムを貼り付けて感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行って、配線パターンをセミアディティブ方式で作製す
るためのレジストパターン２４を従たる導体層上２３上
に形成する（図３（ｄ−１）及び（ｄ−２）参照）。次
に、基板の周囲から導通をとって、レジストパターン２
４をめっきマスクにして電解銅めっきを行い、主たる導
体層２５、主たる導体パターン２５ａ及びビアホール２
６を形成する（図３（ｅ−２）参照）。Next, a photosensitive resin is applied to the entire surface of the substrate or a dry film is attached to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form a wiring pattern in a semi-additive system. Then, the resist pattern 24 to be manufactured in step 1 is formed on the subordinate conductor layer 23 (see FIGS. 3D-1 and 3D-2). Next, the resist pattern 2 is made conductive from the periphery of the substrate.
4 is used as a plating mask to perform electrolytic copper plating to form a main conductor layer 25, a main conductor pattern 25a, and a via hole 2.
6 is formed (see FIG. 3E-2).
【００１８】次に、レジストパターン２４を専用の剥離
液で剥離し（図３（ｆ−２）参照）、さらに、従たる導
体層２３及び主たる導体層上の所定位置にめっき用導通
リードを形成するためのレジストパターン２７を形成す
る（図４（ｇ−１）及び（ｇ−２）参照）。次に、レジ
ストパターン２７をエッチングマスクにして従たる導体
層２３をエッチングし（図４（ｈ−２）参照）、レジス
トパターン２７を専用の剥離液で剥離し、めっき用導通
リード２３ｂ及び主たる導体パターン２５ａと従たる導
体パターン２３ａが形成された配線パターン３１を形成
する（図５（ｉ−１）及び（ｉ−２）参照）。Next, the resist pattern 24 is peeled off with a dedicated peeling liquid (see FIG. 3 (f-2)), and further conductive leads for plating are formed at predetermined positions on the subordinate conductor layer 23 and the main conductor layer. A resist pattern 27 for forming is formed (see FIGS. 4G-1 and 4G-2). Next, by using the resist pattern 27 as an etching mask, the subordinate conductor layer 23 is etched (see FIG. 4 (h-2)), the resist pattern 27 is stripped with a dedicated stripping solution, and the plating conductive lead 23b and the main conductor are removed. The wiring pattern 31 in which the pattern 25a and the subordinate conductor pattern 23a are formed is formed (see FIGS. 5 (i-1) and (i-2)).
【００１９】次に、配線パターン３１の主たる導体層２
５の一部表面に電解めっきにてニッケル、パラジウム、
金、白金、ロジウム、銀及び錫のうち少なくとも１種類
からなる導電性物質被膜を形成するためのめっき用レジ
ストパターン２８を形成する（図５（ｊ−１）及び（ｊ
−２）参照）。ここで、めっき用導通リード２３ｂ及び
配線パターン３１はレジストパターン２８で覆われて導
電性物質被膜２９が付かないようにしてある。Next, the main conductor layer 2 of the wiring pattern 31.
Electrolytic plating of nickel, palladium,
A plating resist pattern 28 for forming a conductive material film made of at least one of gold, platinum, rhodium, silver and tin is formed (FIGS. 5 (j-1) and (j)).
-2)). Here, the conductive lead 23b for plating and the wiring pattern 31 are covered with the resist pattern 28 so that the conductive material film 29 is not attached.
【００２０】次に、基板の周囲から導通をとって電解め
っきを行い、配線パターン３１の主たる導体層２５の一
部表面にニッケル、パラジウム、金、白金、ロジウム、
銀及び錫のうち少なくとも１種類からなる導電性物質被
膜２９を形成する（図６（ｋ−２）参照）。ここで、導
電性物質被膜２９としては通常金被膜が用いられる。次
に、めっき用レジストパターン２８を専用の剥離液で剥
離し（図６（ｌ−１）及び（ｌ−２）参照）、めっき用
導通リード２３ｂをフラッシュエッチングで除去し、配
線パターン３１相互が電気的に絶縁され、ビアホール２
６にて配線層１２と電気的に接続された半導体装置用基
板を得る（図７（ｍ−１）及び（ｍ−２）参照）。ここ
で、予め導電性物質被膜２９の表面にレジストを被せて
保護レジストを形成し、めっき用導通リード２３ｂを除
去後に前記保護用レジストを剥離する工程としても良
い。さらに、ソルダーレジストパターン３２を形成し
て、配線パターン３１がソルダーレジストにて保護、絶
縁された本発明の半導体装置用基板を得る（図７（ｎ−
１）及び（ｎ−２）参照）。Next, electroplating is performed by establishing electrical conduction from the periphery of the substrate, and nickel, palladium, gold, platinum, rhodium, on the partial surface of the main conductor layer 25 of the wiring pattern 31,
A conductive material film 29 made of at least one of silver and tin is formed (see FIG. 6 (k-2)). Here, a gold coating is usually used as the conductive material coating 29. Next, the plating resist pattern 28 is stripped with a dedicated stripping solution (see FIGS. 6 (l-1) and (l-2)), the plating conductive lead 23b is removed by flash etching, and the wiring patterns 31 are mutually separated. Electrically isolated, via hole 2
A semiconductor device substrate electrically connected to the wiring layer 12 at 6 is obtained (see FIGS. 7 (m-1) and (m-2)). Here, a step of forming a protective resist by covering the surface of the conductive substance coating film 29 in advance and removing the protective resist after removing the conductive lead for plating 23b may be performed. Furthermore, a solder resist pattern 32 is formed to obtain a semiconductor device substrate of the present invention in which the wiring pattern 31 is protected and insulated by the solder resist (FIG. 7 (n-
1) and (n-2)).
【００２１】以下、請求項５に係わる本発明の半導体装
置用基板の製造方法について説明する。図１０〜図１１
に半導体装置用基板の製造工程の一実施例を工程順に示
す模式構成断面図を示す。まず、絶縁基板１１の両面に
配線層１２を有するコア基板１０に樹脂フィルム付き銅
箔を積層して絶縁層７１及び導体層７２を形成する（図
１０（ａ）参照）。次に、導体層７２をパターニング処
理して、開口部７３を形成する（図１０（ｂ）参照）。A method of manufacturing a semiconductor device substrate according to the fifth aspect of the present invention will be described below. 10 to 11
2A to 2D are schematic cross-sectional views showing an example of the steps of manufacturing a semiconductor device substrate in the order of steps. First, a copper foil with a resin film is laminated on the core substrate 10 having the wiring layers 12 on both sides of the insulating substrate 11 to form the insulating layer 71 and the conductor layer 72 (see FIG. 10A). Next, the conductor layer 72 is patterned to form the opening 73 (see FIG. 10B).
【００２２】次に、開口部７３にレーザービームを照射
し、絶縁層７１にビア用孔７４を形成する（図１０
（ｃ）参照）。次に、ビア用孔７４を導電化処理して、
電解銅めっき等にてビア用孔７４にビアホール７５を、
導体層７２上に所定厚の導体層をめっきして主たる導体
層７６を形成する（図１０（ｄ）参照）。Next, the opening 73 is irradiated with a laser beam to form a via hole 74 in the insulating layer 71 (FIG. 10).
(See (c)). Next, the via hole 74 is subjected to a conductive treatment,
A via hole 75 is formed in the via hole 74 by electrolytic copper plating or the like.
A conductor layer having a predetermined thickness is plated on the conductor layer 72 to form a main conductor layer 76 (see FIG. 10D).
【００２３】次に、主たる導体層７６をパターニング処
理して、主たる導体パターン７６ａを形成する（図１０
（ｅ）参照）。次に、絶縁層７１及び主たる導体パター
ン７６ａ上に無電解銅めっき及び電解銅めっきを行い、
従たる導体層７７を形成する（図１０（ｆ）参照）。Next, the main conductor layer 76 is patterned to form a main conductor pattern 76a (FIG. 10).
(See (e)). Next, electroless copper plating and electrolytic copper plating are performed on the insulating layer 71 and the main conductor pattern 76a,
The subordinate conductor layer 77 is formed (see FIG. 10F).
【００２４】次に、従たる導体層７７上に感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行い、従たる導体層７７の所定位置にレジストパターン
７８を形成する（図１０（ｇ）参照）。Next, a photosensitive layer is formed on the subordinate conductor layer 77, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 78 at a predetermined position on the subordinate conductor layer 77 (FIG. 10). (See (g)).
【００２５】次に、レジストパターン７８をマスクにし
て従たる導体層７７をエッチングし（図１１（ｈ）参
照）、レジストパターン７８を専用の剥離液で剥離し、
電気的に絶縁された主たる導体パターンを電気的に接続
するためのめっき用導通リード７７ａを形成する（図１
１（ｉ）参照）。Next, the subordinate conductor layer 77 is etched by using the resist pattern 78 as a mask (see FIG. 11 (h)), and the resist pattern 78 is peeled off by a dedicated peeling solution.
A conductive lead 77a for plating is formed for electrically connecting the electrically insulated main conductor pattern (FIG. 1).
1 (i)).
【００２６】次に、主たる導体パターン７６ａの一部表
面に電解めっきにてニッケル、パラジウム、金、白金、
ロジウム、銀及び錫のうち少なくとも１種類からなる導
電性物質被膜を形成するためのめっき用レジストパター
ン７９を形成する（図１１（ｊ）参照）。Next, a part of the surface of the main conductor pattern 76a is electrolytically plated with nickel, palladium, gold, platinum,
A resist pattern 79 for plating for forming a conductive material film made of at least one of rhodium, silver and tin is formed (see FIG. 11 (j)).
【００２７】次に、基板の周囲から導通をとって電解め
っきを行い、主たる導体パターン７６ａの一部表面にニ
ッケル、パラジウム、金、白金、ロジウム、銀及び錫の
うち少なくとも１種類からなる導電性物質被膜８１を形
成する（図１１（ｋ）参照）。ここで、導電性物質被膜
８１としては通常金被膜が用いられる。Next, electroplating is performed by establishing conduction from the periphery of the substrate, and a conductive surface made of at least one of nickel, palladium, gold, platinum, rhodium, silver and tin is formed on a part of the surface of the main conductor pattern 76a. A material coating 81 is formed (see FIG. 11 (k)). Here, a gold coating is usually used as the conductive material coating 81.
【００２８】次に、めっき用レジストパターン７９を専
用の剥離液で剥離し（図１１（ｌ）参照）、めっき用導
通リード７７ａをフラッシュエッチングで除去し、主た
る導体パターン７６ａ相互が電気的に絶縁され、ビアホ
ール７５にて配線層１２と電気的に接続された半導体装
置用基板を得る（図１１（ｍ）参照）。さらに、ソルダ
ーレジストパターン８２を形成して、主たる導体パター
ン７６ａがソルダーレジストにて保護、絶縁された半導
体装置用基板を得る（図１１（ｎ）参照）。Next, the plating resist pattern 79 is stripped with a dedicated stripping solution (see FIG. 11 (l)), the plating conductive lead 77a is removed by flash etching, and the main conductor patterns 76a are electrically insulated from each other. Then, a semiconductor device substrate electrically connected to the wiring layer 12 through the via hole 75 is obtained (see FIG. 11 (m)). Further, a solder resist pattern 82 is formed to obtain a semiconductor device substrate in which the main conductor pattern 76a is protected and insulated by the solder resist (see FIG. 11 (n)).
【００２９】以下、請求項６に係わる本発明の半導体装
置用基板の製造方法について説明する。図１２〜図１３
に半導体装置用基板の製造工程の一実施例を工程順に示
す模式構成断面図を示す。まず、絶縁基板１１の両面に
配線層１２を有するコア基板１０に樹脂フィルム付き銅
箔を積層して絶縁層７１及び導体層７２を形成し、導体
層７２をパターニング処理して、開口部７３を形成する
（図１２（ａ）〜（ｂ）参照）。A method of manufacturing a semiconductor device substrate according to the sixth aspect of the present invention will be described below. 12 to 13
2A to 2D are schematic cross-sectional views showing an example of the steps of manufacturing a semiconductor device substrate in the order of steps. First, a copper foil with a resin film is laminated on the core substrate 10 having the wiring layers 12 on both sides of the insulating substrate 11 to form the insulating layer 71 and the conductor layer 72, and the conductor layer 72 is patterned to form the opening 73. It is formed (see FIGS. 12A and 12B).
【００３０】次に、開口部７３にレーザービームを照射
し、絶縁層７１にビア用孔７４を形成し、ビア用孔７４
を導電化処理して、電解銅めっき等にてビア用孔７４に
ビアホール７５を、導体層７２上に所定厚の導体層をめ
っきして主たる導体層７６を形成する（図１２（ｃ）〜
（ｄ）参照）。Next, the opening 73 is irradiated with a laser beam to form a via hole 74 in the insulating layer 71, and the via hole 74 is formed.
Is subjected to a conductive treatment to form a via hole 75 in the via hole 74 by electrolytic copper plating or the like, and a main conductor layer 76 is formed by plating a conductor layer of a predetermined thickness on the conductor layer 72 (FIG. 12 (c)-
(See (d)).
【００３１】次に、主たる導体層７６をパターニング処
理して、主たる導体パターン７６ａを形成する（図１２
（ｅ）参照）。Next, the main conductor layer 76 is patterned to form a main conductor pattern 76a (FIG. 12).
(See (e)).
【００３２】次に、絶縁層７１及び主たる導体パターン
７６ａ上に感光層を形成し、パターン露光、現像等の一
連のパターニング処理を行い、所定位置に開口領域９２
を有するレジストパターン９１を形成する（図１２
（ｆ）参照）。Next, a photosensitive layer is formed on the insulating layer 71 and the main conductor pattern 76a, and a series of patterning processes such as pattern exposure and development are performed, and an opening region 92 is formed at a predetermined position.
Forming a resist pattern 91 having
(See (f)).
【００３３】次に、開口領域９２を導電化処理し、レジ
ストパターン９１を専用の剥離液で剥離し、無電解、電
解銅めっきを行い、導電化処理された開口領域９２に従
たる導体層からなるめっき用導通リード９３を形成する
（図１２（ｇ）参照）。Next, the opening region 92 is made conductive, the resist pattern 91 is stripped with a dedicated stripping solution, electroless and electrolytic copper plating is performed, and the conductive layer corresponding to the conductive-processed opening region 92 is removed. A conductive lead 93 for plating is formed (see FIG. 12 (g)).
【００３４】次に、主たる導体パターン７６ａの一部表
面に電解めっきにてニッケル、パラジウム、金、白金、
ロジウム、銀及び錫のうち少なくとも１種類からなる導
電性物質被膜を形成するためのめっき用レジストマスク
９４を形成する（図１３（ｈ）参照）。Next, a part of the surface of the main conductor pattern 76a is electrolytically plated with nickel, palladium, gold, platinum,
A plating resist mask 94 for forming a conductive material film made of at least one of rhodium, silver and tin is formed (see FIG. 13 (h)).
【００３５】次に、基板の周囲から導通をとって電解め
っきを行い、主たる導体パターン７６ａの一部表面にニ
ッケル、パラジウム、金、白金、ロジウム、銀及び錫の
うち少なくとも１種類からなる導電性物質被膜９５を形
成する（図１３（ｉ）参照）。ここで、導電性物質被膜
９５としては通常金被膜が用いられる。Next, electroplating is performed by establishing electrical conduction from the periphery of the substrate, and a conductive surface made of at least one of nickel, palladium, gold, platinum, rhodium, silver and tin is formed on a part of the surface of the main conductor pattern 76a. A material film 95 is formed (see FIG. 13 (i)). Here, a gold coating is usually used as the conductive material coating 95.
【００３６】次に、めっき用レジストマスク９４を専用
の剥離液で剥離し（図１３（ｊ）参照）、めっき用導通
リード９３をフラッシュエッチングで除去し、主たる導
体パターン７６ａ相互が電気的に絶縁され、ビアホール
７５にて配線層１２と電気的に接続された半導体装置用
基板を得る（図１３（ｋ）参照）。さらに、ソルダーレ
ジストパターン９６を形成して、主たる導体パターン７
６ａがソルダーレジストにて保護、絶縁された半導体装
置用基板を得る（図１３（ｌ）参照）。Next, the plating resist mask 94 is stripped with a dedicated stripping solution (see FIG. 13 (j)), the plating conductive leads 93 are removed by flash etching, and the main conductor patterns 76a are electrically insulated from each other. Thus, a semiconductor device substrate electrically connected to the wiring layer 12 through the via hole 75 is obtained (see FIG. 13K). Further, a solder resist pattern 96 is formed to form the main conductor pattern 7
A semiconductor device substrate having 6a protected and insulated by a solder resist is obtained (see FIG. 13 (l)).
【００３７】[0037]
【実施例】以下実施例により本発明を詳細に説明する。
＜実施例１＞請求項４に係わる半導体装置基板の製造方
法の一実施例である。まず、絶縁基板１１の両面に配線
層１２を形成したコア基板１０に、絶縁層２１及び極薄
銅箔（厚み約３μｍ、三井金属製）（特に図示せず）が
形成された４層板を準備した（図２（ａ−１）及び（ａ
−２）参照）。次に、絶縁層２１の所定位置にＵＶレー
ザー（ＭＬ６０５ＬＤＸ、三菱電機製）にて穴明け加工
し、８０μｍφのビア用孔２２を形成し、過マンガン酸
処理で樹脂表面を粗化した（図２（ｂ−１）及び（ｂ−
２）参照）。次に、無電解銅めっき及び電解銅めっきを
行って、絶縁層２１上に３〜４μｍ厚の銅の薄膜からな
る従たる導体層２３を形成した（図３（ｃ−２）参
照）。The present invention will be described in detail with reference to the following examples. <Embodiment 1> This is an embodiment of the method of manufacturing a semiconductor device substrate according to claim 4. First, a four-layer board having an insulating layer 21 and an ultra-thin copper foil (thickness of about 3 μm, made by Mitsui Metal Co., Ltd.) (not particularly shown) is formed on a core substrate 10 having wiring layers 12 formed on both sides of an insulating substrate 11. Prepared (Fig. 2 (a-1) and (a
-2)). Next, a hole was formed at a predetermined position of the insulating layer 21 by a UV laser (ML605LDX, manufactured by Mitsubishi Electric) to form a via hole 22 of 80 μmφ, and the resin surface was roughened by a permanganate treatment (FIG. 2). (B-1) and (b-
See 2)). Next, electroless copper plating and electrolytic copper plating were performed to form a sub conductor layer 23 made of a copper thin film having a thickness of 3 to 4 μm on the insulating layer 21 (see FIG. 3C-2).
【００３８】次に、従たる導体層２３を整面後、厚み３
０μｍのドライフィルムを貼り合せて感光層を形成し、
パターン露光、現像等の一連のパターニング処理を行っ
て、レジストパターン２４を形成した（図３（ｄ−１）
及び（ｄ−２）参照）。次に、レジストパターン２４を
めっきマスクにして電解銅めっきを行い、約２５μｍ厚
の主たる導体層２５、主たる導体パターン２５ａ及びビ
アホール２６を形成した（図３（ｅ−２）参照）。さら
に、専用の剥離液でレジストパターン２４を除去した
（図３（ｆ−２）参照）。Next, after the surface of the subordinate conductor layer 23 is adjusted, the thickness 3 is obtained.
A 0 μm dry film is attached to form a photosensitive layer,
A series of patterning treatments such as pattern exposure and development were performed to form a resist pattern 24 (FIG. 3D-1).
And (d-2)). Next, electrolytic copper plating was performed using the resist pattern 24 as a plating mask to form a main conductor layer 25, a main conductor pattern 25a and a via hole 26 having a thickness of about 25 μm (see FIG. 3 (e-2)). Further, the resist pattern 24 was removed with a dedicated stripping solution (see FIG. 3 (f-2)).
【００３９】次に、液状レジスト（ＰＭＥＲ Ｎ−ＨＣ
４０（商品名）、東京応化製）を塗布して感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行い、７０℃で２０分乾燥してレジストパターン２７を
形成した（図４（ｇ−１）及び（ｇ−２）参照）。次
に、硫酸−加水系エッチング液（ＣＰＢ−６０（商品
名）、三菱ガス化学製）に３０秒から１分間浸漬し、レ
ジストパターン２７をエッチングマスクにして表面に露
出した従たる導体層２３をエッチングし、除去した（図
４（ｈ−２）参照）。次に、５０℃に加熱した１％水酸
化ナトリウム溶液でレジストパターン２７を剥離し、め
っき用導通リード２３ｂ及び主たる導体パターン２５ａ
と従たる導体パターン２３ａからなる配線パターン３１
を形成した（図５（ｉ−１）及び（ｉ−２）参照）。Next, a liquid resist (PMER N-HC
40 (trade name) manufactured by Tokyo Ohka Co., Ltd. is applied to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed, followed by drying at 70 ° C. for 20 minutes to form a resist pattern 27 (FIG. 4). (See (g-1) and (g-2)). Next, the secondary conductor layer 23 exposed on the surface is immersed in a sulfuric acid-hydrolyzed etching solution (CPB-60 (trade name), manufactured by Mitsubishi Gas Chemical Co., Ltd.) for 30 seconds to 1 minute to use the resist pattern 27 as an etching mask. It was etched and removed (see FIG. 4 (h-2)). Next, the resist pattern 27 is peeled off with a 1% sodium hydroxide solution heated to 50 ° C., and the conductive lead for plating 23b and the main conductor pattern 25a.
Wiring pattern 31 consisting of the following conductive pattern 23a
Was formed (see FIGS. 5 (i-1) and (i-2)).
【００４０】次に、金めっき液耐性のあるドライフィル
ム（ニチゴーモートン製）を貼り合せて感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行って、めっき用レジストパターン２８を形成した（図
５（ｊ−１）及び（ｊ−２）参照）。次に、基板の周囲
から導通をとって電解ニッケルめっき及び電解金めっき
を順に行い、主たる導体層２５の一部表面に厚み約５μ
ｍのニッケル皮膜及び厚み約０．５μｍの金皮膜からな
る導電性物質被膜２９を形成した（図５（ｋ−２）参
照）。Next, a dry film (manufactured by Nichigo Morton) resistant to a gold plating solution is attached to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form a plating resist pattern 28. (See FIGS. 5 (j-1) and (j-2)). Next, electrolytic nickel plating and electrolytic gold plating are carried out in order from the periphery of the substrate so as to have a thickness of about 5 μm on a part of the surface of the main conductor layer 25.
A conductive substance film 29 composed of a nickel film of m and a gold film of about 0.5 μm was formed (see FIG. 5 (k-2)).
【００４１】次に、アルカリ溶液でレジストパターン２
８を剥離し（図６（ｌ−１）及び（ｊ−２）参照）、さ
らに、硫酸−加水系エッチング液（ＣＰＢ−６０（商品
名）、三菱ガス化学製）の新液に３０秒から１分間浸漬
して、めっき用導通リード２３ｂを除去し、半導体装置
用基板を得た（図７（ｍ−１）及び（ｍ−２）参照）。
最後に、ソルダーレジスト（ＰＳＲ−４０００ ＡＵＳ
５（商品名）、太陽インキ製）を印刷してソルダーレジ
スト感光層を形成し、パターン露光、現像等の一連のパ
ターニング処理を行って、ソルダーレジストパターン３
２を形成し、外形加工を行って、配線パターンピッチ７
０μｍで電解金めっき仕様の半導体装置用基板を得た
（図７（ｎ−１）及び（ｎ−２）参照）。Next, a resist pattern 2 is formed with an alkaline solution.
8 was peeled off (see FIGS. 6 (l-1) and (j-2)), and a new solution of sulfuric acid-hydrolyzed etching solution (CPB-60 (trade name), manufactured by Mitsubishi Gas Chemical Co., Inc.) was added for 30 seconds. The substrate was soaked for 1 minute to remove the plating conductive lead 23b to obtain a semiconductor device substrate (see FIGS. 7 (m-1) and (m-2)).
Finally, solder resist (PSR-4000 AUS
5 (trade name), manufactured by Taiyo Ink Co., Ltd., to form a solder resist photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to obtain a solder resist pattern 3
2 is formed, the outer shape is processed, and the wiring pattern pitch is 7
A substrate for a semiconductor device having an electroplating specification of 0 μm was obtained (see FIGS. 7 (n-1) and (n-2)).
【００４２】＜実施例２＞請求項４に係わる半導体装置
基板の製造方法の他の実施例である。まず、絶縁基板１
１の両面に配線層１２を形成したコア基板１０に、フィ
ルム状樹脂（ＡＢＦ−７５（商品名）、味の素ファイン
テクノ製）を真空ラミネーターで両面に貼り合せ、１４
０℃で３０分間ポストキュアを行い絶縁層５１を形成し
た（図８（ａ）参照）。次に、絶縁層５１の所定位置に
ＵＶレーザー（ＭＬ６０５ＬＤＸ（商品名）、三菱電機
製）にて穴明け加工し、８０μｍφのビア用孔５２を形
成し、過マンガン酸処理で樹脂表面を粗化した（図８
（ｂ）参照）。次に、無電解銅めっき及び電解銅めっき
を行って、絶縁層５１上及びビア用孔５２側面に約２〜
３μｍ厚の銅の薄膜からなる従たる導体層５３を形成し
た（図８（ｃ）参照）。<Embodiment 2> Another embodiment of the method of manufacturing a semiconductor device substrate according to claim 4 is described. First, the insulating substrate 1
1. A film-like resin (ABF-75 (trade name), manufactured by Ajinomoto Fine-Techno Co., Inc.) was attached to both sides of the core substrate 10 on which wiring layers 12 were formed on both sides with a vacuum laminator.
Post-curing was performed at 0 ° C. for 30 minutes to form the insulating layer 51 (see FIG. 8A). Next, a hole is processed at a predetermined position of the insulating layer 51 with a UV laser (ML605LDX (trade name), manufactured by Mitsubishi Electric) to form a via hole 52 of 80 μmφ, and the resin surface is roughened by permanganate treatment. (Fig. 8
(See (b)). Next, electroless copper plating and electrolytic copper plating are performed to form about 2 to 2 on the insulating layer 51 and the side surface of the via hole 52.
A sub conductor layer 53 made of a copper thin film having a thickness of 3 μm was formed (see FIG. 8C).
【００４３】次に、従たる導体層５３を整面後、ロール
コーターでポジ型液状レジストをコーティングして感光
層を形成し、パターン露光、現像等の一連のパターニン
グ処理を行って、レジストパターン５４を形成した（図
８（ｄ）参照）。次に、レジストパターン５４をめっき
マスクにして電解銅めっきを行い、約２５μｍ厚の主た
る導体層５５、主たる導体パターン５５ａ及びビアホー
ル５６を形成した（図８（ｅ）参照）。Next, after the surface of the subordinate conductor layer 53 is adjusted, a positive type liquid resist is coated with a roll coater to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are carried out to form a resist pattern 54. Was formed (see FIG. 8D). Next, electrolytic copper plating was performed using the resist pattern 54 as a plating mask to form a main conductor layer 55, a main conductor pattern 55a, and a via hole 56 having a thickness of about 25 μm (see FIG. 8E).
【００４４】次に、再びロールコーターでポジ型液状レ
ジストをコーティングして感光層を形成し、パターン露
光、現像等の一連のパターニング処理を行って、めっき
用導通リード及び配線パターンを形成するためのレジス
トパターン５７を形成した（図８（ｆ）参照）。次に、
硫酸−加水系エッチング液（ＣＰＢ−６０（商品名）、
三菱ガス化学製）に３０秒から１分間浸漬し、レジスト
パターン５７をエッチングマスクにして、露出した主た
る導体層５５及び従たる導体層５３をエッチングし、除
去した（図８（ｇ）参照）。Next, a positive type liquid resist is again coated with a roll coater to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form conductive leads for plating and wiring patterns. A resist pattern 57 was formed (see FIG. 8 (f)). next,
Sulfuric acid-hydrolyzed etching solution (CPB-60 (trade name),
Mitsubishi Gas Chemical Co., Ltd.) for 30 seconds to 1 minute, and using the resist pattern 57 as an etching mask, the exposed main conductor layer 55 and the subordinate conductor layer 53 were etched and removed (see FIG. 8G).
【００４５】次に、有機アミン系アルカリ溶液でレジス
トパターン５７を剥離し、主たる導体パターン５５ａ及
び従たる導体パターン５３ａからなる配線パターン６１
及びめっき用導通リード５３ｂを形成した（図９（ｈ）
参照）。Next, the resist pattern 57 is peeled off with an organic amine-based alkaline solution, and a wiring pattern 61 consisting of a main conductor pattern 55a and a sub conductor pattern 53a.
And conductive leads 53b for plating were formed (FIG. 9 (h)).
reference).
【００４６】次に、金めっき液耐性のあるドライフィル
ム（ニチゴーモートン製）を貼り合せて感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行って、電解めっき用のレジストパターン５８を形成し
た（図９（ｉ）参照）。次に、基板の周囲から導通をと
って電解ニッケルめっき及び電解金めっきを順に行い、
主たる導体層２５の一部表面に厚み約５μｍのニッケル
皮膜及び厚み約０．５μｍの金皮膜からなる導電性物質
被膜５９を形成した（図９（ｊ）参照）。Next, a dry film (made by Nichigo Morton) having resistance to a gold plating solution is bonded to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a resist pattern 58 for electrolytic plating. Were formed (see FIG. 9 (i)). Next, electrolytic nickel plating and electrolytic gold plating are performed in order by taking electrical continuity from around the substrate,
A conductive material film 59 composed of a nickel film having a thickness of about 5 μm and a gold film having a thickness of about 0.5 μm was formed on a part of the surface of the main conductor layer 25 (see FIG. 9 (j)).
【００４７】次に、アルカリ溶液でレジストパターン５
８を剥離し（図９（ｋ）参照）、さらに、硫酸−加水系
エッチング液（ＣＰＢ−６０（商品名）、三菱ガス化学
製）の新液に３０秒から１分間浸漬して、めっき用導通
リード５３ｂを除去し、半導体装置用基板を得た（図９
（ｌ）参照）。最後に、ソルダーレジスト（ＰＳＲ−４
０００ ＡＵＳ７（商品名）、太陽インキ製）を印刷し
てソルダーレジスト感光層を形成し、パターン露光、現
像等の一連のパターニング処理を行って、ソルダーレジ
ストパターン６２を形成し、外形加工を行って、配線パ
ターンピッチ４０μｍで電解金めっき仕様の半導体装置
用基板を得た（図９（ｍ）参照）。Next, a resist pattern 5 is formed with an alkaline solution.
8 is peeled off (see FIG. 9 (k)), and further immersed in a new solution of a sulfuric acid-hydrogen-based etching solution (CPB-60 (trade name), manufactured by Mitsubishi Gas Chemical Co., Ltd.) for 30 seconds to 1 minute for plating. The conductive lead 53b was removed to obtain a semiconductor device substrate (FIG. 9).
(See (l)). Finally, solder resist (PSR-4
000 AUS7 (trade name), made by TAIYO INK) is printed to form a solder resist photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form a solder resist pattern 62, and external processing is performed. A substrate for a semiconductor device having electrolytic gold plating specifications with a wiring pattern pitch of 40 μm was obtained (see FIG. 9 (m)).
【００４８】＜実施例３＞請求項４に係わる半導体装置
基板の製造方法の他の実施例である。まず、絶縁基板１
１の両面に配線層１２を形成したコア基板１０に、外層
に厚み３５μｍの銅キャリア付きレーザー加工用極薄銅
箔（厚み約３μｍ、三井金属製）を積層した４層板の銅
キャリアを剥離して絶縁層５１及び極薄銅箔（特に図示
せず）が形成された４層板を準備した（図８（ａ）参
照）。次に、絶縁層５１及び極薄銅箔の所定位置に炭酸
ガスレーザー（ＭＬ５０５ＧＴ（商品名）、三菱電機
製）にて穴明け加工し、１５０μｍφのビア用孔５２を
形成した（図８（ｂ）参照）。次に、無電解銅めっき及
び電解銅めっきを行って、絶縁層５１上及びビア用孔５
２側面に約２〜４μｍ厚の銅の薄膜からなる従たる導体
層５３を形成した（図８（ｃ）参照）。<Embodiment 3> Another embodiment of the method of manufacturing a semiconductor device substrate according to claim 4 is described. First, the insulating substrate 1
The core carrier 10 on which wiring layers 12 are formed on both sides of No. 1 is a four-layered copper carrier having an outer layer laminated with an ultrathin copper foil with a copper carrier having a thickness of 35 μm for laser processing (thickness about 3 μm, made by Mitsui Kinzoku) Then, a four-layer plate on which the insulating layer 51 and the ultra-thin copper foil (not shown) were formed was prepared (see FIG. 8A). Next, holes were formed at predetermined positions of the insulating layer 51 and the ultra-thin copper foil with a carbon dioxide gas laser (ML505GT (trade name), manufactured by Mitsubishi Electric) to form via holes 52 of 150 μmφ (FIG. 8 (b). )reference). Next, electroless copper plating and electrolytic copper plating are performed so that the insulating layer 51 and the via holes 5 are formed.
A sub conductor layer 53 made of a copper thin film having a thickness of about 2 to 4 μm was formed on the two side surfaces (see FIG. 8C).
【００４９】次に、従たる導体層５３を整面後、厚み３
０μｍのドライフィルムを貼り合わせて感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行って、レジストパターン５４を形成した（図８（ｄ）
参照）。次に、レジストパターン５４をめっきマスクに
して電解銅めっきを行い、約２８μｍ厚の主たる導体層
５５、主たる導体パターン５５ａ及びビアホール５６を
形成した（図８（ｅ）参照）。Next, after the surface of the subordinate conductor layer 53 is adjusted, the thickness 3
A 0 μm dry film was attached to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development were performed to form a resist pattern 54 (FIG. 8D).
reference). Next, electrolytic copper plating was performed using the resist pattern 54 as a plating mask to form a main conductor layer 55, a main conductor pattern 55a, and a via hole 56 having a thickness of about 28 μm (see FIG. 8E).
【００５０】次に、厚み３０μｍのドライフィルムを貼
り合わせて感光層を形成し、パターン露光、現像等の一
連のパターニング処理を行って、めっき用導通リード及
び配線パターンを形成するためのレジストパターン５７
を形成した（図８（ｆ）参照）。次に、レジストパター
ン５７をエッチングマスクにして、塩化第２銅液にて表
面に露出した主たる導体層５５及び従たる導体層５３を
エッチングし、除去した（図８（ｇ）参照）。Next, a dry film having a thickness of 30 μm is bonded to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a conductive pattern for plating and a resist pattern 57 for forming a wiring pattern.
Was formed (see FIG. 8 (f)). Next, using the resist pattern 57 as an etching mask, the main conductor layer 55 and the subordinate conductor layer 53 exposed on the surface were etched and removed with a cupric chloride solution (see FIG. 8G).
【００５１】次に、水酸化ナトリウム溶液でレジストパ
ターン５７を剥離し、主たる導体パターン５５ａ及び従
たる導体パターン５３ａからなる配線パターン６１及び
めっき用導通リード５３ｂを形成した（図９（ｈ）参
照）。Next, the resist pattern 57 was peeled off with a sodium hydroxide solution to form a wiring pattern 61 consisting of a main conductor pattern 55a and a sub conductor pattern 53a and a conductive lead 53b for plating (see FIG. 9 (h)). .
【００５２】次に、金めっき液耐性のあるドライフィル
ム（ニチゴーモートン製）を貼り合せて感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行って、電解めっき用のレジストパターン５８を形成し
た（図９（ｉ）参照）。次に、基板の周囲から導通をと
って電解ニッケルめっき及び電解金めっきを順に行い、
主たる導体層２５の一部表面上に厚み約３μｍのニッケ
ル皮膜及び厚み約０．３μｍの金皮膜からなる導電性物
質被膜２９を形成した（図９（ｊ）参照）。Next, a dry film (manufactured by Nichigo Morton) resistant to a gold plating solution is bonded to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a resist pattern 58 for electrolytic plating. Were formed (see FIG. 9 (i)). Next, electrolytic nickel plating and electrolytic gold plating are performed in order by taking electrical continuity from around the substrate,
A conductive material film 29 consisting of a nickel film having a thickness of about 3 μm and a gold film having a thickness of about 0.3 μm was formed on a part of the surface of the main conductor layer 25 (see FIG. 9 (j)).
【００５３】次に、アルカリ溶液でレジストパターン５
８を剥離し（図９（ｋ）参照）、さらに、硫酸−加水系
エッチング液（ＣＰＢ−６０（商品名）、三菱ガス化学
製）の新液に３０秒から１分間浸漬して、めっき用導通
リード５３ｂを除去し、半導体装置用基板を得た（図９
（ｌ）参照）。最後に、ソルダーレジスト（ＰＳＲ−４
０００ ＡＵＳ５（商品名）、太陽インキ製）を印刷し
てソルダーレジスト感光層を形成し、パターン露光、現
像等の一連のパターニング処理を行って、ソルダーレジ
ストパターン６２を形成し、外形加工を行って、配線パ
ターンピッチ８０μｍで電解金めっき仕様の本発明の半
導体装置用基板を得た（図９（ｍ）参照）。Next, a resist pattern 5 is formed with an alkaline solution.
8 is peeled off (see FIG. 9 (k)), and further immersed in a new solution of a sulfuric acid-hydrogen-based etching solution (CPB-60 (trade name), manufactured by Mitsubishi Gas Chemical Co., Ltd.) for 30 seconds to 1 minute for plating. The conductive lead 53b was removed to obtain a semiconductor device substrate (FIG. 9).
(See (l)). Finally, solder resist (PSR-4
000 AUS5 (trade name), made by TAIYO INK) is printed to form a solder resist photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form a solder resist pattern 62, and external processing is performed. A semiconductor device substrate of the present invention having an electrolytic gold plating specification with a wiring pattern pitch of 80 μm was obtained (see FIG. 9 (m)).
【００５４】＜実施例４＞請求項５に係わる半導体装置
基板の製造方法の一実施例である。まず、絶縁基板１１
の両面に配線層１２を有するコア基板１０に樹脂フィル
ム付きの１８μｍの銅箔を積層して絶縁層７１及び導体
層７２を形成した（図１０（ａ）参照）。次に、導体層
７２上にドライフィルムを貼り合わせ、パターン露光、
現像等の一連のパターニング処理を行って、レジストパ
ターンを形成し、６０℃、４７°ボーメの塩化第２鉄溶
液で、導体層７２をエッチングし、５０℃、１％の水酸
化ナトリウム溶液をスプレーで吹き付けてレジストパタ
ーンを剥離し、開口部７３を形成した（図１０（ｂ）参
照）。<Embodiment 4> This is an embodiment of a method of manufacturing a semiconductor device substrate according to claim 5. First, the insulating substrate 11
An 18 μm copper foil with a resin film was laminated on the core substrate 10 having the wiring layers 12 on both surfaces to form an insulating layer 71 and a conductor layer 72 (see FIG. 10A). Next, a dry film is attached on the conductor layer 72, and pattern exposure is performed.
A series of patterning treatments such as development is performed to form a resist pattern, the conductor layer 72 is etched with ferric chloride solution at 60 ° C and 47 ° Baume, and sprayed with 50 ° C and 1% sodium hydroxide solution. And the resist pattern was peeled off to form the opening 73 (see FIG. 10B).
【００５５】次に、開口部７３よりレーザービームを照
射し、絶縁層７１にビア用孔７４を形成した（図１０
（ｃ）参照）。次に、ビア用孔７４をパラジウム触媒に
て導電化処理して、無電解及び電解銅めっきにてビア用
孔７４側面に２〜３μｍの銅の薄膜を形成し、電解銅め
っきを行って、ビア用孔７４にビアホール７５を、導体
層７２上に１５μｍ厚の銅の被膜を形成して主たる導体
層７６を形成した（図１０（ｄ）参照）。Next, a laser beam is irradiated through the opening 73 to form a via hole 74 in the insulating layer 71 (FIG. 10).
(See (c)). Next, the via hole 74 is subjected to a conductive treatment with a palladium catalyst to form a copper thin film of 2 to 3 μm on the side surface of the via hole 74 by electroless and electrolytic copper plating, and electrolytic copper plating is performed. A via hole 75 was formed in the via hole 74, and a copper film having a thickness of 15 μm was formed on the conductor layer 72 to form a main conductor layer 76 (see FIG. 10D).
【００５６】次に、主たる導体層７６上にドライフィル
ムを貼り合わせて感光層を形成し、パターン露光、現像
等の一連のパターニング処理を行って、レジストパター
ンを形成し、６０℃、４７°ボーメの塩化第２鉄溶液
で、主たる導体層７６をエッチングし、５０℃、１％の
水酸化ナトリウム溶液をスプレーで吹き付けてレジスト
パターンを剥離し、主たる導体パターン７６ａを形成し
た（図１０（ｅ）参照）。次に、絶縁層７１及び主たる
導体パターン７６ａ上をパラジウム触媒にて導電化処理
して、無電解及び電解銅めっきを行い、２〜３μｍの従
たる導体層７７を形成した（図１０（ｆ）参照）。Next, a dry film is laminated on the main conductor layer 76 to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a resist pattern, and 60 ° C. and 47 ° Baume are formed. Of the ferric chloride solution, the main conductor layer 76 was etched, and the resist pattern was peeled off by spraying a 1% sodium hydroxide solution at 50 ° C. to form the main conductor pattern 76a (FIG. 10 (e)). reference). Next, the insulating layer 71 and the main conductor pattern 76a were made conductive by a palladium catalyst, and electroless and electrolytic copper plating was performed to form a sub-conductor layer 77 having a thickness of 2 to 3 μm (FIG. 10 (f)). reference).
【００５７】次に、従たる導体層７７上にドライフィル
ムを貼り合わせて感光層を形成し、パターン露光、現像
等の一連のパターニング処理を行い、従たる導体層７７
の所定位置にレジストパターン７８を形成した（図１０
（ｇ）参照）。次に、レジストパターン７８をマスクに
して従たる導体層７７をエッチングし（図１１（ｈ）参
照）、レジストパターン７８を専用の剥離液で剥離し、
電気的に絶縁された主たる導体パターンを電気的に接続
するめっき用導通リード７７ａを形成した（図１１
（ｉ）参照）。Next, a dry film is laminated on the subordinate conductor layer 77 to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed, and the subordinate conductor layer 77 is formed.
A resist pattern 78 is formed at a predetermined position of (see FIG.
(See (g)). Next, the subordinate conductor layer 77 is etched by using the resist pattern 78 as a mask (see FIG. 11 (h)), and the resist pattern 78 is peeled by a dedicated peeling liquid,
A conductive lead 77a for plating that electrically connects the main electrically conductive pattern is formed (FIG. 11).
(See (i)).
【００５８】次に、金めっき耐性のあるドライフィルム
（ニチゴーモートン製）を貼り合せて感光層を形成し、
パターン露光、現像等の一連のパターニング処理を行っ
て、電解めっき用のレジストパターン７９を形成した
（図１１（ｊ）参照）。次に、基板の周囲から導通をと
って電解ニッケルめっき及び電解金めっきを順に行い、
主たる導体層の一部表面上に厚み約５μｍのニッケル皮
膜及び厚み約１μｍの金皮膜からなる導電性物質被膜８
１を形成した（図１１（ｋ）参照）。Next, a dry film having resistance to gold plating (manufactured by Nichigo Morton) is attached to form a photosensitive layer,
A series of patterning treatments such as pattern exposure and development were performed to form a resist pattern 79 for electrolytic plating (see FIG. 11 (j)). Next, electrolytic nickel plating and electrolytic gold plating are performed in order by taking electrical continuity from around the substrate,
Conductive material film 8 consisting of a nickel film having a thickness of about 5 μm and a gold film having a thickness of about 1 μm on a part of the surface of the main conductor layer
1 was formed (see FIG. 11 (k)).
【００５９】次に、めっき用レジストパターン７９をア
ルカリ溶液で剥離し（図１１（ｌ）参照）、硫酸−加水
系エッチング液（ＣＰＢ−６０（商品名）、三菱化学
製）の新液に３０秒から１分間浸漬してめっき用導通リ
ード７７ａを除去し、主たる導体パターン７６ａ相互が
電気的に絶縁され、ビアホール７５にて配線層１２と電
気的に接続された半導体装置用基板を得た（図１１
（ｍ）参照）。最後に、ソルダーレジスト（ＰＳＲ−４
０００ ＡＵＳ５（商品名）、太陽インキ製）を印刷し
てソルダーレジスト感光層を形成し、パターン露光、現
像等の一連のパターニング処理を行って、ソルダーレジ
ストパターン８２を形成して、主たる導体パターン７６
ａがソルダーレジストにて保護、絶縁された半導体装置
用基板を得た（図１１（ｎ）参照）。Next, the plating resist pattern 79 is peeled off with an alkaline solution (see FIG. 11 (l)), and a new solution of a sulfuric acid-hydrolyzed etching solution (CPB-60 (trade name), manufactured by Mitsubishi Chemical) is used. The plating conductive lead 77a was removed by immersing for 1 minute from a second to obtain a semiconductor device substrate in which the main conductor patterns 76a were electrically insulated from each other and were electrically connected to the wiring layer 12 at the via holes 75 ( Figure 11
(See (m)). Finally, solder resist (PSR-4
000 AUS5 (trade name, manufactured by Taiyo Ink Co., Ltd.) is printed to form a solder resist photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a solder resist pattern 82 and a main conductor pattern 76.
A semiconductor device substrate in which a was protected and insulated by a solder resist was obtained (see FIG. 11 (n)).
【００６０】＜実施例５＞請求項６に係わる半導体装置
基板の製造方法の一実施例である。まず、絶縁基板１１
の両面に配線層１２を有するコア基板１０に樹脂フィル
ム付きの１８μｍの銅箔を積層して絶縁層７１及び導体
層７２を形成し、導体層７２上にドライフィルムを貼り
合わせ、パターン露光、現像等の一連のパターニング処
理を行ってレジストパターンを形成し、６０℃、４７°
ボーメの塩化第２鉄溶液で、導体層７２をエッチング
し、５０℃、１％の水酸化ナトリウム溶液をスプレーで
吹き付けてレジストパターンを剥離し、開口部７３を形
成した（図１２（ａ）〜（ｂ）参照）。<Embodiment 5> This is an embodiment of a method of manufacturing a semiconductor device substrate according to claim 6. First, the insulating substrate 11
18 μm copper foil with a resin film is laminated on the core substrate 10 having the wiring layers 12 on both sides to form an insulating layer 71 and a conductor layer 72, and a dry film is attached on the conductor layer 72, and pattern exposure and development are performed. A series of patterning treatments, such as
The conductor layer 72 was etched with Baume's ferric chloride solution, and a resist pattern was peeled off by spraying a 1% sodium hydroxide solution at 50 ° C. to form an opening 73 (FIG. 12A-). (See (b)).
【００６１】次に、開口部７３よりレーザービームを照
射し、絶縁層７１にビア用孔７４を形成し、ビア用孔７
４をパラジウム触媒にて導電化処理して、無電解及び電
解銅めっきにてビア用孔７４側面に２〜３μｍの銅の薄
膜を形成した。さらに、電解銅めっきを行って、ビア用
孔７４にビアホール７５を、導体層７２上に１５μｍ厚
の銅の被膜を形成して主たる導体層７６を形成した（図
１２（ｃ）〜（ｄ）参照）。Next, a laser beam is irradiated from the opening 73 to form a via hole 74 in the insulating layer 71, and the via hole 7 is formed.
4 was made conductive with a palladium catalyst, and a copper thin film of 2 to 3 μm was formed on the side surface of the via hole 74 by electroless and electrolytic copper plating. Further, electrolytic copper plating was performed to form a via hole 75 in the via hole 74 and a main conductor layer 76 by forming a 15 μm-thick copper coating on the conductor layer 72 (FIGS. 12C to 12D). reference).
【００６２】次に、主たる導体層７６上にドライフィル
ムを貼り合わせて感光層を形成し、パターン露光、現像
等の一連のパターニング処理を行って、レジストパター
ンを形成し、６０℃、４７°ボーメの塩化第２鉄溶液
で、主たる導体層７６をエッチングし、５０℃、１％の
水酸化ナトリウム溶液をスプレーで吹き付けてレジスト
パターンを剥離し、主たる導体パターン７６ａを形成し
た（図１２（ｅ）参照）。Next, a dry film is laminated on the main conductor layer 76 to form a photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a resist pattern, and 60 ° C. and 47 ° Baume are formed. Of the ferric chloride solution, the main conductor layer 76 was etched, and the resist pattern was peeled off by spraying a 1% sodium hydroxide solution at 50 ° C. to form the main conductor pattern 76a (FIG. 12 (e)). reference).
【００６３】次に、絶縁層７１及び主たる導体パターン
７６ａ上にドライフィルムを貼り合わせて感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行い、所定位置に開口領域９２を有するレジストパター
ン９１を形成した（図１２（ｆ）参照）。Next, a dry film is laminated on the insulating layer 71 and the main conductor pattern 76a to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed, and a resist having an opening region 92 at a predetermined position. A pattern 91 was formed (see FIG. 12 (f)).
【００６４】次に、開口領域９２をパラジウム触媒にて
導電化処理して、レジストパターン９１を専用の剥離液
で剥離し、無電解及び電解銅めっきを行い、導電化処理
された開口領域９２に２〜３μｍ厚の従たる導体層から
なるめっき用導通リード９３を形成した（図１２（ｇ）
参照）。Next, the opening area 92 is made conductive with a palladium catalyst, the resist pattern 91 is stripped with a dedicated stripping solution, electroless and electrolytic copper plating is performed, and the opening area 92 is made conductive. A conductive lead 93 for plating made of a subordinate conductor layer having a thickness of 2 to 3 μm was formed (FIG. 12 (g)).
reference).
【００６５】次に、金めっき耐性のあるドライフィルム
（ニチゴーモートン製）を貼り合せて感光層を形成し、
パターン露光、現像等の一連のパターニング処理を行っ
て、電解めっき用のレジストマスク９４を形成した（図
１３（ｈ）参照）。Next, a dry film having resistance to gold plating (manufactured by Nichigo Morton) is laminated to form a photosensitive layer,
A series of patterning processes such as pattern exposure and development were performed to form a resist mask 94 for electrolytic plating (see FIG. 13 (h)).
【００６６】次に、基板の周囲から導通をとって電解ニ
ッケルめっき及び電解金めっきを順に行い、主たる導体
層の一部表面上に厚み約５μｍのニッケル皮膜及び厚み
約１μｍの金皮膜からなる導電性物質被膜９５を形成し
た（図１３（ｉ）参照）。Next, electrolytic nickel plating and electrolytic gold plating are performed in this order with electrical continuity from the periphery of the substrate, and a conductive film consisting of a nickel film with a thickness of about 5 μm and a gold film with a thickness of about 1 μm is formed on a part of the surface of the main conductor layer. A substance coating 95 was formed (see FIG. 13 (i)).
【００６７】次に、めっき用レジストマスク９４をアル
カリ溶液で剥離し（図１３（ｊ）参照）、硫酸−加水系
エッチング液（ＣＰＢ−６０（商品名）、三菱化学製）
の新液に３０秒から１分間浸漬してめっき用導通リード
９３を除去し、導体パターンピッチ４０μｍの主たる導
体パターン７６ａ相互が電気的に絶縁され、ビアホール
７５にて配線層１２と電気的に接続された半導体装置用
基板を得た（図１３（ｋ）参照）。最後に、ソルダーレ
ジスト（ＰＳＲ−４０００ ＡＵＳ５（商品名）、太陽
インキ製）を印刷してソルダーレジスト感光層を形成
し、パターン露光、現像等の一連のパターニング処理を
行ってソルダーレジストパターン９６を形成して、主た
る導体パターン７６ａがソルダーレジストにて保護、絶
縁された半導体装置用基板を得た（図１３（ｌ）参
照）。Next, the resist mask 94 for plating is peeled off with an alkaline solution (see FIG. 13 (j)), and a sulfuric acid-hydrogen-based etching solution (CPB-60 (trade name), manufactured by Mitsubishi Chemical).
The conductive lead 93 for plating is removed by immersing in the new solution for 30 seconds to 1 minute, the main conductor patterns 76a having a conductor pattern pitch of 40 μm are electrically insulated from each other, and electrically connected to the wiring layer 12 by the via hole 75. The obtained semiconductor device substrate was obtained (see FIG. 13 (k)). Finally, a solder resist (PSR-4000 AUS5 (trade name), made by Taiyo Ink Co., Ltd.) is printed to form a solder resist photosensitive layer, and a series of patterning treatments such as pattern exposure and development are performed to form a solder resist pattern 96. Then, a semiconductor device substrate in which the main conductor pattern 76a was protected and insulated by a solder resist was obtained (see FIG. 13 (l)).
【００６８】[0068]
【発明の効果】本発明の半導体装置用基板の製造方法で
は、半導体装置用基板の製造工程の途中でめっき用導通
リードを従たる導体層で形成し、このめっき用導通リー
ドを用いて配線パターンの一部表面に金膜等の導電性物
質被膜を電解めっきにて形成した後このめっき用導通リ
ードを除去するため、従来の工程で必要としていためっ
き用導通リード追加のための設計変更とパターン形成用
マスクの変更と調整、めっき用導通リード除去用パター
ンの設計とマスク作製などがほとんど不要になり、製造
工程の短縮及びコスト削減を行うことができる。また、
５０μｍピッチ程度の微細配線パターン密集部に外部と
電気的に接続しない孤立パターンがある場合にも電解金
めっきを行うことができ、めっきリード除去によるパタ
ーンの形状不良や断線発生がなくなった。さらに、高密
度配線基板を得ることができ、位置合わせに煩わされる
こともなくなった。また、引き出しリードが端面に残ら
ないようにできるため、端面部に露出したリードによる
絶縁性低下やマイグレーション発生などがなくなり、絶
縁信頼性が向上した。According to the method for manufacturing a semiconductor device substrate of the present invention, the conductive lead for plating is formed by the subordinate conductor layer during the manufacturing process of the substrate for semiconductor device, and the conductive lead for plating is used to form a wiring pattern. A conductive material coating such as a gold film is formed on a part of the surface of the plate by electrolytic plating, and the conductive lead for plating is removed. The change and adjustment of the formation mask, the design of the conductive lead removal pattern for plating, the mask preparation, etc. are almost unnecessary, and the manufacturing process and cost can be reduced. Also,
Electrolytic gold plating can be performed even when there is an isolated pattern that is not electrically connected to the outside in a dense wiring pattern dense portion having a pitch of about 50 μm, and the pattern shape defect and disconnection due to removal of the plating lead are eliminated. Furthermore, a high-density wiring board can be obtained, and the alignment is no longer bothered. Further, since the lead-out lead can be prevented from remaining on the end face, the deterioration of the insulation property due to the lead exposed on the end face part and the occurrence of migration are eliminated, and the insulation reliability is improved.
【図１】（ａ）は、本発明の半導体装置用基板の一実施
例を示す模式平面図である。（ｂ）は、模式平面図をＡ
−Ａ’線で切断した本発明の半導体装置用基板の一実施
例を示す模式構成断面図である。FIG. 1A is a schematic plan view showing an embodiment of a semiconductor device substrate of the present invention. (B) is a schematic plan view of A
FIG. 3 is a schematic cross-sectional view showing an example of the semiconductor device substrate of the present invention, which is taken along the line AA.
【図２】（ａ−１）、（ｂ−１）は、請求項４に係わる
半導体装置用基板の製造方法の一実施例の一部を工程順
に示す模式平面図である。（ａ−２）、（ｂ−２）は、
請求項４に係わる半導体装置用基板の製造方法の一実施
例の一部を工程順に示す模式構成断面図である。2 (a-1) and 2 (b-1) are schematic plan views showing, in the order of steps, a part of one embodiment of the method for manufacturing a semiconductor device substrate according to claim 4; (A-2) and (b-2) are
FIG. 7 is a schematic cross-sectional view showing a part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図３】（ｄ−１）は、請求項４に係わる半導体装置用
基板の製造方法の一実施例の一部を示す模式平面図であ
る。（ｃ−２）〜（ｆ−２）は、請求項４に係わる半導
体装置用基板の製造方法の一実施例の一部を工程順に示
す模式構成断面図である。FIG. 3D-1 is a schematic plan view showing a part of an embodiment of a method for manufacturing a substrate for a semiconductor device according to claim 4; (C-2) to (f-2) are schematic cross-sectional views showing part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図４】（ｇ−１）は、請求項４に係わる半導体装置用
基板の製造方法の一実施例の一部を示す模式平面図であ
る。（ｇ−２）、（ｈ−２）は、請求項４に係わる半導
体装置用基板の製造方法の一実施例の一部を工程順に示
す模式構成断面図である。FIG. 4G is a schematic plan view showing a part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 4; (G-2) and (h-2) are schematic cross-sectional views showing a part of one embodiment of the method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図５】（ｉ−１）、（ｊ−１）は、請求項４に係わる
半導体装置用基板の製造方法の一実施例の一部を工程順
に示す模式平面図である。（ｉ−２）、（ｊ−２）は、
請求項４に係わる半導体装置用基板の製造方法の一実施
例の一部を工程順に示す模式構成断面図である。5 (i-1) and (j-1) are schematic plan views showing a part of one embodiment of the method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps. (I-2) and (j-2) are
FIG. 7 is a schematic cross-sectional view showing a part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図６】（ｌ−１）は、請求項４に係わる半導体装置用
基板の製造方法の一実施例の一部を示す模式平面図であ
る。（ｋ−２）、（ｌ−２）は、請求項４に係わる半導
体装置用基板の製造方法の一実施例の一部を工程順に示
す模式構成断面図である。FIG. 6A is a schematic plan view showing a part of an embodiment of a method for manufacturing a semiconductor device substrate according to the present invention; (K-2) and (1-2) are schematic cross-sectional views showing a part of an embodiment of the method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図７】（ｍ−１）、（ｎ−１）は、請求項４に係わる
半導体装置用基板の製造方法の一実施例の一部を工程順
に示す模式平面図である。（ｍ−２）、（ｎ−２）は、
請求項４に係わる半導体装置用基板の製造方法の一実施
例の一部を工程順に示す模式構成断面図である。7 (m-1) and (n-1) are schematic plan views showing, in the order of steps, part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 4; (M-2) and (n-2) are
FIG. 7 is a schematic cross-sectional view showing a part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図８】（ａ）〜（ｇ）は、請求項４に係わる半導体装
置用基板の製造方法の他の実施例の一部を工程順に示す
模式構成断面図である。8A to 8G are schematic cross-sectional views showing a part of another embodiment of the method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図９】（ｈ）〜（ｍ）は、請求項４に係わる半導体装
置用基板の製造方法の他の実施例の一部を工程順に示す
模式構成断面図である。9 (h) to 9 (m) are schematic cross-sectional views showing a part of another embodiment of the method for manufacturing a semiconductor device substrate according to claim 4 in the order of steps.
【図１０】（ａ）〜（ｇ）は、請求項５に係わる半導体
装置用基板の製造方法の一実施例の一部を工程順に示す
模式構成断面図である。10A to 10G are schematic cross-sectional views showing part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 5 in the order of steps.
【図１１】（ｈ）〜（ｎ）は、請求項５に係わる半導体
装置用基板の製造方法の一実施例の一部を工程順に示す
模式構成断面図である。11 (h) to (n) are schematic cross-sectional views showing a part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 5 in the order of steps.
【図１２】（ａ）〜（ｇ）は、請求項６に係わる半導体
装置用基板の製造方法の一実施例の一部を工程順に示す
模式構成断面図である。12A to 12G are schematic cross-sectional views showing part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 6 in the order of steps.
【図１３】（ｈ）〜（ｌ）は、請求項６に係わる半導体
装置用基板の製造方法の一実施例の一部を工程順に示す
模式構成断面図である。13 (h) to 13 (l) are schematic cross-sectional views showing part of an embodiment of a method for manufacturing a semiconductor device substrate according to claim 6 in the order of steps.
１０……コア基板 １１……絶縁基板 １２……配線層 ２１、５１、７１……絶縁層 ２２、５２、７４……ビア用孔 ２３、５３、７７……従たる導体層 ２３ａ、５３ａ……従たる導体パターン ２３ｂ、７７ａ、９３……めっき用導通リード ２４、５４、９１……レジストパターン ２５、５５、７６……主たる導体層 ２５ａ、５５ａ、７６ａ……主たる導体パターン ２６、５６、７５……ビアホール ２７、５７、７８……レジストパターン ２８、５８、７９……めっき用レジストパターン ２９、５９、８１、９５……導電性物質被膜 ３１、６１……配線パターン ３２、６２、８２……ソルダーレジストパターン ７２……導体層 ７３……開口部 ９２……開口領域 ９４……めっき用レジストマスク 10 ... Core substrate 11 ... Insulating substrate 12 ... Wiring layer 21, 51, 71 ... Insulating layer 22, 52, 74 ... Via holes 23, 53, 77 ... Subordinate conductor layers 23a, 53a ... Subordinate conductor pattern 23b, 77a, 93 ... Conductive lead for plating 24, 54, 91 ... Resist pattern 25, 55, 76 ... Main conductor layer 25a, 55a, 76a ... Main conductor pattern 26, 56, 75 ... Beer holes 27, 57, 78 ... Resist pattern 28, 58, 79 ... Resist pattern for plating 29, 59, 81, 95 ... Conductive substance coating 31, 61 ... Wiring pattern 32, 62, 82 ... Solder resist pattern 72 ... Conductor layer 73 ... Opening 92: Opening area 94: Resist mask for plating
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/46 Ｈ０５Ｋ 3/46 Ｎ Ｈ０１Ｌ 23/12 Ｎ (72)発明者 杉立 一彦 東京都台東区台東１丁目５番１号 凸版印 刷株式会社内 (72)発明者 太田 秋津 東京都台東区台東１丁目５番１号 凸版印 刷株式会社内 (72)発明者 徳島 弘明 東京都台東区台東１丁目５番１号 凸版印 刷株式会社内 Ｆターム(参考） 5E314 AA27 BB06 BB11 CC06 DD07 FF05 FF17 5E339 AB02 AC01 AD03 AD05 AE01 BC02 BD03 BD06 BD11 BE13 CC01 CD01 CE16 CF06 CF16 CF17 CG04 5E343 AA02 AA12 BB24 DD33 DD43 ER16 ER18 ER23 ER26 GG08 GG11 5E346 AA06 AA15 AA43 CC08 CC32 CC54 CC55 DD02 DD25 DD32 DD33 DD44 EE33 FF07 FF15 GG15 GG17 GG18 GG22 GG28 HH25 HH32 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 3/46 H05K 3/46 N H01L 23/12 N (72) Inventor Kazuhiko Sugachi 1 Taito, Taito-ku, Tokyo Inc. 5-11 Toppan Printing Co., Ltd. (72) Inventor Ota Akitsu 1-5-1 Taito Taito-ku, Tokyo Metropolitan Imprint Inc. (72) Inventor Hiroaki Tokushima 1-5 Taito-ku, Taito-ku, Tokyo No. 1 Toppan Printing Co., Ltd. F term (reference) 5E314 AA27 BB06 BB11 CC06 DD07 FF05 FF17 5E339 AB02 AC01 AD03 AD05 AE01 BC02 BD03 BD06 BD11 BE13 CC01 CD01 CE16 CF06 CF16 CF17 CG04 5E343 AA02 AA12 BB24 DD16 DD18 ER16 ER16 ER16 GG08 GG11 5E346 AA06 AA15 AA43 CC08 CC32 CC54 CC55 DD02 DD25 DD32 DD33 DD44 EE33 FF07 FF15 GG15 GG17 GG18 GG22 GG28 HH25 HH32
Claims (6)
層が直接積み重ねられて一つの導体層が形成されてお
り、前記一つの導体層をパターニング処理して形成され
た配線パターンの主たる導体層の少なくとも一部表面が
主たる導体層とは異なる導電性物質で覆われている半導
体装置用基板であって、前記配線パターンの少なくとも
一つ以上が電気的に絶縁されていることを特徴とする半
導体装置用基板。1. A main conductor having a wiring pattern formed by directly stacking main conductor layers having different thicknesses on a sub conductor layer to form one conductor layer, and forming a conductor pattern by patterning the one conductor layer. A substrate for a semiconductor device in which at least a part of the surface of the layer is covered with a conductive material different from the main conductor layer, wherein at least one or more of the wiring patterns is electrically insulated Substrate for semiconductor device.
性物質で、前記従たる導体層は銅もしくは銅以外の導電
性物質で、前記主たる導体層とは異なる導電性物質はニ
ッケル、パラジウム、金、白金、ロジウム、銀及び錫の
うち少なくとも１種類からなる導電性物質で形成されて
いることを特徴とする請求項１に記載の半導体装置用基
板。2. The main conductor layer is a conductive substance containing copper as a main component, the sub conductor layer is copper or a conductive substance other than copper, and the conductive substance different from the main conductor layer is nickel. The substrate for a semiconductor device according to claim 1, wherein the substrate for a semiconductor device is formed of a conductive substance made of at least one of palladium, gold, platinum, rhodium, silver and tin.
し、前記従たる導体層は主たる導体層以下の厚みからな
り、前記配線パターンの少なくとも一部が１００μｍピ
ッチ以下の微細かつ高密度な配線パターンであることを
特徴とする請求項１または２に記載の半導体装置用基
板。3. The main conductor layer has a thickness of 3 μm or more, the sub conductor layer has a thickness of the main conductor layer or less, and at least a part of the wiring pattern has a fine and high density of 100 μm pitch or less. It is a wiring pattern, The board | substrate for semiconductor devices of Claim 1 or 2 characterized by the above-mentioned.
特徴とする請求項１乃至３のいずれか一項に記載の半導
体装置用基板の製造方法。 （ａ）絶縁基板の両面に従たる導体層を形成する工程。 （ｂ）前記従たる導体層上にレジストパターンを形成
し、前記レジストパターンをマスクにして主たる導体
層、主たる導体パターン及びビアホールを形成し、前記
レジストパターンを剥離する工程。 （ｃ）前記従たる導体層及び主たる導体パターン上の所
定位置にレジストパターンを形成する工程。 （ｄ）前記レジストパターンをエッチングマスクにして
従たる導体層をエッチングし、前記レジストパターンを
剥離し、電気的に絶縁された主たる導体パターンを電気
的に接続するめっき用導通リードを従たる導体層で形成
する工程。 （ｅ）前記主たる導体層構成物質とは異なる導電性物質
を主たる導体パターンの少なくとも一部表面に形成する
ためのレジストマスクを形成する工程。 （ｆ）前記レジストマスクをめっきマスクにして電解め
っきを行い、めっき用導通リードで接続された主たる導
体層の一部表面に主たる導体層構成物質とは異なる導電
性物質被膜を形成する工程。 （ｇ）前記レジストマスクを専用の剥離液で除去し、め
っき用導通リードをエッチングで除去する工程。 （ｈ）基板上にソルダーレジストパターンを形成する工
程。4. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising at least the following steps. (A) A step of forming conductor layers on both sides of the insulating substrate. (B) A step of forming a resist pattern on the subordinate conductor layer, forming a main conductor layer, a main conductor pattern and a via hole using the resist pattern as a mask, and peeling off the resist pattern. (C) A step of forming a resist pattern at predetermined positions on the subordinate conductor layer and the main conductor pattern. (D) A conductive layer that is a subordinate conductive layer for plating that etches the subordinate conductor layer using the resist pattern as an etching mask to peel off the resist pattern and electrically connect the electrically insulated main conductive pattern. Forming process. (E) A step of forming a resist mask for forming a conductive substance different from the main conductor layer constituent substance on at least a part of the surface of the main conductor pattern. (F) A step of performing electrolytic plating by using the resist mask as a plating mask to form a conductive substance film different from the main conductor layer constituent substance on a part of the surface of the main conductor layer connected by the conductive lead for plating. (G) A step of removing the resist mask with a dedicated stripping solution and etching the conductive leads for plating. (H) A step of forming a solder resist pattern on the substrate.
特徴とする請求項１乃至３のいずれか一項に記載の半導
体装置用基板の製造方法。 （ａ）絶縁基板の両面に主たる導体層を形成する工程。 （ｂ）前記主たる導体層をパターニング処理し、主たる
導体パターンを形成する工程。 （ｃ）前記絶縁基板及び前記主たる導体パターン上に従
たる導体層を形成する工程。 （ｄ）前記従たる導体層上の所定位置にレジストパター
ンを形成する工程。 （ｅ）前記レジストパターンをエッチングマスクにして
従たる導体層をエッチングし、めっき用導通リードを形
成する工程。 （ｆ）前記レジストパターンを専用の剥離液で剥離し、
前記主たる導体層構成物質とは異なる導電性物質を主た
る導体パターンの少なくとも一部表面に形成するための
レジストマスクを形成する工程。 （ｇ）前記レジストマスクをめっきマスクにして電解め
っきを行い、めっき用導通リードで接続された主たる導
体層の一部表面に主たる導体層構成物質とは異なる導電
性物質被膜を形成する工程。 （ｈ）前記レジストマスクを専用の剥離液で除去し、前
記めっき用導通リードをエッチングで除去する工程。 （ｉ）基板上にソルダーレジストパターンを形成する工
程。5. The method for manufacturing a substrate for a semiconductor device according to claim 1, further comprising at least the following steps. (A) A step of forming main conductor layers on both surfaces of the insulating substrate. (B) A step of patterning the main conductor layer to form a main conductor pattern. (C) A step of forming a conductive layer on the insulating substrate and the main conductive pattern. (D) A step of forming a resist pattern at a predetermined position on the subordinate conductor layer. (E) A step of forming a conductive lead for plating by etching a subordinate conductor layer using the resist pattern as an etching mask. (F) The resist pattern is stripped with a dedicated stripping solution,
A step of forming a resist mask for forming a conductive substance different from the main conductor layer constituent substance on at least a part of the surface of the main conductor pattern. (G) A step of performing electrolytic plating by using the resist mask as a plating mask to form a conductive material film different from the main conductor layer constituent material on a part of the surface of the main conductor layer connected by the conductive lead for plating. (H) A step of removing the resist mask with a dedicated stripping solution and removing the plating conductive leads by etching. (I) A step of forming a solder resist pattern on the substrate.
特徴とする請求項１乃至３のいずれか一項に記載の半導
体装置用基板の製造方法。 （ａ）絶縁基板の両面に主たる導体層を形成する工程。 （ｂ）前記主たる導体層をパターニング処理し、主たる
導体パターンを形成する工程。 （ｃ）前記絶縁基板及び前記主たる導体パターン上の所
定位置に開口領域を有するレジストパターンを形成する
工程。 （ｄ）前記開口領域を導電化処理する工程。 （ｅ）前記レジストマスクを専用の剥離液で剥離し、無
電解、電解銅めっきを行い、導電化処理された前記開口
領域に従たる導体層からなるめっき用導通リードを形成
する工程。 （ｆ）前記主たる導体層構成物質とは異なる導電性物質
を主たる導体パターンの少なくとも一部表面に形成する
ためのレジストマスクを形成する工程。 （ｇ）前記レジストマスクをめっきマスクにして電解め
っきを行い、めっき用導通リードで接続された主たる導
体層の一部表面に主たる導体層構成物質とは異なる導電
性物質被膜を形成する工程。 （ｈ）前記レジストマスクを専用の剥離液で除去し、前
記めっき用導通リードをエッチングで除去する工程。 （ｉ）基板上にソルダーレジストパターンを形成する工
程。6. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising at least the following steps. (A) A step of forming main conductor layers on both surfaces of the insulating substrate. (B) A step of patterning the main conductor layer to form a main conductor pattern. (C) A step of forming a resist pattern having an opening region at a predetermined position on the insulating substrate and the main conductor pattern. (D) A step of electrically conducting the opening region. (E) A step of stripping the resist mask with a dedicated stripping solution, performing electroless and electrolytic copper plating, and forming a conductive lead for plating made of a conductor layer according to the opening region subjected to the conductivity treatment. (F) A step of forming a resist mask for forming a conductive substance different from the main conductor layer constituent substance on at least a part of the surface of the main conductor pattern. (G) A step of performing electrolytic plating by using the resist mask as a plating mask to form a conductive material film different from the main conductor layer constituent material on a part of the surface of the main conductor layer connected by the conductive lead for plating. (H) A step of removing the resist mask with a dedicated stripping solution and removing the plating conductive leads by etching. (I) A step of forming a solder resist pattern on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001293183A JP2003101195A (en) | 2001-09-26 | 2001-09-26 | Substrate for semiconductor device and production method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001293183A JP2003101195A (en) | 2001-09-26 | 2001-09-26 | Substrate for semiconductor device and production method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003101195A true JP2003101195A (en) | 2003-04-04 |
Family
ID=19115027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001293183A Pending JP2003101195A (en) | 2001-09-26 | 2001-09-26 | Substrate for semiconductor device and production method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003101195A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7443131B2 (en) | 2004-01-13 | 2008-10-28 | Nsk Ltd. | Control device for electric power steering apparatus |
| JP2009272549A (en) * | 2008-05-09 | 2009-11-19 | Nitto Denko Corp | Method of manufacturing wiring circuit board |
| KR101194461B1 (en) | 2011-09-22 | 2012-10-24 | 삼성전기주식회사 | Printed circuit board and method for manufacturing the same |
| JP2017191845A (en) * | 2016-04-13 | 2017-10-19 | 株式会社ジェイデバイス | Semiconductor device and manufacturing method of semiconductor device |
| WO2023054963A1 (en) * | 2021-09-29 | 2023-04-06 | 스템코 주식회사 | Multilayer substrate, method for manufacturing same, and electronic device including multilayer substrate |
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|---|---|---|---|---|
| JPS63240093A (en) * | 1987-03-27 | 1988-10-05 | 松下電器産業株式会社 | Manufacture of printed wiring board |
| JPH11307687A (en) * | 1998-04-16 | 1999-11-05 | Ibiden Co Ltd | Package board |
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2001
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240093A (en) * | 1987-03-27 | 1988-10-05 | 松下電器産業株式会社 | Manufacture of printed wiring board |
| JPH11307687A (en) * | 1998-04-16 | 1999-11-05 | Ibiden Co Ltd | Package board |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7443131B2 (en) | 2004-01-13 | 2008-10-28 | Nsk Ltd. | Control device for electric power steering apparatus |
| JP2009272549A (en) * | 2008-05-09 | 2009-11-19 | Nitto Denko Corp | Method of manufacturing wiring circuit board |
| JP4523051B2 (en) * | 2008-05-09 | 2010-08-11 | 日東電工株式会社 | Method for manufacturing printed circuit board |
| US8460563B2 (en) | 2008-05-09 | 2013-06-11 | Nitto Denko Corporation | Producing method of wired circuit board |
| KR101194461B1 (en) | 2011-09-22 | 2012-10-24 | 삼성전기주식회사 | Printed circuit board and method for manufacturing the same |
| JP2017191845A (en) * | 2016-04-13 | 2017-10-19 | 株式会社ジェイデバイス | Semiconductor device and manufacturing method of semiconductor device |
| WO2023054963A1 (en) * | 2021-09-29 | 2023-04-06 | 스템코 주식회사 | Multilayer substrate, method for manufacturing same, and electronic device including multilayer substrate |
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