JP2003059926A - Semiconductor device - Google Patents
Semiconductor deviceInfo
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- JP2003059926A JP2003059926A JP2002163983A JP2002163983A JP2003059926A JP 2003059926 A JP2003059926 A JP 2003059926A JP 2002163983 A JP2002163983 A JP 2002163983A JP 2002163983 A JP2002163983 A JP 2002163983A JP 2003059926 A JP2003059926 A JP 2003059926A
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- insulating film
- gate insulating
- dielectric constant
- interface layer
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高誘電体からなる
ゲート絶縁膜を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a gate insulating film made of a high dielectric material.
【０００２】[0002]
【従来の技術】近年の半導体装置における高集積化及び
高速化に対する技術進展に伴い、ＭＯＳＦＥＴの微細化
が進められている。微細化に伴いゲート絶縁膜の薄膜化
を進めると、トンネル電流によるゲートリーク電流の増
大等の問題が顕在化してくる。この問題を抑制するため
に、ＨｆＯ2 、ＺｒＯ2 、Ｌａ2Ｏ3、ＴｉＯ2 又はＴａ
2Ｏ5等の高誘電率材料を用いたゲート絶縁膜（以下、hi
gh-kゲート絶縁膜と称する）により、小さいＳｉＯ2 換
算膜厚（以下、ＥＯＴ（Equivalent Oxide Thickness）
と称する）を実現しながら物理的膜厚を厚くするという
手法が研究されている。2. Description of the Related Art In recent years, high integration of semiconductor devices and
MOSFET miniaturization along with technological progress for higher speed
Is being promoted. Thinning of gate insulating film due to miniaturization
The gate leakage current due to the tunnel current.
Greater problems will become apparent. To suppress this problem
To HfO2, ZrO2, La2O3, TiO2Or Ta
2OFiveGate insulating film using a high dielectric constant material such as
gh-k gate insulating film), so small SiO2Exchange
Calculated thickness (hereinafter referred to as EOT (Equivalent Oxide Thickness)
Called)) while increasing the physical film thickness
Methods are being studied.
【０００３】また、昨今のシステムＬＳＩにおいては、
演算処理を行なう内部回路、入出力を受け持つ周辺回
路、及びＤＲＡＭ等の複数の機能を持つ回路を１つのチ
ップに集積することが一般的になっている。このような
システムＬＳＩを構成するＭＯＳＦＥＴに対しては、高
駆動力と低リーク電流とが求められる。Further, in the recent system LSI,
It has become common to integrate an internal circuit that performs arithmetic processing, a peripheral circuit that handles input / output, and a circuit having a plurality of functions such as a DRAM into one chip. High driving force and low leakage current are required for MOSFETs that constitute such a system LSI.
【０００４】従来のhigh-kゲート絶縁膜の形成方法とし
て、特開2000-058832号公報（United States Patent 6,
013,553 ）に記載された方法が知られている。As a conventional method for forming a high-k gate insulating film, Japanese Patent Laid-Open No. 2000-058832 (United States Patent 6,
013,553) is known.
【０００５】図５は、前記公報に開示された従来の半導
体装置、具体的には、オキシ窒化ジルコニウム又はオキ
シ窒化ハフニウムよりなるhigh-kゲート絶縁膜を有する
ＭＯＳＦＥＴの断面構成を示している。FIG. 5 shows a cross-sectional structure of the conventional semiconductor device disclosed in the above publication, specifically, a MOSFET having a high-k gate insulating film made of zirconium oxynitride or hafnium oxynitride.
【０００６】図５に示すように、Ｓｉ基板１の上にエピ
タキシャルＳｉ層２が形成されている。エピタキシャル
Ｓｉ層２の上部には不純物がドーピングされており、該
上部は電圧印加時にチャネル領域３となる。チャネル領
域３の上にはhigh-kゲート絶縁膜４を介して導電性のゲ
ート電極５が形成されている。As shown in FIG. 5, an epitaxial Si layer 2 is formed on a Si substrate 1. The upper portion of the epitaxial Si layer 2 is doped with impurities, and the upper portion becomes the channel region 3 when a voltage is applied. A conductive gate electrode 5 is formed on the channel region 3 via a high-k gate insulating film 4.
【０００７】high-kゲート絶縁膜４の形成方法は次の通
りである。すなわち、Ｓｉ基板１の上に、チャネル領域
３となる部分を含むエピタキシャルＳｉ層２を形成した
後、圧力１．３３×１０-1Ｐａ程度の酸素雰囲気内で、
Ｓｉ基板１に対して６００〜７００℃程度の加熱処理を
３０秒間程度行なうことによって、厚さ１ｎｍ未満の酸
化物層を形成する。その後、この酸化物層に対して、そ
のまま残存させるか、希釈ＨＦにより取り除いてＳｉ表
面を水素終端させるか、又は、クラスターツールを用い
た超高真空状態（１．３３×１０-6Ｐａ程度）での７８
０℃程度の加熱処理により昇華して原子的に平滑なＳｉ
表面を形成するかのいずれかの処理が行なわれる。酸化
物層つまりシリコン酸化膜を残存させる代わりに、オキ
シ窒化シリコン膜の超薄膜よりなる保護障壁層を形成し
てもよい。The method of forming the high-k gate insulating film 4 is as follows. That is, after forming the epitaxial Si layer 2 including the portion to be the channel region 3 on the Si substrate 1, in an oxygen atmosphere with a pressure of about 1.33 × 10 −1 Pa,
A heat treatment at about 600 to 700 ° C. is performed on the Si substrate 1 for about 30 seconds to form an oxide layer having a thickness of less than 1 nm. Then, the oxide layer is left as it is, or it is removed by diluted HF to terminate the Si surface with hydrogen, or an ultrahigh vacuum state using a cluster tool (about 1.33 × 10 −6 Pa) At 78
Si that is sublimated by heat treatment at about 0 ° C and is atomically smooth
Either treatment for forming the surface is performed. Instead of leaving the oxide layer, that is, the silicon oxide film, a protective barrier layer made of an ultra-thin silicon oxynitride film may be formed.
【０００８】以上のようにクリーンなＳｉ表面、酸化物
層又は保護障壁層のいずれかを持つＳｉ基板１を準備し
た後、Ｓｉ基板１の上に、スパッタ法、蒸着法、化学的
気相成長（ＣＶＤ）法又はプラズマＣＶＤ法等により、
ジルコニウム又はハフニウムよりなる金属層を堆積す
る。その後、該金属層に対して、ＮＯ若しくはＮ2 Ｏ等
の酸素及び窒素を含むガスを用いた酸窒化処理、Ｎ2 及
びＯ2 を用いた低温下での遠隔プラズマ処理（基板処理
チャンバーとプラズマ生成チャンバーとが異なってい
る）、又は、ＮＨ3 を用いた遠隔プラズマ窒化処理及び
それに引き続く酸化処理を行なうこと等により、オキシ
窒化ジルコニウム又はオキシ窒化ハフニウムよりなるhi
gh-kゲート絶縁膜４を形成する。After preparing a Si substrate 1 having a clean Si surface, an oxide layer, or a protective barrier layer as described above, the Si substrate 1 is sputtered, vapor-deposited, or chemically vapor-deposited. (CVD) method or plasma CVD method,
Deposit a metal layer of zirconium or hafnium. Then, the metal layer is subjected to an oxynitriding treatment using a gas containing oxygen and nitrogen such as NO or N 2 O, a remote plasma treatment using N 2 and O 2 at a low temperature (a substrate treatment chamber and a plasma treatment). The production chamber is different), or by performing remote plasma nitriding treatment using NH 3 and subsequent oxidation treatment, etc., a zirconium oxynitride or hafnium oxynitride
A gh-k gate insulating film 4 is formed.
【０００９】その後、Ａｒ等の不活性ガス雰囲気中又は
還元性ガス雰囲気中で、high-kゲート絶縁膜４に対して
７５０℃程度のアニールを２０秒間行なうことにより、
high-kゲート絶縁膜４を緻密化する。このように形成さ
れたhigh-kゲート絶縁膜４は非晶質又は多結晶であり、
ＳｉＯ2 の比誘電率と比べて著しく高い比誘電率を有す
る。Thereafter, the high-k gate insulating film 4 is annealed at about 750 ° C. for 20 seconds in an atmosphere of an inert gas such as Ar or a reducing gas atmosphere.
The high-k gate insulating film 4 is densified. The high-k gate insulating film 4 thus formed is amorphous or polycrystalline,
It has a significantly higher dielectric constant than that of SiO 2 .
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、前述の
従来のＭＯＳＦＥＴにおいては、high-kゲート絶縁膜の
信頼性寿命が短くなるという問題がある。However, the above-mentioned conventional MOSFET has a problem that the reliability life of the high-k gate insulating film is shortened.
【００１１】前記に鑑み、本発明は、長い信頼性寿命を
持つhigh-kゲート絶縁膜を実現することを目的とする。In view of the above, it is an object of the present invention to realize a high-k gate insulating film having a long reliability life.
【００１２】[0012]
【課題を解決するための手段】前記の目的を達成するた
め、本願発明者は、従来のhigh-kゲート絶縁膜の信頼性
寿命が短くなる原因を検討した結果、次のような知見を
得た。すなわち、前述の従来の方法を用いてシリコン基
板上にhigh-kゲート絶縁膜を形成した場合、シリコン基
板界面に、ＳｉＯ2 の組成に近いシリケート（high-k材
料（ジルコニウム酸化物等の金属酸化物）とシリコンと
の３元系化合物）が形成される。一般的に、シリケート
は、シリコンを含まない元のhigh-k材料よりも比誘電率
が低い。また、high-kゲート絶縁膜堆積後のアニール
（ゲート絶縁膜を緻密化するためのＰＤＡ（Post Depos
ition Anneal））によって、ゲート絶縁膜を構成するhi
gh-k材料の結晶化が進む結果、該high-k材料から結晶粒
界を介して酸素がシリコン基板まで拡散し、それにより
シリコン基板界面にＳｉＯ2 が形成されてしまう。すな
わち、high-kゲート絶縁膜は、比誘電率の低いＳｉＯ2
又はＳｉＯ2 の組成に近いシリケートよりなる界面層
と、比誘電率の高いhigh-k材料又はhigh-k材料の組成に
近いシリケートよりなるhigh-k層との積層構造を持つ。
ところが、このような積層構造においては、ゲート電極
を介して電圧が印加されると低誘電率の界面層に電界集
中が起こり、その結果、絶縁破壊が生じやすくなって、
high-kゲート絶縁膜の重要な特性である信頼性が劣化し
てしまうと考えられる。In order to achieve the above-mentioned object, the inventors of the present application have investigated the cause of shortening the reliability life of a conventional high-k gate insulating film, and obtained the following findings. It was That is, when a high-k gate insulating film is formed on a silicon substrate by using the above-mentioned conventional method, a silicate (high-k material (metal oxide such as zirconium oxide) having a composition close to that of SiO 2 is formed at the interface of the silicon substrate. A ternary compound of a substance) and silicon is formed. In general, silicates have a lower dielectric constant than the original silicon-free high-k materials. Also, annealing after deposition of the high-k gate insulating film (PDA (Post Deposa for densifying the gate insulating film
ition Anneal)) to form the gate insulating film.
As a result of the progress of crystallization of the gh-k material, oxygen diffuses from the high-k material to the silicon substrate through the grain boundaries, and thereby SiO 2 is formed at the silicon substrate interface. That is, the high-k gate insulating film is made of SiO 2 having a low relative dielectric constant.
Alternatively, it has a laminated structure of an interface layer made of a silicate having a composition close to that of SiO 2 and a high-k layer made of a high-k material having a high relative dielectric constant or a silicate having a composition close to that of a high-k material.
However, in such a laminated structure, when a voltage is applied through the gate electrode, electric field concentration occurs in the interface layer having a low dielectric constant, and as a result, dielectric breakdown easily occurs,
It is considered that reliability, which is an important characteristic of the high-k gate insulating film, is deteriorated.
【００１３】そこで、本願発明者は、high-kゲート絶縁
膜の信頼性寿命の長さと、界面層厚さのhigh-kゲート絶
縁膜全体の厚さに対する比Ｔ１／（Ｔ１＋Ｔ２）（但し
Ｔ１は界面層の物理的厚さ、Ｔ２はhigh-k層の物理的厚
さ）との相関をシミュレーションを用いて調べてみた。
その結果を図１に示す。シミュレーションは、trap gen
eration model（J.H.Stathis, Technical Digest of In
ternational ElectronDevice and Material (1998), p1
67.）をhigh-kゲート絶縁膜に応用することによって行
なった。具体的には、high-kゲート絶縁膜について、リ
ーク電流Ｊg 、ストレス印加直後のリーク電流Ｊ0 、注
入電荷当たりの欠陥生成率Ｐg （＝絶縁破壊時の電流増
加比ΔＪg／Ｊ0）、及び絶縁破壊に至るときの臨界欠陥
密度Ｎbdのそれぞれの値を求め、これらの値に基づい
て、high-kゲート絶縁膜における絶縁破壊寿命Ｔbd（＝
Ｎbd／Ｐg ）を求めた。また、シュミュレーションにお
いては、high-kゲート絶縁膜のＥＯＴが常に１．５ｎｍ
を保つように各物理的厚さＴ１及びＴ２を調整しながら
比Ｔ１／（Ｔ１＋Ｔ２）を変化させていった場合におけ
る、印加電圧１Ｖのストレス下（温度は室温）でのhigh
-kゲート絶縁膜の信頼性寿命を算出した。但し、シュミ
ュレーションにおいては、界面層の比誘電率ε１を３．
９の一定値に固定したのに対して、high-k層の比誘電率
ε２を８．０、１２．０、１８．０及び２４．０の複数
の値に変化させた。ここで、ＥＯＴ＝Ｔ１＋（ε１／ε
２）×Ｔ２の関係が成り立つ。Therefore, the inventor of the present application has found that the ratio of the reliability life of the high-k gate insulating film to the total thickness of the high-k gate insulating film is T1 / (T1 + T2) (where T1 is The physical thickness of the interface layer, T2, was correlated with the physical thickness of the high-k layer.
The result is shown in FIG. Simulation is trap gen
eration model (JHStathis, Technical Digest of In
ternational ElectronDevice and Material (1998), p1
67.) was applied to a high-k gate insulating film. Specifically, for the high-k gate insulating film, the leakage current J g , the leakage current J 0 immediately after stress application, the defect generation rate P g per injected charge (= current increase ratio ΔJ g / J 0 at dielectric breakdown). ), And the critical defect density N bd at the time of reaching the dielectric breakdown, and based on these values, the dielectric breakdown life T bd (=
N bd / P g ) was determined. Also, in simulation, the EOT of the high-k gate insulating film is always 1.5 nm.
In the case where the ratio T1 / (T1 + T2) is changed while adjusting the physical thicknesses T1 and T2 so that
-k Calculated the reliability life of the gate insulating film. However, in the simulation, the relative dielectric constant ε1 of the interface layer was set to 3.
While fixed at a constant value of 9, the relative permittivity ε2 of the high-k layer was changed to a plurality of values of 8.0, 12.0, 18.0 and 24.0. Here, EOT = T1 + (ε1 / ε
2) The relationship of T2 is established.
【００１４】図１に示すように、比Ｔ１／（Ｔ１＋Ｔ
２）、つまりhigh-kゲート絶縁膜全体の厚さに対する界
面層厚さの比が０．２以下である場合、high-kゲート絶
縁膜の信頼性を高く維持できる。また、比Ｔ１／（Ｔ１
＋Ｔ２）が増加するに従い、high-kゲート絶縁膜の信頼
性が劣化する傾向がある。さらに、図１の縦軸に対数目
盛りを用いていることを考慮すると、比Ｔ１／（Ｔ１＋
Ｔ２）を０．２以下に設定することは、high-kゲート絶
縁膜の信頼性を飛躍的に向上させる効果を持っているこ
とが分かる。具体的には、比Ｔ１／（Ｔ１＋Ｔ２）を
０．２以下に設定することによって、例えば比Ｔ１／
（Ｔ１＋Ｔ２）が０．５程度である場合と比べて、信頼
性寿命を３桁以上も長くすることができる。As shown in FIG. 1, the ratio T1 / (T1 + T
2) That is, when the ratio of the interface layer thickness to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability of the high-k gate insulating film can be maintained high. In addition, the ratio T1 / (T1
As + T2) increases, the reliability of the high-k gate insulating film tends to deteriorate. Further, considering that the vertical axis of FIG. 1 uses a logarithmic scale, the ratio T1 / (T1 +
It can be seen that setting T2) to 0.2 or less has the effect of dramatically improving the reliability of the high-k gate insulating film. Specifically, by setting the ratio T1 / (T1 + T2) to 0.2 or less, for example, the ratio T1 /
As compared with the case where (T1 + T2) is about 0.5, the reliability life can be extended by three digits or more.
【００１５】また、図１に示すように、比Ｔ１／（Ｔ１
＋Ｔ２）が０．０〜０．２である構造を持つゲート絶縁
膜においては、high-k層の比誘電率ε２が８．０から１
２．０へ増加するに従って信頼性寿命の長さも増加し、
ε２が１２．０から１８．０までの範囲で信頼性寿命の
長さがほぼ飽和して最大値を示す。一方、ε２が１８．
０から２４．０へ増加すると、信頼性寿命の長さは逆に
減少してしまう。ところで、一般的に、high-k層におけ
る比誘電率ε２の値は厚さ方向に変化している。従っ
て、high-k層における比誘電率ε２の平均値をε２avと
したときには、ε２avは１２．０以上で且つ１８．０以
下であることが好ましい。また、high-k層として、一の
金属とシリコンと酸素とを含むシリケート膜を用いた場
合、high-k層の組成をＭXＳｉYＯ（但しＭは一の金属を
表し、Ｘ＞０、Ｙ＞０である）とすると、前述の１２．
０≦ε２av≦１８．０の条件は、０．２０≦Ｙ／（Ｘ＋
Ｙ）≦０．３０の条件と等価である。すなわち、high-k
ゲート絶縁膜の信頼性の観点からは、high-k層の材料と
してシリコンを含まない完全な金属酸化物を用いるより
も、０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０の関係を満た
す、シリコン含有のシリケートＭXＳｉYＯを用いた方が
好ましい。その理由は、high-k層と界面層との間の比誘
電率の差を小さくすることによって、界面層への電界集
中が緩和されるためと考えられる。尚、界面層もＭXＳ
ｉYＯで表せるシリケートを含むことがあるが、このシ
リケートにおけるＹ／（Ｘ＋Ｙ）は０．９０以上であっ
て、組成的にはＳｉＯ2 とほぼ同等である。Further, as shown in FIG. 1, the ratio T1 / (T1
In the gate insulating film having a structure in which + T2) is 0.0 to 0.2, the relative dielectric constant ε2 of the high-k layer is 8.0 to 1
As it increases to 2.0, the length of reliability life also increases,
When ε2 is in the range of 12.0 to 18.0, the length of reliability life is almost saturated and shows the maximum value. On the other hand, ε2 is 18.
When it is increased from 0 to 24.0, the reliability life length is decreased. By the way, generally, the value of the relative permittivity ε2 in the high-k layer changes in the thickness direction. Therefore, when the average value of the dielectric constant .epsilon.2 in high-k layer and .epsilon.2 av is, .epsilon.2 av is preferably at and 18.0 or less at 12.0 or higher. When a silicate film containing one metal, silicon and oxygen is used as the high-k layer, the composition of the high-k layer is M X Si Y O (where M represents one metal and X> 0. , Y> 0).
The condition of 0 ≦ ε2 av ≦ 18.0 is 0.20 ≦ Y / (X +
Y) is equivalent to the condition of 0.30. I.e. high-k
From the viewpoint of the reliability of the gate insulating film, the relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30 is satisfied, as compared with the case where a perfect metal oxide containing no silicon is used as the material of the high-k layer. It is preferred to use a silicon-containing silicate M X Si Y O. It is considered that the reason is that the electric field concentration on the interface layer is relaxed by reducing the difference in the relative dielectric constant between the high-k layer and the interface layer. Note that the interface layer be M X S
Although it may contain a silicate that can be represented by i Y O, Y / (X + Y) in this silicate is 0.90 or more, and is compositionally similar to SiO 2 .
【００１６】さらに、本願発明者は、high-kゲート絶縁
膜の信頼性寿命の長さと、界面層厚さＴ１のhigh-kゲー
ト絶縁膜全体の厚さ（Ｔ１＋Ｔ２）（但しＴ２はhigh-k
層の物理的厚さ）に対する比との相関を実験により調べ
てみた。その結果を図２に示す。尚、実験に用いた界面
層は、組成がＳｉＯ2 に近いＳｉＯＮ膜（比誘電率ε１
＝３．９）であり、実験に用いたhigh-k層はＣＶＤ（ch
emical vapor deposition ）法により形成されたＳｉ3
Ｎ4膜（比誘電率ε２＝７．５）である。また、実験に
おいては、high-kゲート絶縁膜のＥＯＴが常に３．０ｎ
ｍを保つように各物理的厚さＴ１及びＴ２を調整しなが
ら比Ｔ１／（Ｔ１＋Ｔ２）を変化させていった場合にお
ける、印加電圧３．５Ｖのストレス下（温度は１００
℃）で絶縁破壊が生じるまでに絶縁膜に注入された総電
荷量（絶縁破壊総電荷量Ｑbd）を測定した。ここで、絶
縁破壊総電荷量Ｑbdの大きさがhigh-kゲート絶縁膜の信
頼性寿命の長さと対応する。Furthermore, the inventor of the present application has found that the reliability life of the high-k gate insulating film is long and the total thickness of the high-k gate insulating film of the interface layer thickness T1 (T1 + T2) (where T2 is high-k).
The correlation with the ratio to the physical thickness of the layer) was investigated experimentally. The result is shown in FIG. The interface layer used in the experiment was a SiON film (relative dielectric constant ε1) having a composition close to that of SiO 2.
= 3.9), the high-k layer used in the experiment is CVD (ch
Si 3 formed by emical vapor deposition) method
It is an N 4 film (relative permittivity ε2 = 7.5). In addition, in the experiment, the EOT of the high-k gate insulating film was always 3.0n.
When the ratio T1 / (T1 + T2) is changed while adjusting the physical thicknesses T1 and T2 so as to keep m, the applied voltage is 3.5 V under stress (temperature is 100
The total amount of electric charges injected into the insulating film (dielectric breakdown total amount of charge Q bd ) until the dielectric breakdown occurred at (° C.) was measured. Here, the magnitude of the total amount Qbd of dielectric breakdown corresponds to the length of the reliability life of the high-k gate insulating film.
【００１７】図２に示すように、比Ｔ１／（Ｔ１＋Ｔ
２）が０．２以下である場合、high-kゲート絶縁膜の信
頼性を高く維持できる一方、該比が０．３を越えると信
頼性が急激に劣化することが実験的に実証された。ま
た、図２の縦軸に対数目盛りを用いていることを考慮す
ると、比Ｔ１／（Ｔ１＋Ｔ２）を０．２以下に設定する
ことは、high-kゲート絶縁膜の信頼性を飛躍的に向上さ
せる効果を持っていることが分かる。As shown in FIG. 2, the ratio T1 / (T1 + T
It was experimentally proved that the reliability of the high-k gate insulating film can be kept high when 2) is 0.2 or less, while the reliability is rapidly deteriorated when the ratio exceeds 0.3. . Considering that the vertical axis of FIG. 2 uses a logarithmic scale, setting the ratio T1 / (T1 + T2) to 0.2 or less dramatically improves the reliability of the high-k gate insulating film. You can see that it has an effect.
【００１８】以上のように、図１及び図２に示す結果か
ら、high-kゲート絶縁膜の信頼性の観点からは、界面層
厚さＴ１の全体厚さ（Ｔ１＋Ｔ２）に対する比を０．３
以下にすることが必須であり、また、比Ｔ１／（Ｔ１＋
Ｔ２）を０．２以下にすることがより好ましい。As described above, from the results shown in FIGS. 1 and 2, from the viewpoint of the reliability of the high-k gate insulating film, the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) is 0.3.
It is essential to make the ratio below, and the ratio T1 / (T1 +
It is more preferable that T2) is 0.2 or less.
【００１９】本発明は、以上の知見に基づきなされたも
のであって、具体的には、本発明に係る半導体装置は、
半導体基板上に形成された高誘電率絶縁膜を有する半導
体装置を前提とし、高誘電率絶縁膜は、半導体基板との
界面に形成された界面層と、界面層の上に形成され、界
面層よりも比誘電率が高い高誘電率層とを有し、界面層
の厚さＴ１及び高誘電率層の厚さＴ２は、Ｔ１／（Ｔ１
＋Ｔ２）≦０．３の関係を満たす。The present invention has been made based on the above findings. Specifically, the semiconductor device according to the present invention is
Assuming a semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate, the high dielectric constant insulating film is formed on an interface layer formed on the interface with the semiconductor substrate and on the interface layer. And a high dielectric constant layer having a relative dielectric constant higher than that of the interface layer, the thickness T1 of the interface layer and the thickness T2 of the high dielectric constant layer are T1 / (T1
+ T2) ≦ 0.3 is satisfied.
【００２０】本発明の半導体装置によると、高誘電率絶
縁膜における界面層厚さＴ１の全体厚さ（Ｔ１＋Ｔ２）
に対する比を０．３以下にするため、高誘電率絶縁膜に
電圧が印加された場合にも界面層への電界集中を抑制で
きる。従って、このような高誘電率絶縁膜を用いること
によって、長い信頼性寿命を持つhigh-kゲート絶縁膜を
実現することができる。また、このとき、比誘電率の低
い界面層が薄く且つ比誘電率の高い高誘電率層が厚いの
で、high-kゲート絶縁膜のＥＯＴを小さくすることがで
きる。According to the semiconductor device of the present invention, the total thickness (T1 + T2) of the interface layer thickness T1 in the high dielectric constant insulating film.
Since the ratio is less than 0.3, the electric field concentration on the interface layer can be suppressed even when a voltage is applied to the high dielectric constant insulating film. Therefore, by using such a high dielectric constant insulating film, a high-k gate insulating film having a long reliability life can be realized. Further, at this time, since the interface layer having a low relative permittivity is thin and the high dielectric constant layer having a high relative permittivity is thick, the EOT of the high-k gate insulating film can be reduced.
【００２１】本発明の半導体装置において、Ｔ１及びＴ
２は、Ｔ１／（Ｔ１＋Ｔ２）≦０．２の関係を満たすこ
とが好ましい。In the semiconductor device of the present invention, T1 and T
2 preferably satisfies the relationship of T1 / (T1 + T2) ≦ 0.2.
【００２２】このようにすると、高誘電率絶縁膜の信頼
性をより向上させることができる。By doing so, the reliability of the high dielectric constant insulating film can be further improved.
【００２３】本発明の半導体装置において、界面層の比
誘電率ε１は３．９以上で且つ７．０以下であると共に
高誘電率層の比誘電率ε２は７．０よりも大きく、高誘
電率層における比誘電率ε２の平均値ε２avは１２．０
以上で且つ１８．０以下であることが好ましい。In the semiconductor device of the present invention, the interfacial layer has a relative permittivity ε1 of 3.9 or more and 7.0 or less, and the high permittivity layer has a relative permittivity ε2 of more than 7.0. The average value ε2 av of the relative permittivity ε2 in the refractive index layer is 12.0
It is preferably not less than 18.0.
【００２４】このようにすると、高誘電率層と界面層と
の間の比誘電率の差が所定の範囲内に制限されるため、
電圧印加時の界面層への電界集中がより緩和され、高誘
電率絶縁膜の信頼性をより向上させることができる。In this way, the difference in relative permittivity between the high dielectric constant layer and the interface layer is limited to within a predetermined range.
The concentration of an electric field on the interface layer when a voltage is applied is further alleviated, and the reliability of the high dielectric constant insulating film can be further improved.
【００２５】本発明の半導体装置において、界面層の比
誘電率ε１は３．９以上で且つ７．０以下であると共に
高誘電率層の比誘電率ε２は７．０よりも大きく、高誘
電率層は、一の金属とシリコンと酸素とを含むシリケー
トよりなり、高誘電率層の組成をＭXＳｉYＯ（但し、Ｍ
は一の金属を表し、Ｘ＞０、Ｙ＞０である）としたとき
に、Ｘ及びＹは、０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０
の関係を満たすことが好ましい。In the semiconductor device of the present invention, the relative permittivity ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative permittivity ε2 of the high dielectric constant layer is larger than 7.0. The high-permittivity layer is made of a silicate containing one metal, silicon and oxygen, and has a composition of the high dielectric constant layer of M X Si Y O (provided that M
Represents one metal, and X> 0, Y> 0), X and Y are 0.20 ≦ Y / (X + Y) ≦ 0.30.
It is preferable to satisfy the relationship of.
【００２６】このようにすると、高誘電率層の材料とし
てシリコンを含まない完全な金属酸化物を用いた場合と
比べて、高誘電率層と界面層との間の比誘電率の差が小
さくなるため、電圧印加時の界面層への電界集中がより
緩和され、その結果、高誘電率絶縁膜の信頼性をより向
上させることができる。By doing so, the difference in relative dielectric constant between the high dielectric constant layer and the interface layer is smaller than that in the case where a complete metal oxide containing no silicon is used as the material of the high dielectric constant layer. Therefore, the concentration of the electric field on the interface layer at the time of applying a voltage is further alleviated, and as a result, the reliability of the high dielectric constant insulating film can be further improved.
【００２７】本発明の半導体装置において、高誘電率層
は、ハフニウム又はジルコニウムとシリコンと酸素とを
含むシリケートよりなることが好ましい。In the semiconductor device of the present invention, the high dielectric constant layer is preferably made of silicate containing hafnium or zirconium, silicon and oxygen.
【００２８】このようにすると、長い信頼性寿命を持つ
high-kゲート絶縁膜を確実に実現することができる。By doing so, a long reliability life is provided.
A high-k gate insulating film can be reliably realized.
【００２９】[0029]
【発明の実施の形態】以下、本発明の一実施形態に係る
半導体装置及びその製造方法について図面を参照しなが
ら説明する。DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to the drawings.
【００３０】図３（ａ）〜（ｅ）は本実施形態に係る半
導体装置の製造方法の各工程を示す断面図である。3A to 3E are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to this embodiment.
【００３１】図３（ａ）に示すように、例えばＳｉ（１
００）基板１１上に素子分離用絶縁膜１２を形成し、そ
れによってデバイス領域ＲD を規定する。As shown in FIG. 3A, for example, Si (1
00) The element isolation insulating film 12 is formed on the substrate 11 to define the device region R D.
【００３２】次に、Ｓｉ基板１１に対して、標準ＲＣＡ
洗浄及び希釈ＨＦ洗浄を順次行なった後、例えばＮＨ3
ガス中でＳｉ基板１１に対して６００〜７００℃程度の
熱処理を行なう。これにより、図３（ｂ）に示すよう
に、デバイス領域ＲD のＳｉ基板１１上にシリコン窒化
膜（Ｓｉ3Ｎ4膜）１３が形成される。Next, for the Si substrate 11, the standard RCA
After sequentially performing washing and diluted HF washing, for example, NH 3
The Si substrate 11 is heat-treated at about 600 to 700 ° C. in a gas. As a result, as shown in FIG. 3B, the silicon nitride film (Si 3 N 4 film) 13 is formed on the Si substrate 11 in the device region R D.
【００３３】次に、図３（ｃ）に示すように、例えばＣ
ＶＤ法を用いて、Ｓｉ3Ｎ4膜１３の上にＨｆＯ2 膜１４
を形成する。具体的には、液体ＨｆソースであるＨｆ t
-butoxide （Ｃ16Ｈ36ＨｆＯ4 ）中にＮ2 等のキャリア
ガスを吹き込んでバブリングを行なう。これにより、液
体Ｈｆソースを気体状態にして該ソースガスをキャリア
ガスと共に反応炉内に導入し、５００℃程度の温度下で
ＲＴ−ＣＶＤ（RapidThermal CVD ）処理を使用してＨ
ｆＯ2 膜１４を形成する。このとき、ＨｆＯ2膜１４の
成長速度又は膜質の向上のために乾燥Ｏ2 ガスを反応炉
内に導入する。このように形成されたＨｆＯ2 膜１４に
対して組成分析を行なったところ、Ｈｆソース中にＨ
ｆ、Ｏ、Ｃ及びＨが含まれているため、ＨｆＯ2 膜１４
の内部に１〜２原子％程度以下の微量なＣ及びＨが含有
されていた。尚、反応炉内にはＮ2ガスも導入される
が、５００℃程度の温度下ではＮ2 ガスは非常に不活性
であるため、Ｎ2 ガスの寄与は非常に小さい。Next, as shown in FIG. 3C, for example, C
By using the VD method, the HfO 2 film 14 is formed on the Si 3 N 4 film 13.
To form. Specifically, Hf t which is a liquid Hf source
Bubbling is performed by blowing a carrier gas such as N 2 into butoxide (C 16 H 36 HfO 4 ). As a result, the liquid Hf source is turned into a gaseous state, the source gas is introduced into the reaction furnace together with the carrier gas, and the H-type gas is introduced into the reaction furnace at a temperature of about 500 ° C. using the RT-CVD (Rapid Thermal CVD) process.
The fO 2 film 14 is formed. At this time, dry O 2 gas is introduced into the reaction furnace in order to improve the growth rate or film quality of the HfO 2 film 14. The composition of the HfO 2 film 14 thus formed was analyzed.
Since it contains f, O, C and H, the HfO 2 film 14
A minute amount of C and H of about 1 to 2 atomic% or less was contained inside. Although N 2 gas is also introduced into the reaction furnace, the contribution of N 2 gas is very small because N 2 gas is very inactive at a temperature of about 500 ° C.
【００３４】次に、例えばＮ2 ガス中で、ＨｆＯ2 膜１
４に対して６００〜８００℃程度のＰＤＡ処理を３０秒
間程度行なう。これにより、Ｓｉ基板１１の酸化、Ｈｆ
Ｏ2膜１４からの水素の脱離、ＨｆＯ2 膜１４の緻密化
及び微結晶化、並びに、Ｓｉ基板１１又はＳｉ3Ｎ4膜１
３とＨｆＯ2 膜１４との間におけるＳｉ及びＨｆの相互
拡散等の反応が生じる。その結果、ＨｆＯ2 膜１４の堆
積当初（図３（ｃ）参照）における、Ｓｉ基板１１上に
Ｓｉ3Ｎ4膜１３が形成され且つＳｉ3Ｎ4膜１３上にＨｆ
Ｏ2 膜１４が形成された構造は、最終的に、図３（ｄ）
に示すように、Ｓｉ基板１１上に比誘電率の低い界面層
１５が形成され且つ界面層１５上に比誘電率の高いhigh
-k層１６が形成された構造に変化する。ここで、界面層
１５はＳｉＯ2 又はＳｉＯ2 の組成に近いシリケートよ
りなり、high-k層１６はＨｆＯ2又はＨｆＯ2 の組成に
近いシリケートよりなる。また、界面層１５及びhigh-k
層１６にはそれぞれ微量のＮが含まれる。Next, the HfO 2 film 1 is formed, for example, in N 2 gas.
4 is subjected to PDA treatment at about 600 to 800 ° C. for about 30 seconds. Thereby, oxidation of the Si substrate 11 and Hf
Desorption of hydrogen from the O 2 film 14, densification and microcrystallization of the HfO 2 film 14, and Si substrate 11 or Si 3 N 4 film 1
3 and the HfO 2 film 14 cause a reaction such as interdiffusion of Si and Hf. As a result, the initial deposition of the HfO 2 film 14 in (FIG. 3 (c) refer), Si the Si 3 N 4 film 13 on the substrate 11 is formed and Hf on the Si 3 N 4 film 13
The structure in which the O 2 film 14 is formed is finally shown in FIG.
As shown in FIG. 3, an interface layer 15 having a low relative dielectric constant is formed on the Si substrate 11, and a high relative dielectric constant is high on the interface layer 15.
The structure is changed to the -k layer 16. Here, the interface layer 15 is made of SiO 2 or a silicate having a composition close to that of SiO 2 , and the high-k layer 16 is made of HfO 2 or a silicate having a composition close to that of HfO 2 . In addition, the interface layer 15 and high-k
Each of the layers 16 contains a trace amount of N.
【００３５】次に、図３（ｅ）に示すように、界面層１
５とhigh-k層１６との積層構造を有するhigh-kゲート絶
縁膜の上に、例えばポリシリコンよりなるゲート電極１
７を形成する。具体的には、ＳｉＨ4 を用いて５４０℃
程度の蒸着温度でポリシリコン膜を形成した後、該ポリ
シリコン膜に対して例えば５×１０15ｃｍー2のドーズ量
でＰイオンを注入し、その後、イオン注入されたポリシ
リコン膜をパターン化することによりゲート電極１７を
形成する。これにより、ｎＭＯＳＦＥＴ構造が完成す
る。尚、ゲート電極１７に注入された不純物に対する活
性化アニールは、乾燥Ｎ2 ガス中における９００℃、３
０秒間のＲＴＰ（Rapid Thermal Process）により行な
った。Next, as shown in FIG. 3E, the interface layer 1
The gate electrode 1 made of, for example, polysilicon is formed on the high-k gate insulating film having a laminated structure of 5 and the high-k layer 16.
Form 7. Specifically, using SiH 4 at 540 ° C
After forming a polysilicon film at a vapor deposition temperature of about 5 nm, P ions are implanted into the polysilicon film at a dose amount of, for example, 5 × 10 15 cm −2, and then the ion-implanted polysilicon film is patterned. By doing so, the gate electrode 17 is formed. This completes the nMOSFET structure. The activation annealing for the impurities injected into the gate electrode 17 was performed at 900 ° C. for 3 times in dry N 2 gas.
It was performed by RTP (Rapid Thermal Process) for 0 seconds.
【００３６】本実施形態の特徴は、例えばＨｆＯ2 膜１
４の形成前にＳｉ基板１１上にＳｉ 3Ｎ4膜１３を形成す
ることにより、又は例えばＨｆＯ2 膜１４に対するＰＤ
Ａの処理温度を低めに設定したり若しくは該ＰＤＡの処
理時間を短めに設定すること等により、high-kゲート絶
縁膜全体の厚さに対する界面層１５の厚さの比を所定の
範囲内に設定することである。具体的には、high-kゲー
ト絶縁膜全体の厚さ、つまり界面層１５の厚さＴ１とhi
gh-k層１６の厚さＴ２との合計厚さ（Ｔ１＋Ｔ２）に対
する界面層１５の厚さＴ１の比を０．３以下、より好ま
しくは０．２以下に設定することである。これにより、
本実施形態においては、ゲート電圧印加時にも界面層１
５への電界集中を抑制できるので、長い信頼性寿命を持
つhigh-kゲート絶縁膜を実現することができる。また、
界面層１５とhigh-k層１６とが積層されてなるゲート絶
縁膜を有するＭＯＳキャパシタに対して、ＬＣＲ（indu
ctance - capacitance - resistance ）メータを用いて
ＣＶ（capacitance - voltage ）測定を行ない、その測
定結果に基づいて、ゲート電極の空乏化又は基板の量子
化効果等を考慮して、シミュレーションプログラムによ
りゲート絶縁膜のＥＯＴを算出したところ、十分に小さ
なＥＯＴが得られた。すなわち、本実施形態において
は、比誘電率の低い界面層１５が薄く且つ比誘電率の高
いhigh-k層１６が厚いので、high-kゲート絶縁膜のＥＯ
Ｔを小さくすることができる。The feature of this embodiment is, for example, HfO.2Membrane 1
4 is formed on the Si substrate 11 before the formation of 3NFourForm the film 13
Or, for example, HfO2PD for membrane 14
Set the processing temperature of A to a lower value or treat the PDA.
By setting a short processing time, high-k gate
The ratio of the thickness of the interface layer 15 to the thickness of the entire border film is set to a predetermined value.
It is to be set within the range. Specifically, high-k game
The total thickness of the insulating film, that is, the thickness T1 of the interface layer 15 and hi
The thickness T2 of the gh-k layer 16 and the total thickness (T1 + T2)
The ratio of the thickness T1 of the interface layer 15 is 0.3 or less, more preferably
Specifically, it should be set to 0.2 or less. This allows
In this embodiment, the interface layer 1 is applied even when the gate voltage is applied.
Since the electric field concentration on 5 can be suppressed, it has a long reliability life.
A high-k gate insulating film can be realized. Also,
A gate insulating layer formed by stacking an interface layer 15 and a high-k layer 16
LCR (indu
ctance-capacitance-resistance)
CV (capacitance-voltage) measurement is performed and
Based on the determined result, the depletion of the gate electrode or the quantum of the substrate
The simulation program will
Calculated EOT of the gate insulating film is sufficiently small
EOT was obtained. That is, in this embodiment
Indicates that the interface layer 15 having a low relative permittivity is thin and has a high relative permittivity.
Since the high-k layer 16 is thick, the EO of the high-k gate insulating film
T can be reduced.
【００３７】図４（ａ）は、本実施形態の半導体装置、
つまりＨｆプレカーサーを用いて形成されたＨｆＯ2 誘
電体をhigh-k材料とするゲート絶縁膜を備えたＭＯＳＦ
ＥＴの高分解能断面ＴＥＭ（transmission electron mi
croscope）像を示している。図４（ａ）に示すように、
本実施形態の半導体装置におけるhigh-kゲート絶縁膜の
全体厚さ（界面層１５の厚さＴ１とhigh-k層１６の厚さ
Ｔ２との合計（Ｔ１＋Ｔ２））は３．０〜３．３ｎｍ程
度である。また、界面層１５の厚さＴ１は０．４〜０．
５ｎｍ程度である。すなわち、high-kゲート絶縁膜全体
の厚さに対する界面層１５の厚さの比Ｔ１／（Ｔ１＋Ｔ
２）は０．１２〜０．１７程度であり、本発明で推奨す
る関係：Ｔ１／（Ｔ１＋Ｔ２）≦０．３（より好ましく
はＴ１／（Ｔ１＋Ｔ２）≦０．２）を十分に満たしてい
る。FIG. 4A shows the semiconductor device of this embodiment.
That is, a MOSF having a gate insulating film made of a HfO 2 dielectric formed by using an Hf precursor and having a high-k material.
High resolution TEM (transmission electron mi) of ET
croscope) image is shown. As shown in FIG.
The total thickness of the high-k gate insulating film (the total thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 (T1 + T2)) in the semiconductor device of this embodiment is 3.0 to 3.3 nm. It is a degree. The thickness T1 of the interface layer 15 is 0.4 to 0.
It is about 5 nm. That is, the ratio of the thickness of the interface layer 15 to the total thickness of the high-k gate insulating film T1 / (T1 + T
2) is about 0.12 to 0.17, which sufficiently satisfies the relationship recommended by the present invention: T1 / (T1 + T2) ≦ 0.3 (more preferably T1 / (T1 + T2) ≦ 0.2). .
【００３８】図４（ｂ）は、比較例としての半導体装
置、つまり本実施形態と同様の方法により形成されたＨ
ｆＯ2 誘電体をhigh-k材料とするゲート絶縁膜を備えた
他のＭＯＳＦＥＴの高分解能断面ＴＥＭ像を示してい
る。図４（ｂ）に示すように、比較例の半導体装置にお
いては、図４（ａ）に示す本実施形態のＭＯＳキャパシ
タ構造と対応するように、Ｓｉ基板２１上に、界面層２
５とhigh-k層２６との積層構造からなるゲート絶縁膜を
介して、Ｐｏｌｙ−Ｓｉよりなるゲート電極２７が形成
されている。また、比較例の半導体装置においては、hi
gh-kゲート絶縁膜の全体厚さ（界面層２５の厚さＴ１’
とhigh-k層２６の厚さＴ２’との合計（Ｔ１’＋Ｔ
２’））は３．０〜３．３ｎｍ程度である。また、界面
層２５の厚さＴ１’は１．０ｎｍ程度である。すなわ
ち、high-kゲート絶縁膜全体の厚さに対する界面層２５
の厚さの比Ｔ１’／（Ｔ１’＋Ｔ２’）は０．３０〜
０．３３程度であり、前述の本発明で推奨する関係を満
たしていない。FIG. 4B shows a semiconductor device as a comparative example, that is, H formed by the same method as this embodiment.
7 shows a high-resolution cross-sectional TEM image of another MOSFET provided with a gate insulating film using a fO 2 dielectric as a high-k material. As shown in FIG. 4B, in the semiconductor device of the comparative example, the interface layer 2 is formed on the Si substrate 21 so as to correspond to the MOS capacitor structure of this embodiment shown in FIG.
A gate electrode 27 made of Poly-Si is formed via a gate insulating film having a laminated structure of the No. 5 and the high-k layer 26. In the semiconductor device of the comparative example, hi
Total thickness of gh-k gate insulating film (thickness T1 ′ of interface layer 25)
And the thickness T2 ′ of the high-k layer 26 (T1 ′ + T
2 ')) is about 3.0 to 3.3 nm. The thickness T1 ′ of the interface layer 25 is about 1.0 nm. That is, the interface layer 25 with respect to the total thickness of the high-k gate insulating film
The thickness ratio T1 '/ (T1' + T2 ') is 0.30
It is about 0.33, which does not satisfy the above-mentioned relationship recommended by the present invention.
【００３９】図４（ａ）に示す本実施形態のＭＯＳキャ
パシタ構造、及び、図４（ｂ）に示す比較例のＭＯＳキ
ャパシタ構造のそれぞれについて、ゲート面積を５００
０μｍ2 として、印加電圧３．０Ｖ（ゲート電極側が低
電位）のストレス下（温度は室温）でのゲート絶縁膜の
信頼性寿命を算出した。その結果、界面層の相対厚さが
小さい本実施形態のゲート絶縁膜の信頼性寿命は１×１
０4 秒程度であり、界面層の相対厚さが大きい比較例の
ゲート絶縁膜の信頼性寿命は１×１０2 秒程度であっ
た。すなわち、high-kゲート絶縁膜全体の厚さに対する
界面層の厚さの比Ｔ１／（Ｔ１＋Ｔ２）が０．２以下で
あると、high-kゲート絶縁膜の信頼性寿命が劇的に向上
する。これは、Ｓｉ基板表面に形成される低誘電率の界
面層を薄くできると、該界面層に集中する強い電界強度
に起因して信頼性劣化が生じる事態を回避できるためと
考えられる。For each of the MOS capacitor structure of this embodiment shown in FIG. 4A and the MOS capacitor structure of the comparative example shown in FIG. 4B, the gate area is 500.
The reliability life of the gate insulating film under stress (at room temperature) under an applied voltage of 3.0 V (low potential on the gate electrode side) was calculated as 0 μm 2 . As a result, the reliability life of the gate insulating film according to the present embodiment in which the relative thickness of the interface layer is small is 1 × 1.
0 is about 4 seconds, reliability life of the gate insulating film of Comparative Example relative thickness is large interfacial layer was about 1 × 10 2 seconds. That is, when the ratio T1 / (T1 + T2) of the thickness of the interface layer to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability life of the high-k gate insulating film is dramatically improved. . This is considered to be because if the interface layer having a low dielectric constant formed on the surface of the Si substrate can be thinned, it is possible to avoid the situation where reliability is deteriorated due to the strong electric field strength concentrated on the interface layer.
【００４０】ところで、図４（ａ）及び（ｂ）に示すよ
うに、high-kゲート絶縁膜の高分解能断面ＴＥＭ像にお
いては、界面層の像はhigh-k層の像と比べて明らかに白
くなる。ここで、high-kゲート絶縁膜の組成をＨｆXＳ
ｉYＯ（但しＸ＞０、Ｙ＞０）とすると、Ｙ／（Ｘ＋
Ｙ）＝０．９０が界面層とhigh-k層との境界に対応す
る。尚、high-kゲート絶縁膜の組成は、Ｓｉ基板側から
次第にＳｉ組成が減少するように、言い換えると、Ｙ／
（Ｘ＋Ｙ）の値が１．０から次第に減少するように変化
する。すなわち、０．９０≦Ｙ／（Ｘ＋Ｙ）≦１．０の
関係を満たす範囲が界面層であり、Ｙ／（Ｘ＋Ｙ）＜
０．９０の関係を満たす範囲がhigh-k層である。このと
き、界面層の比誘電率ε１は３．９以上で且つ７．０以
下であると共にhigh-k層の比誘電率ε２は７．０よりも
大きい。By the way, as shown in FIGS. 4A and 4B, in the high-resolution cross-sectional TEM image of the high-k gate insulating film, the image of the interface layer is clearer than that of the high-k layer. It becomes white. Here, the composition of the high-k gate insulating film is set to Hf X S
i Y O (where X> 0, Y> 0), Y / (X +
Y) = 0.90 corresponds to the boundary between the interface layer and the high-k layer. The composition of the high-k gate insulating film is such that the Si composition gradually decreases from the Si substrate side, in other words, Y /
The value of (X + Y) changes from 1.0 to gradually decrease. That is, the range satisfying the relationship of 0.90 ≦ Y / (X + Y) ≦ 1.0 is the interface layer, and Y / (X + Y) <
The range that satisfies the relationship of 0.90 is the high-k layer. At this time, the relative permittivity ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative permittivity ε2 of the high-k layer is larger than 7.0.
【００４１】尚、本実施形態において、Ｓｉ基板１１上
にＳｉ3Ｎ4膜１３を介してＨｆＯ2膜１４を形成した
後、ＨｆＯ2 膜１４に対してＰＤＡ処理を行ない、それ
により、界面層１５とhigh-k層１６との積層構造を有す
るhigh-kゲート絶縁膜を形成したが、このとき、窒素原
子がゲート絶縁膜のいずれかの部分（基板近傍、電極近
傍、膜中央部等）に含まれていてもよい。また、ＰＤＡ
処理条件は特に限定されるものではないが、ＰＤＡ処理
温度は８００℃程度以下であり、ＰＤＡ処理温度は３０
秒程度以下であることが好ましい。[0041] In the present embodiment, after forming the HfO 2 film 14 via the Si 3 N 4 film 13 on the Si substrate 11, performs PDA processing on the HfO 2 film 14, whereby the interfacial layer A high-k gate insulating film having a laminated structure of 15 and a high-k layer 16 was formed. At this time, nitrogen atoms were present at any part of the gate insulating film (near the substrate, near the electrode, central part of the film, etc.). May be included in. Also, PDA
The treatment conditions are not particularly limited, but the PDA treatment temperature is about 800 ° C. or lower, and the PDA treatment temperature is 30
It is preferably about a second or less.
【００４２】また、本実施形態において、液体Ｈｆソー
スであるHf t-butoxide を用いてＨｆＯ2 膜１４を形成
したが、ＨｆＯ2 膜１４の形成方法は特に限定されるも
のではない。具体的には、例えば固体原料であるＨｆ n
itrato（Ｈｆ（ＮＯ3）4）を加熱して液体状態にすると
共に該液状の原料中にＡｒ等のキャリアガスを吹き込ん
でバブリングを行なった後、気化した原料をキャリアガ
スと共に、基板ヒーターとコールドウォールとを有する
ＣＶＤ装置の反応炉内に導入し、その後、２００℃程度
の温度下でＲＴ−ＣＶＤ処理を使用してＨｆＯ2 膜１４
を形成してもよい。このとき、ＨｆＯ2 膜１４の成長速
度又は膜質の向上のために乾燥Ｏ2 ガスを反応炉内に導
入する。このように形成されたＨｆＯ2 膜１４に対して
組成分析を行なった場合、Ｈｆソース中にＨｆ、Ｏ、及
びＮが含まれているため、ＨｆＯ 2 膜１４の内部に１〜
２原子％程度以下の微量なＮが含有される。尚、反応炉
内にはＡｒガスも導入されるが、２００℃程度の温度下
ではＡｒガスは非常に不活性であるため、Ａｒガスの寄
与は非常に小さい。In the present embodiment, the liquid Hf saw
HfO using Hft-butoxide2Form the film 14
However, HfO2The method for forming the film 14 is not particularly limited.
Not of. Specifically, for example, Hf n, which is a solid raw material,
itrato (Hf (NO3)Four) Is heated to a liquid state
A carrier gas such as Ar is blown into the liquid raw material together.
After bubbling in, the vaporized raw material is
With a substrate heater and cold wall
Introduced into the reaction furnace of the CVD equipment, then about 200 ℃
At room temperature using RT-CVD process2Membrane 14
May be formed. At this time, HfO2Growth rate of film 14
Dry O to improve the degree or film quality2Guide gas into reactor
To enter. HfO formed in this way2For membrane 14
When composition analysis was performed, Hf, O, and
And N are included, HfO 21 to inside the membrane 14
A trace amount of N of about 2 atomic% or less is contained. Incidentally, the reaction furnace
Ar gas is also introduced inside, but at a temperature of about 200 ° C
However, since Ar gas is very inert, the Ar gas
The award is very small.
【００４３】また、本実施形態において、high-kゲート
絶縁膜（つまりその中のhigh-k層１６）の材料としてＨ
ｆＯ2 を用いた。しかし、これに代えて、他の金属酸化
物、具体的には、Ｈｆと同様の性質を持つＺｒの酸化物
（ＺｒＯ2 ）、ＴｉＯ2 、Ｔａ2Ｏ5、Ｌａ2Ｏ3又はＡｌ
2Ｏ3等を用いた場合にも、界面層１５の厚さＴ１及びhi
gh-k層１６の厚さＴ２がＴ１／（Ｔ１＋Ｔ２）≦０．３
の関係（より好ましくはＴ１／（Ｔ１＋Ｔ２）≦０．２
の関係）を満たす限り、high-kゲート絶縁膜の信頼性寿
命について本実施形態と同様の劇的な向上効果が生じ
る。特に、界面層の比誘電率ε１が３．９以上で且つ
７．０以下であると共にhigh-k層１６の比誘電率ε２が
７．０よりも大きく、さらに、high-k層１６における比
誘電率ε２の平均値ε２avが１２．０以上で且つ１８．
０以下である場合には、次のような特別な効果が得られ
る。すなわち、high-k層１６と界面層１５との間の比誘
電率の差が所定の範囲内に制限されるため、電圧印加時
の界面層１５への電界集中がより緩和され、high-kゲー
ト絶縁膜の信頼性をより向上させることができる。Further, in this embodiment, H is used as the material of the high-k gate insulating film (that is, the high-k layer 16 therein).
fO 2 was used. However, instead of this, another metal oxide, specifically, an oxide of Zr (ZrO 2 ), TiO 2 , Ta 2 O 5 , La 2 O 3 or Al having the same properties as Hf is used.
Even when 2 O 3 or the like is used, the thickness T1 of the interface layer 15 and hi
The thickness T2 of the gh-k layer 16 is T1 / (T1 + T2) ≦ 0.3
Relationship (more preferably T1 / (T1 + T2) ≦ 0.2
As long as the relationship (1) is satisfied, the same dramatic improvement effect as that of the present embodiment occurs in the reliability life of the high-k gate insulating film. In particular, the relative permittivity ε1 of the interface layer is 3.9 or more and 7.0 or less, the relative permittivity ε2 of the high-k layer 16 is larger than 7.0, and The average value ε2 av of the dielectric constant ε2 is 12.0 or more and 18.
When it is 0 or less, the following special effects are obtained. That is, since the difference in the relative dielectric constant between the high-k layer 16 and the interface layer 15 is limited within a predetermined range, the electric field concentration on the interface layer 15 when a voltage is applied is further relaxed, and the high-k The reliability of the gate insulating film can be further improved.
【００４４】また、本実施形態において、high-kゲート
絶縁膜（つまりその中のhigh-k層１６）の材料として、
組成がＭXＳｉYＯ（但しＭは一の金属を表し、Ｘ＞０、
Ｙ＞０である）で表される金属シリケート（金属、シリ
コン及び酸素以外の元素を含んでいてもよい）、例えば
Ｈｆシリケート（ＨｆXＳｉYＯ2 ）又はＺｒシリケート
（ＺｒXＳｉYＯ2 ）等を用いた場合にも、比Ｔ１／（Ｔ
１＋Ｔ２）≦０．３の関係（好ましくはＴ１／（Ｔ１＋
Ｔ２）≦０．２の関係）を満たす限り、high-kゲート絶
縁膜の信頼性寿命について本実施形態と同様の劇的な向
上効果が生じる。特に、界面層の比誘電率ε１が３．９
以上で且つ７．０以下であると共にhigh-k層１６の比誘
電率ε２が７．０よりも大きく、さらに、high-k層１６
が０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０の関係を満たす
金属シリケートＭXＳｉYＯである場合には、次のような
特別な効果が得られる。すなわち、シリコンを含まない
完全な金属酸化物を用いた場合と比べて、high-k層１６
と界面層１５との間の比誘電率の差が小さくなるため、
電圧印加時の界面層１５への電界集中がより緩和され、
その結果、high-kゲート絶縁膜の信頼性をより向上させ
ることができる。Further, in this embodiment, as a material of the high-k gate insulating film (that is, the high-k layer 16 therein),
The composition is M X Si Y O (where M represents one metal, X> 0,
Y> 0) represented by metal silicate (may contain elements other than metal, silicon and oxygen) such as Hf silicate (Hf X Si Y O 2 ) or Zr silicate (Zr X Si Y O 2). ) Etc., the ratio T1 / (T
1 + T2) ≦ 0.3 (preferably T1 / (T1 +
As long as T2) ≤ 0.2) is satisfied, the reliability life of the high-k gate insulating film is dramatically improved as in the present embodiment. In particular, the relative dielectric constant ε1 of the interface layer is 3.9.
The dielectric constant ε2 of the high-k layer 16 is more than 7.0 and less than 7.0, and is larger than 7.0.
Is a metal silicate M X Si Y O satisfying the relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30, the following special effects are obtained. That is, as compared with the case of using a complete metal oxide containing no silicon, the high-k layer 16
Since the difference in relative dielectric constant between the interface layer 15 and the interface layer 15 becomes small,
The electric field concentration on the interface layer 15 when a voltage is applied is further relaxed,
As a result, the reliability of the high-k gate insulating film can be further improved.
【００４５】ところで、本実施形態のＨｆＯ2 膜１４に
代えて例えばＨｆシリケート膜を形成する場合、次のよ
うな方法を用いることができる。すなわち、液体Ｈｆソ
ースであるＨｆ t-butoxide （Ｃ16Ｈ36ＨｆＯ4 ）及び
ＳｉソースであるＴＤＥＡＳ（Tetrakis Diethyl Amino
Silicon：Si[N(C2H5)2]4 ）を気化して、キャリアガス
であるＮ2 ガスと共に反応炉内に導入した後、３００〜
５００℃程度の温度下でＣＶＤ処理を行なうことによ
り、Ｈｆシリケート膜を形成できる。このとき、Ｈｆソ
ースとＳｉソースとの混合比、又はＣＶＤ処理の温度を
調節することによって、Ｈｆシリケート膜の組成を変化
させることができる。また、Ｈｆシリケート膜の成長速
度又は膜質の向上のために、乾燥Ｏ2 ガスを反応炉内に
導入してもよい。By the way, in the case of forming, for example, an Hf silicate film in place of the HfO 2 film 14 of this embodiment, the following method can be used. That is, Hft-butoxide (C 16 H 36 HfO 4 ) which is a liquid Hf source and TDEAS (Tetrakis Diethyl Amino) which is a Si source.
Silicon: vaporizing Si [N (C 2 H 5 ) 2] 4), was introduced into the reactor with N 2 gas as a carrier gas, 300
The Hf silicate film can be formed by performing the CVD process at a temperature of about 500 ° C. At this time, the composition of the Hf silicate film can be changed by adjusting the mixing ratio of the Hf source and the Si source or the temperature of the CVD process. Further, dry O 2 gas may be introduced into the reaction furnace in order to improve the growth rate or film quality of the Hf silicate film.
【００４６】また、本実施形態において、基板としてＳ
ｉ基板１１を用いたが、これに代えて、他の半導体基
板、例えばＳｉＧｅ基板又はＳｉＣ基板等を用いてもよ
い。Further, in this embodiment, S is used as the substrate.
Although the i substrate 11 is used, another semiconductor substrate such as a SiGe substrate or a SiC substrate may be used instead of the i substrate 11.
【００４７】また、本実施形態において、ゲート電極１
７としてＰｏｌｙ−Ｓｉゲート電極を用いたが、これに
代えて、メタルゲート電極を用いてもよい。具体的に
は、例えばＡｒスパッタによるＰＶＤ（physical vapor
deposition ）法を用いて、ＴｉＮ膜とＡｌ膜との積層
構造、又はＴａＮ膜の単層構造を有するメタルゲート電
極を形成してもよい。In this embodiment, the gate electrode 1
Although a Poly-Si gate electrode was used as 7, a metal gate electrode may be used instead of this. Specifically, for example, PVD (physical vapor) by Ar sputtering is used.
Deposition method may be used to form a metal gate electrode having a laminated structure of a TiN film and an Al film or a single-layer structure of a TaN film.
【００４８】[0048]
【発明の効果】本発明によると、high-kゲート絶縁膜に
おける界面層厚さＴ１の全体厚さ（Ｔ１＋Ｔ２）に対す
る比を０．３以下、より好ましくは０．２以下にするた
め、ゲート電圧印加時における界面層への電界集中を抑
制できるので、high-kゲート絶縁膜の信頼性寿命を向上
させることができる。According to the present invention, the ratio of the interface layer thickness T1 in the high-k gate insulating film to the total thickness (T1 + T2) is 0.3 or less, more preferably 0.2 or less. Since the electric field concentration on the interface layer during application can be suppressed, the reliability life of the high-k gate insulating film can be improved.
【図１】high-kゲート絶縁膜の信頼性寿命の長さと、界
面層厚さＴ１のhigh-kゲート絶縁膜全体の厚さ（Ｔ１＋
Ｔ２）（但しＴ２はhigh-k層の物理的厚さ）に対する比
との相関をシミュレーションを用いて調べた結果を示す
図である。FIG. 1 is the reliability life of the high-k gate insulating film and the total thickness of the high-k gate insulating film having an interface layer thickness T1 (T1 +
It is a figure which shows the result of having investigated the correlation with the ratio with respect to T2) (however, T2 is the physical thickness of a high-k layer) using simulation.
【図２】high-kゲート絶縁膜の信頼性寿命の長さと、界
面層厚さＴ１のhigh-kゲート絶縁膜全体の厚さ（Ｔ１＋
Ｔ２）（但しＴ２はhigh-k層の物理的厚さ）に対する比
との相関を実験により調べた結果を示す図である。FIG. 2 shows the reliability life of the high-k gate insulating film and the total thickness of the high-k gate insulating film having an interface layer thickness T1 (T1 +
It is a figure which shows the result of having investigated the correlation with the ratio with respect to T2) (however, T2 is the physical thickness of a high-k layer) by experiment.
【図３】（ａ）〜（ｅ）は本発明の一実施形態に係る半
導体装置の製造方法の各工程を示す断面図である。3A to 3E are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図４】（ａ）は本発明の一実施形態に係る半導体装置
の高分解能断面ＴＥＭ像を示す図であり、（ｂ）は比較
例に係る半導体装置の高分解能断面ＴＥＭ像を示す図で
ある。4A is a diagram showing a high-resolution cross-sectional TEM image of a semiconductor device according to an embodiment of the present invention, and FIG. 4B is a diagram showing a high-resolution cross-sectional TEM image of a semiconductor device according to a comparative example. is there.
【図５】従来の半導体装置の断面図である。FIG. 5 is a cross-sectional view of a conventional semiconductor device.
１１ Ｓｉ基板 １２ 素子分離用絶縁膜 １３ Ｓｉ3Ｎ4膜 １４ ＨｆＯ2 膜 １５ 界面層 １６ high-k層 １７ ゲート電極 ２１ Ｓｉ基板 ２５ 界面層 ２６ high-k層 ２７ ゲート電極 ＲD デバイス領域11 Si substrate 12 Element isolation insulating film 13 Si 3 N 4 film 14 HfO 2 film 15 Interface layer 16 high-k layer 17 Gate electrode 21 Si substrate 25 Interface layer 26 high-k layer 27 Gate electrode RD Device region
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F058 BA06 BA20 BD01 BD04 BD10 BD18 BF02 BF06 BH04 BJ04 BJ10 5F140 AA05 AA24 AC32 BA01 BA02 BA05 BA20 BD01 BD07 BD11 BD13 BD16 BE02 BE08 BE10 BE17 BF01 BF04 BG27 BG32 BG37 CB01 ─────────────────────────────────────────────────── ─── Continued front page F-term (reference) 5F058 BA06 BA20 BD01 BD04 BD10 BD18 BF02 BF06 BH04 BJ04 BJ10 5F140 AA05 AA24 AC32 BA01 BA02 BA05 BA20 BD01 BD07 BD11 BD13 BD16 BE02 BE08 BE10 BE17 BF01 BF04 BG27 BG32 BG37 CB01
Claims (5)
膜を有する半導体装置であって、 前記高誘電率絶縁膜は、 前記半導体基板との界面に形成された界面層と、 前記界面層の上に形成され、前記界面層よりも比誘電率
が高い高誘電率層とを有し、 前記界面層の厚さＴ１及び前記高誘電率層の厚さＴ２
は、 Ｔ１／（Ｔ１＋Ｔ２）≦０．３の関係を満たすことを特
徴とする半導体装置。1. A semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate, wherein the high dielectric constant insulating film includes an interface layer formed at an interface with the semiconductor substrate, and the interface layer. A high-dielectric layer having a relative dielectric constant higher than that of the interface layer, the thickness T1 of the interface layer and the thickness T2 of the high-dielectric layer.
Is a semiconductor device characterized by satisfying a relationship of T1 / (T1 + T2) ≦ 0.3.
徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein T1 and T2 satisfy a relationship of T1 / (T1 + T2) ≦ 0.2.
で且つ７．０以下であると共に前記高誘電率層の比誘電
率ε２は７．０よりも大きく、 前記高誘電率層における前記比誘電率ε２の平均値ε２
avは１２．０以上で且つ１８．０以下であることを特徴
とする請求項１に記載の半導体装置。3. The relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric constant layer is larger than 7.0. Mean value ε2 of the relative permittivity ε2 in
The semiconductor device according to claim 1, wherein av is 12.0 or more and 18.0 or less.
で且つ７．０以下であると共に前記高誘電率層の比誘電
率ε２は７．０よりも大きく、 前記高誘電率層は、一の金属とシリコンと酸素とを含む
シリケートよりなり、 前記高誘電率層の組成をＭXＳｉYＯ（但し、Ｍは前記一
の金属を表し、Ｘ＞０、Ｙ＞０である）としたときに、 Ｘ及びＹは、 ０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０の関係を満たすこ
とを特徴とする請求項１に記載の半導体装置。4. The relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric constant layer is larger than 7.0. Is a silicate containing one metal, silicon and oxygen, and has a composition of the high dielectric constant layer of M X Si Y O (where M represents the one metal, and X> 0, Y> 0). ), X and Y satisfy the relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30. 3. The semiconductor device according to claim 1, wherein
コニウムとシリコンと酸素とを含むシリケートよりなる
ことを特徴とする請求項１に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the high dielectric constant layer is made of silicate containing hafnium or zirconium, silicon and oxygen.
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| US29947801P | 2001-06-21 | 2001-06-21 | |
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| JP2006001334A Expired - Lifetime JP4712560B2 (en) | 2001-06-21 | 2006-01-06 | Manufacturing method of semiconductor device |
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| JP2007271175A Pending JP2008078675A (en) | 2001-06-21 | 2007-10-18 | Semiconductor device having high permittivity insulating film |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2011018926A (en) | 2011-01-27 |
| JP4165076B2 (en) | 2008-10-15 |
| JP2003008005A (en) | 2003-01-10 |
| JP2008078675A (en) | 2008-04-03 |
| JP4047075B2 (en) | 2008-02-13 |
| JP4712560B2 (en) | 2011-06-29 |
| JP3773448B2 (en) | 2006-05-10 |
| JP4713518B2 (en) | 2011-06-29 |
| JP2006165589A (en) | 2006-06-22 |
| JP2007194652A (en) | 2007-08-02 |
| JP2003008011A (en) | 2003-01-10 |
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