JP2002508099A - 異なるデータ・レートで動作するネットワーク・ポートに関して、共用メモリへのアクセスを調停する方法および装置 - Google Patents
異なるデータ・レートで動作するネットワーク・ポートに関して、共用メモリへのアクセスを調停する方法および装置Info
- Publication number
- JP2002508099A JP2002508099A JP50565599A JP50565599A JP2002508099A JP 2002508099 A JP2002508099 A JP 2002508099A JP 50565599 A JP50565599 A JP 50565599A JP 50565599 A JP50565599 A JP 50565599A JP 2002508099 A JP2002508099 A JP 2002508099A
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- access request
- arbiter
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
- H04L49/254—Centralised controller, i.e. arbitration or scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
- H04L49/352—Gigabit ethernet switching [GBPS]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.ネットワーク・システム内の多数のポート間で共用されたパケット・スイッ チ内でバッファ・メモリを管理する装置であって、 低速データ・ポートとバッファ・メモリの間で第1のデータ・レートでデータ を送るように構成された複数の低速データ・ポート・インタフェースと、 高速データ・ポートとバッファ・メモリの間で第2のデータ・レートでデータ を送るように構成された複数の高速データ・ポート・インタフェースと、 複数の低速データ・ポート・インタフェースに結合され、低速データ・ポート のうちの1つのアクセス要求を選択し、アクセス要求を出力するように構成され た第1のレベル・アービタと、 複数の高速データ・ポート・インタフェースと第1のレベル・アービタの出力 とに結合され、高速データ・ポート・インタフェースからの複数のアクセス要求 のうちのアクセス要求および第1のレベル・アービタからのアクセス要求からバ ッファ・メモリによって処理されるべきアクセス要求を選択するように構成され た第2のレベル・アービタとを含む装置。 2.第1のレベル・アービタが、 複数の低速データ・ポートからの複数のメモリ書込みアクセス要求を受け取り 、書込み許可信号を低速データ・ポートのうちの1つに送るように構成された調 停回路と、 複数の低速データ・ポートからの複数のコマンド・ワードを受け取り、調停回 路からの信号に応答してコマンド・ワードのうち1つを出力するように構成され たコマンド・マルチプレクサと、 複数の低速データ・ポートからの少なくとも1つのデータ・ワードの少なくと も1つのセグメントを受け取り、調停回路からの信号に対応してデータ・ワード のセグメントを出力するように構成されたデータ・マルチプレクサとを含む第1 のレベル書込みアービタ回路を含む請求項1に記載の装置。 3.第1のレベル書込みアービタがさらに、 コマンド・ワードを受け取るように構成されたロード回路と、 連続的なデータ・セグメントがデータ・マルチプレクサから受信され、ロード 回路からの信号に応答して蓄積され、複数の低速データ・ポートの1つからのデ ータ・ワード、タグ・ワード、および書込みアドレスを形成する蓄積回路を含む 請求項2に記載の装置。 4.蓄積回路が、第1のデータ・レジスタからの蓄積されたデータを並列にメモ リに出力し、同時に、第2のデータ・ワードを連続的なセグメントで第2のデー タ・レジスタ内に蓄積する請求項3に記載の装置。 5.データのセグメントの幅が16ビットであり、データ・ワードの幅が128 ビットである請求項4に記載の装置。 6.第1のレベル・アービタがさらに、 複数の低速データ・ポートからの複数のメモリ読取りアクセス要求を受け取り 、低速データ・ポートの1つに読取り許可信号を送るように構成された調停回路 と、 複数の低速データ・ポートからの複数の読取りアドレスを受け取り、調停回路 からの信号に応答して複数の読取りアドレスのうちの1つをメモリに送るように 構成された読取りアドレス・マルチプレクサとを含む第1のレベル読取りアービ タ回路を含む請求項2に記載の装置。 7.第2のレベル・アービタが、 読取りアクセス要求および書込みアクセス要求を含む高速データ・ポート・イ ンタフェースからの複数のアクセス要求と、読取り要求および書込み要求を含む 第1のレベル・アービタからのアクセス要求を受け取り、読取り許可信号、書込 み許可信号、メモリ制御信号をメモリ・コントローラに出力するように構成され た調停回路と、 高速データ・ポート・インタフェースおよび第1のレベル・アービタから情報 を受け取り、調停回路からの信号に応答して情報を出力するように構成された複 数のマルチプレクサとを含む請求項1に記載の装置。 8.複数のマルチプレクサが受け取った情報は、データ情報、アドレス情報、お よびタグ情報を含み、複数のマルチプレクサが調停回路によってアクセス要求が 許可されているポートに関連する情報を出力する請求項7に記載の装置。 9.第2のレベル・アービタがさらに、読取りアドレスおよび書込みアドレスを 受け取り、調停回路からの信号に応答して読取りアドレスまたは書込みアドレス を出力するように構成されたアドレス・マルチプレクサを含む請求項8に記載の 装置。 10.第2のレベル・アービタがさらに、メモリに書き込まれるべきデータおよ びタグ情報を格納するように構成されたパイプライン・レジスタを含む請求項9 に記載の装置。 11.低速データ・ポートがデータを100Mbpsのレートで送り、高速デー タ・ポートが低速データ・ポートの10倍のレートでデータを送る請求項1に記 載の装置。 12.異なるデータ・レートで動作するネットワーク・クライアントによるネッ トワーク内の共用資源へのアクセスを制御するための方法であって、 第1のデータ・レートで動作するように構成された少なくとも1つの低速クラ イアントからのアクセス要求を受け取るステップと、 第2のデータ・レートで動作するように構成された少なくとも1つの高速クラ イアントからのアクセス要求を受け取るステップと、 低速クライアントのアクセス要求を選択するために低速クライアントのアクセ ス要求を調停するステップと、 共用資源によって処理されるべきアクセス要求を選択するために高速クライア ントのアクセス要求と低速クライアントのアクセス要求の間を調停するステップ と を含む方法。 13.低速クライアントからのアクセス要求を受け取るステップが、 低速書込みアクセス要求を受け取るステップと、 低速書込みアクセス要求に関連するコマンド・ビット、書込みデータ、および 書込みアドレスを受け取るステップとを含む請求項12に記載の方法。 14.低速書込みアクセスが許可された時、書込みデータおよび書込みアドレス を格納するために低速クライアントの間で共用された格納位置の領域を、コマン ド・ビットを使用して識別するステップをさらに含む請求項13に記載の方法。 15.高速クライアントからのアクセス要求を受け取るステップが、 高速書込みアクセス要求を受け取るステップと、 高速書込みアクセス要求に関連するコマンド・ビット、書込みデータ、および 書込みアドレスを受け取るステップとを含む請求項14に記載の方法。 16.高速アクセス要求が許可された時、コマンド・ビットを使用して、書込み データおよび書込みアドレスを高速クライアントに関連する格納領域内でアセン ブルするステップと、 アセンブルされた書込みデータおよび書込みアドレスを共用資源に書込むステ ップとをさらに含む請求項15に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/884,764 US6119196A (en) | 1997-06-30 | 1997-06-30 | System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates |
US08/884,764 | 1997-06-30 | ||
PCT/US1998/013015 WO1999000736A1 (en) | 1997-06-30 | 1998-06-23 | Method and apparatus for arbitrating access to a shared memory by network ports operating at different data rates |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2002508099A true JP2002508099A (ja) | 2002-03-12 |
JP4024875B2 JP4024875B2 (ja) | 2007-12-19 |
Family
ID=25385338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50565599A Expired - Lifetime JP4024875B2 (ja) | 1997-06-30 | 1998-06-23 | 異なるデータ・レートで動作するネットワーク・ポートに関して、共用メモリへのアクセスを調停する方法および装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6119196A (ja) |
EP (1) | EP0991999B1 (ja) |
JP (1) | JP4024875B2 (ja) |
AT (1) | ATE528888T1 (ja) |
WO (1) | WO1999000736A1 (ja) |
Cited By (5)
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JP2007026022A (ja) * | 2005-07-15 | 2007-02-01 | Nec Electronics Corp | バス調停装置及びバス調停方法 |
WO2010086906A1 (ja) * | 2009-02-02 | 2010-08-05 | 富士通株式会社 | 調停装置 |
WO2010143386A1 (ja) * | 2009-06-08 | 2010-12-16 | パナソニック株式会社 | 調停装置、調停システム、調停方法、半導体集積回路、及び画像処理装置 |
JP2012014571A (ja) * | 2010-07-02 | 2012-01-19 | Fujitsu Ltd | アクセス制御装置、アクセス制御方法およびストレージシステム |
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JP5330513B2 (ja) * | 2009-06-08 | 2013-10-30 | パナソニック株式会社 | 調停装置、調停システム、調停方法、半導体集積回路、及び画像処理装置 |
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JP2012014571A (ja) * | 2010-07-02 | 2012-01-19 | Fujitsu Ltd | アクセス制御装置、アクセス制御方法およびストレージシステム |
US9547330B2 (en) | 2012-10-12 | 2017-01-17 | Socionext Inc. | Processor and control method for processor |
Also Published As
Publication number | Publication date |
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EP0991999A4 (en) | 2007-04-25 |
EP0991999A1 (en) | 2000-04-12 |
JP4024875B2 (ja) | 2007-12-19 |
US6119196A (en) | 2000-09-12 |
WO1999000736A1 (en) | 1999-01-07 |
EP0991999B1 (en) | 2011-10-12 |
ATE528888T1 (de) | 2011-10-15 |
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