JP2002353375A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JP2002353375A JP2002353375A JP2001157696A JP2001157696A JP2002353375A JP 2002353375 A JP2002353375 A JP 2002353375A JP 2001157696 A JP2001157696 A JP 2001157696A JP 2001157696 A JP2001157696 A JP 2001157696A JP 2002353375 A JP2002353375 A JP 2002353375A
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- copper
- layer
- wiring
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
Landscapes
- Chemically Coating (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子を収容
するための半導体素子収納用パッケージや混成集積回路
基板等に用いられる配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a package for housing a semiconductor element for housing a semiconductor element or a hybrid integrated circuit board.
【０００２】[0002]
【従来の技術】従来、半導体素子収納用パッケージや混
成集積回路基板等に用いられる配線基板は、一般に、酸
化アルミニウム質焼結体や窒化アルミニウム質焼結体等
の電気絶縁材料から成る絶縁基体と、該絶縁基体の表面
および内部に被着されたタングステン、モリブデン、マ
ンガン等の金属材料から成る配線層とにより形成されて
おり、絶縁基体の表面に半導体素子や容量素子、抵抗器
等の電子部品を搭載するとともに該電子部品の各電極を
配線層に錫−鉛半田、錫−銀系半田等の低融点ロウ材を
介して電気的に接続するようになっている。2. Description of the Related Art Conventionally, a wiring board used for a package for accommodating a semiconductor element or a hybrid integrated circuit board generally includes an insulating base made of an electrically insulating material such as an aluminum oxide sintered body or an aluminum nitride sintered body. And a wiring layer made of a metal material such as tungsten, molybdenum, or manganese adhered to the surface and inside of the insulating base, and electronic components such as semiconductor elements, capacitance elements, and resistors are formed on the surface of the insulating base. And the respective electrodes of the electronic component are electrically connected to the wiring layer via a low melting point brazing material such as tin-lead solder or tin-silver solder.
【０００３】かかる配線基板は、配線層の所定部位を外
部電気回路基板の配線導体に錫−鉛半田、錫−銀系半田
等の低融点ロウ材を介し接続することによって外部電気
回路基板上に実装され、同時に配線基板に搭載されてい
る電子部品の各電極も所定の外部電気回路に電気的に接
続されることとなる。In such a wiring board, a predetermined portion of the wiring layer is connected to a wiring conductor of the external electric circuit board via a low-melting-point brazing material such as tin-lead solder or tin-silver solder, so that the wiring layer is formed on the external electric circuit board. Each electrode of the electronic component mounted and simultaneously mounted on the wiring board is also electrically connected to a predetermined external electric circuit.
【０００４】また前記配線基板は、通常、配線層の露出
表面に銅めっき層および金めっき層が順次被着されてお
り、該銅めっき層によって配線層の電気抵抗を低く、か
つ配線層に対する低融点ロウ材の接合を良好としてお
り、また金めっき層によって配線層及び銅めっき層の酸
化腐食を有効に防止している。In the wiring board, a copper plating layer and a gold plating layer are usually sequentially deposited on the exposed surface of the wiring layer. The copper plating layer lowers the electric resistance of the wiring layer and lowers the electric resistance of the wiring layer. The joining of the melting point brazing material is good, and the oxidative corrosion of the wiring layer and the copper plating layer is effectively prevented by the gold plating layer.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の配線基板においては、銅めっき層を形成している銅
の結晶粒の平均粒径が一般に約１μｍであり、タングス
テン、モリブデン、マンガン等の金属材料から成る配線
層表面の凹凸径（凹部：約１μｍ）に比べて大きい。そ
のため配線層表面に銅めっき層を被着させても銅めっき
層は配線層表面の凹部内に十分入り込まずに配線層表面
と銅めっき層との間に多数の空隙部が形成されてしま
い、その結果、銅めっき層と配線層との密着強度が弱く
なり、外力印加によって銅めっき層が配線層より容易に
剥離したり、配線層表面と銅めっき層との間の空隙部に
入り込んでいる気体が配線層に電子部品の電極を低融点
ロウ材を介して接続する際等の熱によって大きく膨張
し、銅めっき層にフクレ等が発生してしまうという欠点
があった。However, in the above-mentioned conventional wiring board, the average crystal grain size of the copper crystal grains forming the copper plating layer is generally about 1 μm, and metal such as tungsten, molybdenum, manganese or the like is used. It is larger than the unevenness diameter (recess: about 1 μm) of the surface of the wiring layer made of the material. Therefore, even when the copper plating layer is applied to the wiring layer surface, the copper plating layer does not sufficiently enter the recesses on the wiring layer surface, and a large number of voids are formed between the wiring layer surface and the copper plating layer, As a result, the adhesion strength between the copper plating layer and the wiring layer is weakened, and the copper plating layer is easily peeled off from the wiring layer by the application of an external force, or enters the gap between the wiring layer surface and the copper plating layer. There is a drawback that the gas expands greatly due to heat when the electrode of the electronic component is connected to the wiring layer via the low melting point brazing material, and blisters and the like are generated in the copper plating layer.
【０００６】また、前記配線層に、電子部品の電極を低
融点ロウ材を介して接合する際の熱等が作用すると、銅
めっき層の銅が金めっき層の表面に移動拡散して銅の酸
化物層を形成していまい、配線層に対する低融点ロウ材
の濡れ性が劣化したり、接触電気抵抗が著しく増大して
しまったりするという問題もあった。When heat or the like is applied to the electrodes of the electronic component via the low melting point brazing material on the wiring layer, copper in the copper plating layer moves and diffuses to the surface of the gold plating layer to form a copper layer. When the oxide layer is formed, there are problems that the wettability of the low melting point brazing material to the wiring layer is deteriorated and the contact electric resistance is significantly increased.
【０００７】本発明は上記従来の欠点に鑑み案出された
もので、その目的は配線層と銅めっき層との間に剥離が
発生したり銅めっき層にフクレ等が生じるのを有効に防
止し、配線層に銅めっき層及び金めっき層を強固に被着
させることによって配線層に電子部品の電極を低融点ロ
ウ材を介して強固に取着接続することができる配線基板
を提供することにある。The present invention has been devised in view of the above-mentioned conventional drawbacks, and has as its object to effectively prevent the occurrence of peeling between the wiring layer and the copper plating layer and the occurrence of blisters or the like in the copper plating layer. And a wiring board capable of firmly attaching and connecting electrodes of an electronic component to the wiring layer via a low melting point brazing material by firmly applying a copper plating layer and a gold plating layer to the wiring layer. It is in.
【０００８】[0008]
【課題を解決するための手段】本発明の配線基板は、絶
縁基体に電子部品の電極が低融点ロウ材を介して接続さ
れる配線層を被着形成して成る配線基板であって、前記
配線層のうち少なくとも電子部品の電極が低融点ロウ材
を介して接合される領域の表面に、リンの含有量が０．
８重量％以上の銅−リンめっき層と、銅めっき層と、パ
ラジウム、白金、ロジウム、ルテニウムの少なくとも１
種とホウ素との合金層と、金めっき層とを順次被着させ
たことを特徴とするものである。A wiring board according to the present invention is a wiring board comprising an insulating substrate and a wiring layer formed by connecting electrodes of an electronic component through a low melting point brazing material. In the wiring layer, at least the surface of the region where the electrode of the electronic component is joined via the low melting point brazing material has a phosphorus content of 0.1%.
8% by weight or more of a copper-phosphorus plating layer, a copper plating layer, and at least one of palladium, platinum, rhodium, and ruthenium.
The method is characterized in that an alloy layer of a seed and boron and a gold plating layer are sequentially applied.
【０００９】また本発明の配線基板は、前記銅−リンめ
っき層の厚みが０．０３μｍ以上であることを特徴とす
るものである。In the wiring board according to the present invention, the thickness of the copper-phosphorus plating layer is 0.03 μm or more.
【００１０】また本発明の配線基板は、前記銅−リンめ
っき層を形成する銅の結晶粒の平均粒径が０．０２μｍ
以下であることを特徴とするものである。Further, in the wiring board according to the present invention, the copper crystal grains forming the copper-phosphorus plating layer have an average grain size of 0.02 μm.
It is characterized by the following.
【００１１】また本発明の配線基板は、前記パラジウ
ム、白金、ロジウム、ルテニウムの少なくとも１種とホ
ウ素との合金層のホウ素含有率が０．２重量％〜２重量
％の範囲であることを特徴とするものである。Further, in the wiring board of the present invention, the boron content of the alloy layer of boron and at least one of palladium, platinum, rhodium and ruthenium is in the range of 0.2% by weight to 2% by weight. It is assumed that.
【００１２】本発明の配線基板によれば、少なくとも電
子部品の電極が低融点ロウ材を介して接続される配線層
の表面に、リンの含有量が０．８重量％以上で銅−リン
の結晶粒径が０．３μｍ未満と小さい銅−リンめっき層
を被着させたことから配線層の表面に多数の凹凸があっ
たとしても、この凹部内に銅−リンの結晶が良好に入り
込んで配線層と銅−リンめっき層とが間に空隙部を形成
することなく強固に被着し、また銅−リンめっき層上
に、各々の密着性が良好な銅めっき層と、パラジウム、
白金、ロジウム、ルテニウムの少なくとも１種とホウ素
との合金層と、金めっき層とを順次被着させたことから
配線層に銅めっき層および金めっき層を強固に被着させ
ることができるとともに前記銅めっき層によって配線層
の電気抵抗を小さなものとなすことができ、更に金めっ
き層によって配線層の酸化腐食を有効に防止しつつ配線
層に電子部品の電極を低融点ロウ材を介して確実、強固
に電気的接続することができる。According to the wiring board of the present invention, at least the surface of the wiring layer to which the electrodes of the electronic parts are connected via the low melting point brazing material has a phosphorus content of 0.8% by weight or more and copper-phosphorus. Since a copper-phosphorous plating layer having a crystal grain size of less than 0.3 μm was deposited, even if there were a large number of irregularities on the surface of the wiring layer, crystals of copper-phosphorus could well enter these concave portions. The wiring layer and the copper-phosphorous plating layer are firmly adhered without forming a gap therebetween, and the copper-phosphorous plating layer has a good adhesion to each of the copper plating layers and the palladium,
Since an alloy layer of at least one of platinum, rhodium and ruthenium and boron and a gold plating layer are sequentially deposited, the copper plating layer and the gold plating layer can be firmly deposited on the wiring layer, and The electric resistance of the wiring layer can be reduced by the copper plating layer, and the electrodes of the electronic components can be securely connected to the wiring layer via the low melting point brazing material while effectively preventing the oxidation corrosion of the wiring layer by the gold plating layer. , Can be firmly connected.
【００１３】また同時に、前記銅めっき層と金めっき層
との間に形成した銅の拡散を有効に阻止するパラジウ
ム、白金、ロジウム、ルテニウムの少なくとも１種とホ
ウ素との合金層を形成したことから銅めっき層の銅の金
めっき層表面への拡散が効果的に防止され、配線層に電
子部品の電極を低融点ロウ材を介して接合する際の熱等
が作用したとしても金めっき層の表面に銅の酸化物層が
形成されることはほとんどなく、配線層に対する低融点
ロウ材の接合性を良好に維持することができる。At the same time, an alloy layer of boron and at least one of palladium, platinum, rhodium and ruthenium, which effectively prevents the diffusion of copper formed between the copper plating layer and the gold plating layer, is formed. The diffusion of the copper of the copper plating layer to the surface of the gold plating layer is effectively prevented, and even if heat or the like when the electrodes of the electronic component are joined to the wiring layer via the low melting point brazing material acts on the gold plating layer. A copper oxide layer is scarcely formed on the surface, and good bonding of the low melting point brazing material to the wiring layer can be maintained.
【００１４】[0014]
【発明の実施の形態】次に本発明を添付図面に基づいて
詳細に説明する。図１は、本発明の配線基板を半導体素
子収納用パッケージに適用した場合の一実施例を示す断
面図であり、１は絶縁基体、２は配線層である。この絶
縁基体１と配線層２とで半導体素子３を搭載するための
配線基板４が構成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing one embodiment in which the wiring board of the present invention is applied to a package for housing a semiconductor element, wherein 1 is an insulating base, and 2 is a wiring layer. The insulating substrate 1 and the wiring layer 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.
【００１５】前記絶縁基体１は、酸化アルミニウム質焼
結体、ムライト質焼結体、窒化アルミニウム質焼結体、
炭化珪素質焼結体、ガラスセラミック焼結体等の電気絶
縁材料から成り、その上面に半導体素子３を搭載する搭
載部を有し、該搭載部表面に露出した配線層２に半導体
素子３の電極が半田等の低融点ロウ材からなる接続部材
５を介して接続される。The insulating substrate 1 is made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body, and has a mounting portion for mounting the semiconductor element 3 on the upper surface thereof. The electrodes are connected via a connecting member 5 made of a low melting point brazing material such as solder.
【００１６】前記絶縁基体１は、例えば、酸化アルミニ
ウム質焼結体から成る場合には、酸化アルミニウム、酸
化珪素、酸化カルシウム、酸化マグネシウム等の原料粉
末に適当な有機バインダー、溶剤を添加混合して泥漿状
のセラミックスラリーとなすとともに該セラミックスラ
リーを従来周知のドクターブレード法やカレンダーロー
ル法等のシート成形技術を採用してシート状のセラミッ
クグリーンシート（セラミック生シート）を得、しかる
後、前記セラミックグリーンシートに切断加工や打ち抜
き加工等を施して適当な形状とするとともにこれを複数
枚積層し、最後に前記積層されたセラミックグリーンシ
ートを還元雰囲気中、約１６００℃の温度で焼成するこ
とによって製作される。When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder and a solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. The slurry is formed into a slurry-like ceramic slurry, and the ceramic slurry is formed into a sheet-like ceramic green sheet (ceramic green sheet) by using a sheet forming technique such as a doctor blade method or a calender roll method, which is well known in the art. The green sheet is cut and punched to obtain an appropriate shape, and a plurality of the green sheets are laminated. Finally, the laminated ceramic green sheets are fired at a temperature of about 1600 ° C. in a reducing atmosphere. Is done.
【００１７】また前記絶縁基体１は、その上面の搭載部
から下面にかけて多数の配線層２が被着形成されてお
り、該配線層２の搭載部に露出した部位には半導体素子
３の各電極が錫−鉛半田等の低融点ロウ材から成る接続
部材５を介して電気的に接続され、また絶縁基体１の下
面に導出された部位には外部電気回路基板の配線導体が
半田等の低融点ロウ材を介して電気的に接続される。The insulating substrate 1 has a large number of wiring layers 2 formed thereon from the mounting portion on the upper surface to the lower surface thereof. Each electrode of the semiconductor element 3 is exposed at the portion exposed on the mounting portion of the wiring layer 2. Are electrically connected via a connection member 5 made of a low melting point brazing material such as tin-lead solder, and a wiring conductor of an external electric circuit board is provided at a portion led out to the lower surface of the insulating base 1. It is electrically connected via the melting point brazing material.
【００１８】前記配線層２は、接続される半導体素子３
の電極を外部電気回路に接続する作用をなし、例えば、
タングステンやモリブデン、モリブデン／マンガン、タ
ングステン／銅、モリブデン／銅、タングステン／モリ
ブデン／銅、等のタングステン、モリブデン、マンガン
の少なくとも１種を主成分とする金属材料により形成さ
れている。The wiring layer 2 includes a semiconductor element 3 to be connected.
Acts to connect the electrodes of the external electrical circuit, for example,
It is formed of a metal material containing at least one of tungsten, molybdenum, and manganese, such as tungsten, molybdenum, molybdenum / manganese, tungsten / copper, molybdenum / copper, and tungsten / molybdenum / copper.
【００１９】前記配線層２は、タングステン等の金属粉
末に適当な有機バインダーや溶剤を添加混合して得た金
属ペーストを絶縁基体１となるセラミックグリーンシー
トに予め従来周知のスクリーン印刷法により所定パター
ンに印刷塗布しておくことによって、絶縁基体１の所定
位置に被着形成される。The wiring layer 2 is formed by applying a metal paste obtained by adding a suitable organic binder or solvent to a metal powder such as tungsten or the like to a ceramic green sheet serving as the insulating substrate 1 in a predetermined pattern by a conventionally known screen printing method. Is applied to a predetermined position of the insulating substrate 1.
【００２０】前記配線層２は、図２に示す如く、少なく
とも半導体素子３の電極が低融点ロウ材から成る接続部
材５を介して接続される領域に銅−リンめっき層６、銅
めっき層７、パラジウム、白金、ロジウム、ルテニウム
の少なくとも１種とホウ素との合金層８、金めっき層９
が順次被着されている。As shown in FIG. 2, the wiring layer 2 has a copper-phosphorous plating layer 6 and a copper plating layer 7 at least in regions where electrodes of the semiconductor element 3 are connected via a connecting member 5 made of a low melting point brazing material. Alloy layer 8 of at least one of palladium, platinum, rhodium, ruthenium and boron, gold plating layer 9
Are sequentially applied.
【００２１】前記銅−リンめっき層６は、配線層２に銅
めっき層７、パラジウム、白金、ロジウム、ルテニウム
の少なくとも１種とホウ素との合金層８、金めっき層９
を密着性良く被着させる下地金属層として作用する。The copper-phosphorous plating layer 6 comprises a copper plating layer 7, an alloy layer 8 of boron and at least one of palladium, platinum, rhodium and ruthenium, and a gold plating layer 9 on the wiring layer 2.
Acts as a base metal layer to adhere with good adhesion.
【００２２】前記銅−リンめっき層６は、例えば、配線
層２の表面にパラジウム活性を施した後、この配線層２
を、次亜リン酸塩等のリン系化合物を還元剤として用い
たリン系無電解銅めっき液中に所定時間浸漬することに
よって配線層２の表面に所定厚みに被着される。この場
合、前記銅−リンめっき層６は被着時に共析して含有さ
れるリン成分の作用により結晶粒の粒成長が効果的に抑
制されて銅―リンの結晶粒の平均粒径は、例えば、０．
３μｍ以下の小さなものとなり、その結果、配線層２の
表面に多数の凹凸があったとしても、この凹部内に銅−
リンの結晶が良好に入り込んで配線層２と銅−リンめっ
き層６とは間に空隙部を形成することなく強固に密着さ
せることができる。The copper-phosphorous plating layer 6 is formed, for example, by activating palladium on the surface of the wiring layer 2,
Is immersed in a phosphorus-based electroless copper plating solution using a phosphorus-based compound such as hypophosphite as a reducing agent for a predetermined time, thereby to be adhered to the surface of the wiring layer 2 to a predetermined thickness. In this case, the copper-phosphorus plating layer 6 is eutectoidally deposited, and the growth of crystal grains is effectively suppressed by the action of the phosphorus component contained therein. For example, 0.
As a result, even if there are many irregularities on the surface of the wiring layer 2, copper-
Phosphorus crystal can enter well and the wiring layer 2 and the copper-phosphorus plating layer 6 can be firmly adhered to each other without forming a gap between them.
【００２３】なお、前記銅−リンめっき層６は、銅−リ
ンの結晶粒の平均粒径を０．３μｍ以下の小さなものと
するにはリンの含有量を０．８重量％以上としておく必
要があり、リンの含有量を０．８重量％以上としておく
ことによって銅−リンの結晶粒の粒径は０．３μｍ以下
となり、配線層２の表面に凹凸を有するとしても凹部内
に良好に入り込んで配線層２に強固に被着する。The copper-phosphorus plating layer 6 must have a phosphorus content of 0.8% by weight or more in order to reduce the average particle size of the copper-phosphorus crystal grains to 0.3 μm or less. By setting the phosphorus content to 0.8% by weight or more, the particle size of the copper-phosphorus crystal grains becomes 0.3 μm or less, and even if the surface of the wiring layer 2 has irregularities, It penetrates and is firmly adhered to the wiring layer 2.
【００２４】また前記銅−リンめっき層６は、銅−リン
の結晶粒の平均粒径を０．０２μｍ以下としておくと銅
−リンめっき層６を表面に凹凸を有する配線層２により
一層強固に被着させることができる。従って、前記銅−
リンめっき層６は、銅−リンの結晶粒の平均粒径を０．
０２μｍ以下としておくことが好ましく、より好適には
０．０１μｍ以下としておくのがよい。When the copper-phosphorus plating layer 6 has an average grain size of 0.02 μm or less, the copper-phosphorus plating layer 6 can be more firmly formed by the wiring layer 2 having an uneven surface. Can be applied. Therefore, the copper
The phosphorus plating layer 6 has an average grain size of copper-phosphorus crystal grains of 0.1.
It is preferable to set the thickness to 02 μm or less, and more preferable to set it to 0.01 μm or less.
【００２５】前記銅−リンめっき層６の平均粒径を０．
０１μｍ以下とするには、銅−リンめっき層６中のリン
含有率を１．３重量％程度以上とすることによって、ま
た０．０２μｍ以下とするには、銅−リンめっき層６中
のリン含有率を１重量％程度以上とすることによって行
なわれ、電気伝導性等の特性を考慮すれば１重量％〜１
０重量％の範囲とすることが好ましい。The average particle size of the copper-phosphorus plating layer 6 is set to 0.1.
In order to adjust the phosphorus content in the copper-phosphorous plating layer 6 to be not more than 0.01 μm, the phosphorus content in the copper-phosphorous plating layer 6 should be about 1.3% by weight or more. The content is adjusted to about 1% by weight or more, and considering the properties such as electric conductivity, 1% by weight to 1% by weight.
It is preferred to be in the range of 0% by weight.
【００２６】更に前記銅−リンめっき層６は、その厚み
が０．０３μｍ未満の薄いものとなると配線層２の表面
全体を完全に覆うことが難しく、後述する銅めっき層
７、パラジウム、白金、ロジウム、ルテニウムの少なく
とも１種とホウ素との合金層８、および金めっき層９を
配線層２に強固に被着させるのが困難となる傾向にあ
る。従って、前記銅−リンめっき層６は、その厚みを
０．０３μｍ以上としておくことが好ましい。Further, when the copper-phosphorous plating layer 6 has a thickness of less than 0.03 μm, it is difficult to completely cover the entire surface of the wiring layer 2, and the copper plating layer 7, palladium, platinum, It tends to be difficult to firmly adhere the alloy layer 8 of at least one of rhodium and ruthenium to boron and the gold plating layer 9 to the wiring layer 2. Therefore, it is preferable that the thickness of the copper-phosphorus plating layer 6 be 0.03 μm or more.
【００２７】また更に、前記銅−リンめっき層６の表面
には該銅−リンめっき層６と後述するパラジウム、白
金、ロジウム、ルテニウムの少なくとも１種とホウ素と
の合金層８とのいずれに対して密着性が優れた銅めっき
層７が被着形成されている。Further, the surface of the copper-phosphorous plating layer 6 is formed on any one of the copper-phosphorous plating layer 6 and an alloy layer 8 of boron and at least one of palladium, platinum, rhodium and ruthenium described later. Thus, a copper plating layer 7 having excellent adhesion is adhered and formed.
【００２８】前記銅めっき層７は、配線層２にパラジウ
ム、白金、ロジウム、ルテニウムの少なくとも１種とホ
ウ素との合金層８を強固に被着させ、かつ配線層２に対
し半田等の低融点ロウ材を強固に被着させるとともに配
線層２の電気抵抗を下げる作用をなす。The copper plating layer 7 has a structure in which an alloy layer 8 of boron and at least one of palladium, platinum, rhodium and ruthenium is firmly adhered to the wiring layer 2 and has a low melting point such as solder on the wiring layer 2. It functions to firmly adhere the brazing material and lower the electric resistance of the wiring layer 2.
【００２９】前記銅めっき層７は、例えば、銅−リンめ
っき層６を被着させた配線層２を、ホルマリンを還元剤
として用いた無電解銅めっき液中に所定時間浸漬するこ
とによって銅−リンめっき層６の表面に所定厚みに被着
形成される。この場合、ホルマリンを還元剤として用い
た無電解銅めっき液を用いると、このめっき液が自己触
媒作用を有するため銅−リンめっき層６表面に活性処理
を施すことなく、銅めっき層７を所定厚みに、かつ銅−
リンめっき層６に対して接合強度を大として被着させる
ことが可能となる。The copper plating layer 7 is formed, for example, by immersing the wiring layer 2 on which the copper-phosphorus plating layer 6 is applied in an electroless copper plating solution using formalin as a reducing agent for a predetermined time. A predetermined thickness is formed on the surface of the phosphor plating layer 6. In this case, when an electroless copper plating solution using formalin as a reducing agent is used, the plating solution has a self-catalytic action, so that the copper-phosphorous plating layer 6 can be subjected to a predetermined treatment without performing an activation treatment on the surface thereof. Thick and copper-
It becomes possible to adhere to the phosphorus plating layer 6 with a high bonding strength.
【００３０】なお、前記銅めっき層７は、共析成分を含
有しないホルマリン等を用いて形成され高純度であるこ
とから配線層２の半田等の低融点ロウ材に対する接合性
が大きく改善されるとともに電気抵抗が極めて小さい値
となり、配線層２を伝搬する電気信号等に減衰が発生す
るのを有効に防止することが可能となる。Since the copper plating layer 7 is formed using formalin or the like which does not contain an eutectoid component and has a high purity, the bonding property of the wiring layer 2 to a low melting point brazing material such as solder is greatly improved. At the same time, the electric resistance becomes an extremely small value, so that it is possible to effectively prevent the occurrence of attenuation in electric signals and the like propagating through the wiring layer 2.
【００３１】また、前記銅めっき層７はその表面に、該
銅めっき層７と、後述する金めっき層９のいずれに対し
ても密着性が優れた、パラジウム、白金、ロジウム、ル
テニウムの少なくとも１種とホウ素との合金層８が被着
形成されている。The copper plating layer 7 has on its surface at least one of palladium, platinum, rhodium and ruthenium, which has excellent adhesion to both the copper plating layer 7 and a gold plating layer 9 described later. An alloy layer 8 of seed and boron is deposited.
【００３２】前記パラジウム、白金、ロジウム、ルテニ
ウムの少なくとも１種とホウ素との合金層８は、錫−鉛
半田等の低融点ロウ材を介して半導体素子３の電極を配
線層２に接続する際に作用する熱により銅めっき層７の
銅が後述する金めっき層９の表面に移動拡散することを
阻止する作用をなす。The alloy layer 8 of boron and at least one of palladium, platinum, rhodium and ruthenium is used for connecting the electrode of the semiconductor element 3 to the wiring layer 2 via a low melting point brazing material such as tin-lead solder. Acts to prevent the copper of the copper plating layer 7 from moving and diffusing to the surface of the gold plating layer 9 described later.
【００３３】前記パラジウム、白金、ロジウム、ルテニ
ウムの少なくとも１種とホウ素との合金層８は、塩化パ
ラジウム等の、パラジウム、白金、ロジウム、ルテニウ
ムの少なくとも１種の供給源となる化合物と、ジメチル
アミンボラン、トリメチルアミンボラン等のホウ素系還
元剤とを主成分とする無電解めっき液中に配線層２の露
出表面（銅めっき層７が被着）所定時間浸漬することに
より、所定厚みに被着形成することができる。The alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and boron is composed of a compound serving as a supply source of at least one of palladium, platinum, rhodium and ruthenium, such as palladium chloride, and dimethylamine. The exposed surface of the wiring layer 2 (the copper plating layer 7 is adhered) is immersed for a predetermined time in an electroless plating solution containing a boron-based reducing agent such as borane and trimethylamine borane as a main component, thereby forming a deposition to a predetermined thickness. can do.
【００３４】なお、前記銅めっき層７上にパラジウム−
ホウ素合金層８を被着形成した場合、含有するホウ素成
分の作用により銅の移動拡散を極めて効果的に阻止する
ことができ、例えば、後述する金めっき層９の厚みを
０．０５μｍ未満と極めて薄いものとした場合や、錫−
銀系半田等のいわゆる鉛フリー半田を用いて比較的高温
でロウ付けした場合でも、銅めっき層７の銅が金めっき
層９の表面に移動して酸化物層を作ることはなく、配線
層２に対する低融点ロウ材の接合性や接触抵抗を良好に
維持することができる。It should be noted that palladium-free
When the boron alloy layer 8 is formed by deposition, the movement and diffusion of copper can be extremely effectively prevented by the action of the boron component contained therein. For example, the thickness of the gold plating layer 9 described below is extremely small, less than 0.05 μm. When thinner or tin-
Even when brazing is performed at a relatively high temperature using a so-called lead-free solder such as silver-based solder, the copper of the copper plating layer 7 does not move to the surface of the gold plating layer 9 to form an oxide layer. 2 can maintain good bondability and contact resistance of the low melting point brazing material.
【００３５】また、前記パラジウム、白金、ロジウム、
ルテニウムの少なくとも１種とホウ素との合金層８のホ
ウ素含有量が０．２重量％未満となると、錫−銀系半田
等の比較的高温でロウ付けする低融点ロウ材を使用する
場合、銅めっき層７の銅が金めっき層９に移動拡散する
のを有効に阻止することが困難となる傾向にあり、また
２重量％を超えると触媒不活性なホウ素成分が増大して
めっき法による形成速度が遅くなり、量産性が低いもの
となって実用性が損なわれてしまったり、内部応力が増
大してクラック等を生じ易くなったりする傾向がある。
従って、前記パラジウム、白金、ロジウム、ルテニウム
の少なくとも１種とホウ素との合金層８は、ホウ素の含
有量を０．２重量％〜２重量％の範囲としておくことが
好ましい。The palladium, platinum, rhodium,
When the boron content of the alloy layer 8 of at least one kind of ruthenium and boron is less than 0.2% by weight, when a low melting point brazing material such as a tin-silver solder, which is brazed at a relatively high temperature, is used. There is a tendency that it is difficult to effectively prevent the copper of the plating layer 7 from moving and diffusing into the gold plating layer 9, and if it exceeds 2% by weight, the catalytically inactive boron component increases and the formation by the plating method occurs. There is a tendency that the speed becomes slow, mass productivity is low and practicality is impaired, and internal stress increases and cracks and the like are liable to occur.
Therefore, it is preferable that the alloy layer 8 of boron and at least one of palladium, platinum, rhodium and ruthenium has a boron content in the range of 0.2% by weight to 2% by weight.
【００３６】更に、前記パラジウム、白金、ロジウム、
ルテニウムの少なくとも１種とホウ素との合金層８は、
その厚みが０．０５μｍ未満となると銅めっき層７の銅
が金めっき層９の表面に移動拡散するのを阻止すること
が困難となり、３μｍを超えると形成時に発生して残留
する内部応力が大きくなって銅めっき層７に対して強固
に被着することが困難となるおそれがある。従って、前
記パラジウム、白金、ロジウム、ルテニウムの少なくと
も１種とホウ素との合金層８は、その厚みを０．０５μ
ｍ〜３μｍの範囲とすることが好ましく、また後述する
金めっき層９の厚みを０．０５μｍ未満と非常に薄いも
のとする場合には、銅めっき層７の酸化腐食を防ぐため
に０．３μｍ以上の厚みとすることが好ましい。Further, the palladium, platinum, rhodium,
The alloy layer 8 of at least one kind of ruthenium and boron is
If the thickness is less than 0.05 μm, it is difficult to prevent the copper of the copper plating layer 7 from moving and diffusing to the surface of the gold plating layer 9. If the thickness exceeds 3 μm, the residual internal stress generated during the formation is large. This may make it difficult to firmly adhere to the copper plating layer 7. Accordingly, the alloy layer 8 of boron and at least one of palladium, platinum, rhodium and ruthenium has a thickness of 0.05 μm.
m to 3 μm, and when the thickness of the gold plating layer 9 described below is extremely thin, less than 0.05 μm, it is 0.3 μm or more in order to prevent oxidation corrosion of the copper plating layer 7. It is preferable that the thickness is
【００３７】また更に、前記パラジウム、白金、ロジウ
ム、ルテニウムの少なくとも１種とホウ素との合金層８
の表面には金めっき層９が被着形成されている。Further, an alloy layer 8 of at least one of palladium, platinum, rhodium and ruthenium and boron.
A gold plating layer 9 is formed on the surface of the substrate.
【００３８】前記金めっき層９は、配線層２、銅−リン
めっき層６および銅めっき層７の酸化腐食を防止すると
ともに、配線層２に対する低融点ロウ材の接合性を良好
なものとする作用をなす。The gold plating layer 9 prevents oxidative corrosion of the wiring layer 2, the copper-phosphorous plating layer 6 and the copper plating layer 7, and improves the bonding property of the low melting point brazing material to the wiring layer 2. Works.
【００３９】前記金めっき層９は、例えば、金化合物で
あるシアン化金カリウムおよび錯化剤であるエチレンジ
アミン四酢酸を主成分とする無電解金めっき液中に、前
記パラジウム、白金、ロジウム、ルテニウムの少なくと
も１種とホウ素との合金層８が被着されている配線層２
を所定時間浸漬させることによって前記金属層８の表面
に所定厚みに被着される。The gold plating layer 9 is formed, for example, by placing the above-mentioned palladium, platinum, rhodium, ruthenium in an electroless gold plating solution containing gold potassium cyanide as a gold compound and ethylenediaminetetraacetic acid as a complexing agent as main components. Layer 2 on which alloy layer 8 of at least one of the above and boron is adhered
Is deposited on the surface of the metal layer 8 to a predetermined thickness by immersing the metal layer for a predetermined time.
【００４０】更に前記金めっき層９は、その厚みが０．
８μｍを超えて厚くすると、半導体素子３の電極を配線
層２に半田等の低融点ロウ材からなる接続部材５を介し
て接続したとき、低融点ロウ材５の錫と金との間で脆い
金属間化合物が生成され、半導体素子３の配線層２に対
する接続の信頼性が大きく低下してしまう危険性があ
る。従って、前記金めっき層９は、その厚さを０．８μ
ｍ以下としておくことが好ましい。The gold plating layer 9 has a thickness of 0.1 mm.
When the thickness exceeds 8 μm, when the electrode of the semiconductor element 3 is connected to the wiring layer 2 via the connection member 5 made of a low melting point brazing material such as solder, the low melting point brazing material 5 becomes brittle between tin and gold. There is a risk that intermetallic compounds are generated and the reliability of connection of the semiconductor element 3 to the wiring layer 2 is greatly reduced. Therefore, the gold plating layer 9 has a thickness of 0.8 μm.
m or less.
【００４１】また一方、前記半導体素子３が搭載された
絶縁基体１は、その上面に蓋体１０が樹脂、ガラス、ロ
ウ材等からなる封止材を介して接合され、この蓋体１０
と絶縁基体１とによって半導体素子３を気密に封止する
ようになっている。On the other hand, the insulating substrate 1 on which the semiconductor element 3 is mounted has a lid 10 bonded to the upper surface thereof via a sealing material made of resin, glass, brazing material or the like.
The semiconductor element 3 is hermetically sealed with the insulating substrate 1 and the insulating base 1.
【００４２】前記蓋体１０は酸化アルミニウム質焼結体
やムライト質焼結体、窒化アルミニウム質焼結体等のセ
ラミックス材料、あるいは鉄−ニッケル−コバルト合金
や鉄−ニッケル合金等の金属材料から成り、例えば、酸
化アルミニウム質焼結体から成る場合には、酸化アルミ
ニウム、酸化珪素、酸化マグネシウム、酸化カルシウム
等の原料粉末を従来周知のプレス成形法を採用すること
によって椀状に成形するとともにこれを約１５００℃の
温度で焼成することによって形成される。The lid 10 is made of a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, or a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. For example, in the case of a sintered body made of aluminum oxide, a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide is formed into a bowl shape by employing a conventionally known press molding method, and then formed into a bowl shape. It is formed by firing at a temperature of about 1500 ° C.
【００４３】かくして上述の本発明の配線基板を適用し
た半導体素子収納用パッケージによれば、絶縁基体１上
面の搭載部表面に露出した配線層２に半導体素子３の電
極を半田等の低融点ロウ材から成る接続部材５を介して
電気的、機械的に接続し、しかる後、絶縁基体１の上面
に蓋体１０を樹脂やガラス、ロウ材等から成る封止材を
介して接合させ、絶縁基体１と蓋体１０とから成る容器
内部に半導体素子３を気密に収容することによって最終
製品としての半導体装置が完成する。Thus, according to the package for housing a semiconductor element to which the above-mentioned wiring board of the present invention is applied, the electrodes of the semiconductor element 3 are connected to the wiring layer 2 exposed on the surface of the mounting portion on the upper surface of the insulating base 1 by a low melting point solder such as solder. The cover 10 is electrically and mechanically connected via a connection member 5 made of a material, and then the lid 10 is joined to the upper surface of the insulating base 1 via a sealing material made of resin, glass, brazing material, or the like. The semiconductor device 3 as a final product is completed by hermetically housing the semiconductor element 3 in a container including the base 1 and the lid 10.
【００４４】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、本発明の配線基板
を、半導体素子、容量素子、抵抗器等の電子部品を搭載
する混成集積回路用の配線基板に適用してもよい。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. The present invention may be applied to a wiring board for a hybrid integrated circuit on which electronic components such as a capacitor and a resistor are mounted.
【００４５】[0045]
【発明の効果】本発明の配線基板によれば、少なくとも
電子部品の電極が低融点ロウ材を介して接続される配線
層の表面に、リンの含有量が０．８重量％以上で銅−リ
ンの結晶粒径が０．３μｍ未満と小さい銅−リンめっき
層を被着させたことから配線層の表面に多数の凹凸があ
ったとしても、この凹部内に銅−リンの結晶が良好に入
り込んで配線層と銅−リンめっき層とが間に空隙部を形
成することなく強固に被着し、また銅−リンめっき層上
に、各々の密着性が良好な銅めっき層と、パラジウム、
白金、ロジウム、ルテニウムの少なくとも１種とホウ素
との合金層と、金めっき層とを順次被着させたことから
配線層に銅めっき層および金めっき層を強固に被着させ
ることができるとともに前記銅めっき層によって配線層
の電気抵抗を小さなものとなすことができ、更に金めっ
き層によって配線層の酸化腐食を有効に防止しつつ配線
層に電子部品の電極を低融点ロウ材を介して確実、強固
に電気的接続することができる。According to the wiring board of the present invention, at least the surface of the wiring layer to which the electrodes of the electronic parts are connected via the low-melting brazing material has a phosphorus content of 0.8% by weight or more and a copper-containing material. Since the copper-phosphorus plating layer having a small crystal grain diameter of phosphorus of less than 0.3 μm was deposited, even if there were many irregularities on the surface of the wiring layer, the copper-phosphorus crystal was well formed in the concave portions. The wiring layer and the copper-phosphorus plating layer are firmly adhered without forming a gap between the wiring layer and the copper-phosphorus plating layer, and a copper plating layer having good adhesion, palladium,
Since an alloy layer of at least one of platinum, rhodium and ruthenium and boron and a gold plating layer are sequentially deposited, the copper plating layer and the gold plating layer can be firmly deposited on the wiring layer, and The electric resistance of the wiring layer can be reduced by the copper plating layer, and the electrodes of the electronic components can be securely connected to the wiring layer via the low melting point brazing material while effectively preventing the oxidation corrosion of the wiring layer by the gold plating layer. , Can be firmly connected.
【００４６】また同時に、前記銅めっき層と金めっき層
との間に銅の拡散を有効に阻止するパラジウム、白金、
ロジウム、ルテニウムの少なくとも１種とホウ素との合
金層を形成したことから銅めっき層の銅の金めっき層表
面への拡散が効果的に防止され、配線層に電子部品の電
極を低融点ロウ材を介して接合する際の熱等が作用した
としても金めっき層の表面に銅の酸化物層が形成される
ことはほとんどなく、配線層に対する低融点ロウ材の接
合性を良好に維持することができる。At the same time, palladium, platinum, which effectively prevents the diffusion of copper between the copper plating layer and the gold plating layer,
Since an alloy layer of at least one of rhodium and ruthenium and boron is formed, diffusion of copper of the copper plating layer to the surface of the gold plating layer is effectively prevented, and the electrode of the electronic component is formed on the wiring layer with a low melting point brazing material. A copper oxide layer is hardly formed on the surface of the gold plating layer even if heat or the like at the time of bonding through the joint acts, and the good bonding property of the low melting point brazing material to the wiring layer is maintained. Can be.
【図１】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment in which a wiring board of the present invention is applied to a package for housing a semiconductor element.
【図２】図１に示す配線基板の要部断面図である。FIG. 2 is a sectional view of a main part of the wiring board shown in FIG. 1;
１・・・・・絶縁基体 ２・・・・・配線層 ３・・・・・半導体素子 ４・・・・・配線基板 ５・・・・・接続部材 ６・・・・・銅−リンめっき層 ７・・・・・銅めっき層 ８・・・・・パラジウム、白金、ロジウム、ルテニウム
の少なくとも１種とホウ素との合金層 ９・・・・・金めっき層 １０・・・・蓋体1. Insulating substrate 2. Wiring layer 3. Semiconductor element 4. Wiring board 5. Connection member 6. Copper-phosphorous plating Layer 7 Copper plating layer 8 Alloy layer of at least one of palladium, platinum, rhodium, ruthenium and boron 9 Gold plating layer 10 Lid
Claims (4)
を介して接続される配線層を被着形成して成る配線基板
であって、前記配線層のうち少なくとも電子部品の電極
が低融点ロウ材を介して接合される領域の表面に、リン
の含有量が０．８重量％以上の銅−リンめっき層と、銅
めっき層と、パラジウム、白金、ロジウム、ルテニウム
の少なくとも１種とホウ素との合金層と、金めっき層と
を順次被着させたことを特徴とする配線基板。A wiring board comprising an insulating substrate and a wiring layer to which electrodes of an electronic component are connected via a low melting point brazing material, wherein at least the electrode of the electronic component is low in the wiring layer. A copper-phosphorus plating layer having a phosphorus content of 0.8% by weight or more, a copper plating layer, and at least one of palladium, platinum, rhodium, and ruthenium on a surface of a region to be joined via the melting point brazing material. A wiring board, wherein an alloy layer with boron and a gold plating layer are sequentially applied.
ｍ以上であることを特徴とする請求項１に記載の配線基
板。2. The copper-phosphorus plating layer has a thickness of 0.03 μm.
2. The wiring board according to claim 1, wherein m is not less than m.
粒の平均粒径が０．０２μｍ以下であることを特徴とす
る請求項１に記載の配線基板。3. The wiring board according to claim 1, wherein the average crystal grain size of the copper crystal grains forming the copper-phosphorous plating layer is 0.02 μm or less.
ウムの少なくとも１種とホウ素との合金層のホウ素含有
率が０．２重量％〜２重量％の範囲であることを特徴と
する請求項１に記載の配線基板。4. The method according to claim 1, wherein the boron content of the alloy layer of boron with at least one of palladium, platinum, rhodium and ruthenium is in the range of 0.2% by weight to 2% by weight. The wiring board as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001157696A JP4683768B2 (en) | 2001-05-25 | 2001-05-25 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001157696A JP4683768B2 (en) | 2001-05-25 | 2001-05-25 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002353375A true JP2002353375A (en) | 2002-12-06 |
| JP4683768B2 JP4683768B2 (en) | 2011-05-18 |
Family
ID=19001521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001157696A Expired - Fee Related JP4683768B2 (en) | 2001-05-25 | 2001-05-25 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4683768B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010140638A1 (en) * | 2009-06-05 | 2010-12-09 | 古河電気工業株式会社 | Metal-clad laminate and method for producing metal-clad laminate |
| JP2012111678A (en) * | 2010-06-30 | 2012-06-14 | Vectron Internatl Gmbh & Co Kg | Metal covering for cavity case, and non-magnetic closed cavity case |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267299A (en) * | 1992-03-19 | 1993-10-15 | Hitachi Ltd | Semiconductor device |
| JPH05327187A (en) * | 1992-05-18 | 1993-12-10 | Ishihara Chem Co Ltd | Printed circuit board and manufacture thereof |
| JP2001102733A (en) * | 1999-09-28 | 2001-04-13 | Kyocera Corp | Mounting method of electronic component |
-
2001
- 2001-05-25 JP JP2001157696A patent/JP4683768B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267299A (en) * | 1992-03-19 | 1993-10-15 | Hitachi Ltd | Semiconductor device |
| JPH05327187A (en) * | 1992-05-18 | 1993-12-10 | Ishihara Chem Co Ltd | Printed circuit board and manufacture thereof |
| JP2001102733A (en) * | 1999-09-28 | 2001-04-13 | Kyocera Corp | Mounting method of electronic component |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010140638A1 (en) * | 2009-06-05 | 2010-12-09 | 古河電気工業株式会社 | Metal-clad laminate and method for producing metal-clad laminate |
| JP2012111678A (en) * | 2010-06-30 | 2012-06-14 | Vectron Internatl Gmbh & Co Kg | Metal covering for cavity case, and non-magnetic closed cavity case |
| US9023442B2 (en) | 2010-06-30 | 2015-05-05 | Vectron International Gmbh | Metallization for a cavity housing and a nonmagnetic sealed cavity housing |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4683768B2 (en) | 2011-05-18 |
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