JP2002319704A - Led chip - Google Patents
Led chipInfo
- Publication number
- JP2002319704A JP2002319704A JP2001124555A JP2001124555A JP2002319704A JP 2002319704 A JP2002319704 A JP 2002319704A JP 2001124555 A JP2001124555 A JP 2001124555A JP 2001124555 A JP2001124555 A JP 2001124555A JP 2002319704 A JP2002319704 A JP 2002319704A
- Authority
- JP
- Japan
- Prior art keywords
- side electrode
- type semiconductor
- semiconductor layer
- led chip
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、基板上にｐ形半導
体層とｎ形半導体層とが形成され、ｐ形半導体層および
ｎ形半導体層における基板の反対側である主チップ面に
おいて、ｐ形半導体層およびｎ形半導体層にそれぞれｐ
側電極およびｎ側電極が接続されたＬＥＤチップに関す
るものである。The present invention relates to a p-type semiconductor layer and an n-type semiconductor layer formed on a substrate, and a p-type semiconductor layer and an n-type semiconductor layer having a p-type semiconductor layer on a main chip surface opposite to the substrate. P-type and n-type semiconductor layers, respectively.
The present invention relates to an LED chip to which a side electrode and an n-side electrode are connected.
【０００２】[0002]
【従来の技術】従来から、図２５に示すように、サファ
イアの基板２の上に導電形がｎ形である窒化ガリウムか
らなるｎ形半導体層３を介して、導電形がｐ形である窒
化ガリウムからなるｐ形半導体層５を積層した構造のＬ
ＥＤチップ１が提供されている。図示するＬＥＤチップ
１ではｎ形半導体層３に接続されるｎ側電極７とｐ形半
導体層５に接続されるｐ側電極６とを基板２の両側部に
配置してある。2. Description of the Related Art Conventionally, as shown in FIG. 25, a nitride of p-type conductivity is formed on a sapphire substrate 2 via an n-type semiconductor layer 3 of gallium nitride of n-type conductivity. L having a structure in which a p-type semiconductor layer 5 made of gallium is laminated
An ED chip 1 is provided. In the illustrated LED chip 1, an n-side electrode 7 connected to the n-type semiconductor layer 3 and a p-side electrode 6 connected to the p-type semiconductor layer 5 are arranged on both sides of the substrate 2.
【０００３】このように構成されたＬＥＤチップ２はｐ
側電極６およびｎ側電極７を設けている主チップ面を光
取出側とするフェースアップ状態で実装するときには、
ｐ側電極６とｎ側電極７とにそれぞれボンディングワイ
ヤを介して給電する形で使用する。[0003] The LED chip 2 thus configured is
When mounting in a face-up state in which the main chip surface on which the side electrode 6 and the n-side electrode 7 are provided is a light extraction side,
Power is supplied to the p-side electrode 6 and the n-side electrode 7 via bonding wires.
【０００４】また、基板２はサファイアからなり透光性
を有するから、図２６に示すように基板２を光取出側と
するフェースダウン状態での実装も可能であって、この
場合にはｐ側電極６およびｎ側電極７をバンプ構造とし
て実装基板８に設けた導電体１０にｐ側電極６およびｎ
側電極７を電気的に接続するようにフリップチップ実装
が施される。このような実装形式を採用するときにはＬ
ＥＤチップ１と実装基板８との間に充填材１１が充填さ
れる。Further, since the substrate 2 is made of sapphire and has translucency, it can be mounted in a face-down state with the substrate 2 as a light extraction side as shown in FIG. The electrode 6 and the n-side electrode 7 have a bump structure, and the p-side electrodes 6 and n
Flip chip mounting is performed so as to electrically connect the side electrodes 7. When such a mounting format is adopted, L
A filler 11 is filled between the ED chip 1 and the mounting board 8.
【０００５】[0005]
【発明が解決しようとする課題】ところで、上述した従
来構成のＬＥＤチップ１ではｐ側電極６とｎ側電極７と
が点状に１個ずつ設けられたものであり、ＬＥＤチップ
１の発光面（光取出面）においてｐ側電極６とｎ側電極
７との間では輝度が高いものの、それ以外の部位では輝
度が低いという観察結果が得られている。これは、ｐ側
電極６とｎ側電極７との間では電流密度が十分に大きい
がｐ側電極６とｎ側電極７との間から離れると電流密度
が急速に小さくなり、電流密度の分布に偏りが生じるか
らであると考えられる。要するに、ＬＥＤチップ１の発
光面には輝度むらが生じている。By the way, in the above-mentioned LED chip 1 having the conventional structure, the p-side electrode 6 and the n-side electrode 7 are provided one by one in a dot-like manner. Observation results have been obtained that the luminance is high between the p-side electrode 6 and the n-side electrode 7 on the (light extraction surface), but low in other parts. This is because the current density is sufficiently large between the p-side electrode 6 and the n-side electrode 7, but the current density decreases rapidly away from the space between the p-side electrode 6 and the n-side electrode 7. This is considered to be due to the occurrence of bias. In short, the light emitting surface of the LED chip 1 has uneven brightness.
【０００６】一般に提供されているＬＥＤチップ１は発
光面が３００μｍ角程度であって、ｐ側電極６とｎ側電
極７との電極面積に対する発光面の面積の比が比較的小
さいものであるから、発光面に輝度むらが生じていても
通常は実用上で問題になることはない。A generally provided LED chip 1 has a light-emitting surface of about 300 μm square, and the ratio of the area of the light-emitting surface to the electrode area of the p-side electrode 6 and the n-side electrode 7 is relatively small. Even if luminance unevenness occurs on the light emitting surface, there is usually no problem in practical use.
【０００７】一方、最近では白色ＬＥＤを表示器やディ
スプレイに用いるほか照明用光源として用いることが提
案されており、この種の用途に適用するために１チップ
当たりの輝度を大きくすることが要求され、結果的にＬ
ＥＤチップの大面積化が要求されている。ＬＥＤチップ
を大面積化すれば、電極面積に対して発光面の面積が従
来よりも大きくなるから、発光面内の輝度むらが視覚的
に認識されるようになり、照明用光源として使用するに
は問題が生じる。On the other hand, recently, it has been proposed to use a white LED as a light source for illumination in addition to being used for a display or a display, and it is required to increase the luminance per chip in order to apply this type of application. And consequently L
ED chips are required to have a large area. If the area of the LED chip is increased, the area of the light emitting surface becomes larger than that of the conventional electrode, so that uneven brightness on the light emitting surface can be visually recognized. Causes problems.
【０００８】本発明は前記事由に鑑みて為されたもので
あり、その目的は、発光面内の輝度むらを減少させて輝
度の均一性を向上させたＬＥＤチップを提供することに
ある。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an LED chip in which luminance unevenness in a light emitting surface is reduced and luminance uniformity is improved.
【０００９】[0009]
【課題を解決するための手段】請求項１の発明は、基板
上に形成されたｐ形半導体層およびｎ形半導体層と、ｐ
形半導体層およびｎ形半導体層において基板の反対側で
ある主チップ面にそれぞれ接続されたｐ側電極およびｎ
側電極とを備え、前記主チップ面内においてｐ側電極お
よびｎ側電極の少なくとも一部がそれぞれ互いに並行配
置され、ｐ側電極およびｎ側電極において並行配置され
た部位を横切る方向ではｐ側電極とｎ側電極とが交互に
配列されていることを特徴とする。According to the present invention, a p-type semiconductor layer and an n-type semiconductor layer formed on a substrate are provided.
-Side electrode and n-side electrode respectively connected to the main chip surface opposite to the substrate in the n-type semiconductor layer and the n-type semiconductor layer
And at least a part of the p-side electrode and the n-side electrode are respectively arranged in parallel with each other in the main chip plane, and the p-side electrode is arranged in a direction crossing the parallel-arranged portions in the p-side electrode and the n-side electrode. And n-side electrodes are alternately arranged.
【００１０】請求項２の発明は、請求項１の発明におい
て、前記ｐ側電極および前記ｎ側電極において、並行配
置された部位が等間隔になるように配列されていること
を特徴とする。A second aspect of the present invention is characterized in that, in the first aspect of the present invention, in the p-side electrode and the n-side electrode, portions arranged in parallel are arranged at equal intervals.
【００１１】請求項３の発明は、請求項１の発明におい
て、前記ｐ側電極と前記ｎ側電極との少なくとも一方に
ついては、並行配置された部位が主チップ面上では電気
的に接続されていないことを特徴とする。According to a third aspect of the present invention, in the first aspect of the present invention, at least one of the p-side electrode and the n-side electrode is electrically connected on the main chip surface at a portion arranged in parallel. It is characterized by not having.
【００１２】請求項４の発明は、請求項１の発明におい
て、前記ｐ側電極および前記ｎ側電極において、並行配
置された部位を横切る方向にそれぞれ分岐しかつ互いに
並行する複数の枝部が形成されていることを特徴とす
る。According to a fourth aspect of the present invention, in the first aspect of the present invention, the p-side electrode and the n-side electrode are formed with a plurality of branch portions which are branched in a direction crossing the portions arranged in parallel and are parallel to each other. It is characterized by having been done.
【００１３】請求項５の発明は、請求項１の発明におい
て、前記主チップ面内において複数のｐ側電極およびｎ
側電極の少なくとも一部がそれぞれ互いに並行配置され
る渦巻き状に延長され、渦巻き状に形成される部位の中
心から外側に向かってｐ側電極およびｎ側電極を横切る
方向ではｐ側電極とｎ側電極とが交互に配列されている
ことを特徴とする。According to a fifth aspect of the present invention, in the first aspect of the invention, a plurality of p-side electrodes and n
At least a part of the side electrode is extended in a spiral shape arranged in parallel with each other, and the p-side electrode and the n-side electrode extend in a direction crossing the p-side electrode and the n-side electrode from the center of the spirally formed portion to the outside. The electrodes are alternately arranged.
【００１４】請求項６の発明は、基板上に形成されたｐ
形半導体層およびｎ形半導体層と、ｐ形半導体層および
ｎ形半導体層において基板の反対側である主チップ面に
それぞれ接続された複数個ずつのｐ側電極およびｎ側電
極とを備えることを特徴とする。According to a sixth aspect of the present invention, there is provided a semiconductor device comprising:
And a plurality of p-side and n-side electrodes respectively connected to the main chip surface opposite to the substrate in the p-type and n-type semiconductor layers. Features.
【００１５】請求項７の発明は、請求項６の発明におい
て、前記ｐ側電極および前記ｎ側電極のうち異種導電形
の半導体層に接続された電極間の距離を、同種導電形の
半導体層に接続された電極間の距離よりも小さくしたこ
とを特徴とする。According to a seventh aspect of the present invention, in the invention of the sixth aspect, the distance between the p-side electrode and the n-side electrode connected to the semiconductor layer of a different conductivity type is set to be the same as that of the semiconductor layer of the same conductivity type. Characterized in that the distance between the electrodes is smaller than the distance between the electrodes.
【００１６】請求項８の発明は、請求項７の発明におい
て、前記ｐ側電極と前記ｎ側電極のうち異種導電形の半
導体層に接続された電極間が等間隔に配列されているこ
とを特徴とする。According to an eighth aspect of the present invention, in the invention of the seventh aspect, between the p-side electrode and the n-side electrode, electrodes connected to the semiconductor layers of different conductivity types are arranged at equal intervals. Features.
【００１７】請求項９の発明は、基板上に形成されたｐ
形半導体層およびｎ形半導体層と、ｐ形半導体層および
ｎ形半導体層において基板の反対側である主チップ面に
それぞれ接続されたｐ側電極およびｎ側電極とを備え、
前記主チップ面がｐ側電極およびｎ側電極との一方によ
り複数の領域に分割され、各領域内にそれぞれ他方が配
置されることを特徴とする。According to a ninth aspect of the present invention, there is provided a semiconductor device comprising:
A p-type semiconductor layer and an n-type semiconductor layer, and a p-side electrode and an n-side electrode connected to a main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer, respectively.
The main chip surface is divided into a plurality of regions by one of a p-side electrode and an n-side electrode, and the other is disposed in each region.
【００１８】請求項１０の発明は、請求項９の発明にお
いて、前記ｐ側電極と前記ｎ側電極とのうちの前記一方
が前記各領域をそれぞれ全周に亘って囲むように形成さ
れることを特徴とする。According to a tenth aspect of the present invention, in the ninth aspect, the one of the p-side electrode and the n-side electrode is formed so as to surround each of the regions over the entire circumference. It is characterized by.
【００１９】請求項１１の発明は、請求項９の発明にお
いて、前記ｐ側電極と前記ｎ側電極とのうちの前記他方
が前記一方に設けた線状部分に並行配置される線状の部
分を備えることを特徴とする。According to an eleventh aspect of the present invention, in the ninth aspect of the present invention, a linear portion is provided in which the other of the p-side electrode and the n-side electrode is arranged in parallel with a linear portion provided on the one side. It is characterized by having.
【００２０】請求項１２の発明は、基板上に形成された
ｐ形半導体層およびｎ形半導体層と、ｐ形半導体層およ
びｎ形半導体層において基板の反対側である主チップ面
にそれぞれ接続されたｐ側電極およびｎ側電極とを備
え、ｐ側電極およびｎ側電極との一方が主チップ面の中
心部に配置され、前記一方の周囲を囲む形で他方が配置
されていることを特徴とする。According to a twelfth aspect of the present invention, a p-type semiconductor layer and an n-type semiconductor layer formed on a substrate are connected to a main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer, respectively. A p-side electrode and an n-side electrode, one of the p-side electrode and the n-side electrode is disposed at the center of the main chip surface, and the other is disposed so as to surround the periphery of the one. And
【００２１】請求項１３の発明は、請求項１２の発明に
おいて、前記ｐ側電極と前記ｎ側電極とが交互に入れ子
状に配列されていることを特徴とする。According to a thirteenth aspect, in the twelfth aspect, the p-side electrodes and the n-side electrodes are alternately nested.
【００２２】請求項１４の発明は、請求項１３の発明に
おいて、前記ｐ側電極と前記ｎ側電極とが等間隔になる
ように配列されていることを特徴とする。According to a fourteenth aspect, in the thirteenth aspect, the p-side electrode and the n-side electrode are arranged at equal intervals.
【００２３】請求項１５の発明は、請求項１３または請
求項１４の発明において、前記ｐ側電極と前記ｎ側電極
とが同心円状に配列されていることを特徴とする。According to a fifteenth aspect, in the thirteenth or fourteenth aspect, the p-side electrode and the n-side electrode are arranged concentrically.
【００２４】請求項１６の発明は、請求項１３または請
求項１４の発明において、前記ｐ側電極と前記ｎ側電極
とが主チップ面の外周形状の相似形状であることを特徴
とする。In a sixteenth aspect of the present invention, in the thirteenth or fourteenth aspect, the p-side electrode and the n-side electrode have a similar shape to the outer peripheral shape of the main chip surface.
【００２５】請求項１７の発明は、請求項１または請求
項６または請求項９または請求項１２の発明において、
前記ｎ側電極と前記ｐ側電極との配置パターンが、前記
主チップ面内で線対称性を有することを特徴とする。The invention of claim 17 is the invention of claim 1 or claim 6 or claim 9 or claim 12 wherein
The arrangement pattern of the n-side electrode and the p-side electrode has line symmetry in the plane of the main chip.
【００２６】請求項１８の発明は、請求項１または請求
項６または請求項９または請求項１２の発明において、
前記ｎ側電極と前記ｐ側電極との配置パターンが、前記
主チップ面内で２回以上の回転対称性を有することを特
徴とする。The invention according to claim 18 is the invention according to claim 1 or claim 6 or claim 9 or claim 12,
The arrangement pattern of the n-side electrode and the p-side electrode has a rotational symmetry of two or more times in the plane of the main chip.
【００２７】請求項１９の発明は、請求項１または請求
項６または請求項９または請求項１２の発明において、
前記ｎ側電極と前記ｐ側電極との配置パターンが、前記
主チップ面内で２回以上の回転対称性を有するととも
に、２本以上の対称線に関して線対称性を有することを
特徴とする。[0027] The invention of claim 19 is the invention according to claim 1 or claim 6 or claim 9 or claim 12,
The arrangement pattern of the n-side electrode and the p-side electrode has a rotational symmetry two or more times in the main chip plane and a line symmetry with respect to two or more symmetry lines.
【００２８】請求項２０の発明は、請求項１または請求
項６または請求項９の発明において、前記ｎ側電極と前
記ｐ側電極とにそれぞれ給電する給電部を設け、ｎ側電
極とｐ側電極との少なくとも一方の給電部を複数個設け
たことを特徴とする。According to a twentieth aspect of the present invention, in the first, sixth, or ninth aspect of the present invention, a power supply portion is provided for supplying power to the n-side electrode and the p-side electrode, respectively. It is characterized in that a plurality of at least one power supply part with the electrode is provided.
【００２９】上述したいずれの構成も、ｐ側電極とｎ側
電極との間で電流の流れる経路が多く形成されるから、
発光領域を通過する電流の電流密度の差を従来構成に比
較して減少させることができ、発光領域における電流密
度の均一化を図ることができる。その結果、従来構成よ
りも輝度むらを大幅に減少させることができる。なお、
ＬＥＤチップを実装する態様についてはとくに制限はな
く、フェースアップ状態とフェースダウン状態とのいず
れの態様においても上述した構成は適用可能である。た
だし、ｐ側電極およびｎ側電極が点状ではない構成を採
用する場合に、ｐ側電極およびｎ側電極が発光面側に存
在しないフェースダウン状態で実装するほうが、輝度む
らをより低減することが可能である。In any of the above-described configurations, many paths for current flow are formed between the p-side electrode and the n-side electrode.
The difference in the current density of the current passing through the light emitting region can be reduced as compared with the conventional configuration, and the current density in the light emitting region can be made uniform. As a result, luminance unevenness can be significantly reduced as compared with the conventional configuration. In addition,
There is no particular limitation on the mode in which the LED chip is mounted, and the above-described configuration is applicable to both the face-up state and the face-down state. However, when the configuration in which the p-side electrode and the n-side electrode are not dot-shaped is adopted, it is more preferable to mount in a face-down state in which the p-side electrode and the n-side electrode do not exist on the light emitting surface side, thereby further reducing the luminance unevenness. Is possible.
【００３０】[0030]
【発明の実施の形態】以下の各実施形態において説明す
るＬＥＤチップ１は、図２５に示した従来構成と同様
に、サファイヤからなる透光性を有する基板２上に、バ
ッファ層（図示せず）、導電形がｎ形である窒化ガリウ
ム（ＧａＮ）層からなるｎ形半導体層３、クラッド層
（図示せず）、発光層４（図２３参照）に、クラッド層
（図示せず）、導電形がｐ形である窒化ガリウム（Ｇａ
Ｎ）層からなるｐ形半導体層５を順に積み重ねた構成を
有する。ただし、半導体の種類は上述のような窒化ガリ
ウム系化合物半導体に限定されるものではなく、他の半
導体も用いることができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS An LED chip 1 described in each of the following embodiments has a buffer layer (not shown) on a light-transmitting substrate 2 made of sapphire, similarly to the conventional configuration shown in FIG. ), An n-type semiconductor layer 3 composed of a gallium nitride (GaN) layer having an n-type conductivity, a cladding layer (not shown), a light emitting layer 4 (see FIG. 23), a cladding layer (not shown), and a conductive layer. Gallium nitride (Ga
It has a configuration in which p-type semiconductor layers 5 composed of N) layers are sequentially stacked. However, the type of semiconductor is not limited to the gallium nitride-based compound semiconductor as described above, and other semiconductors can also be used.
【００３１】ｎ形半導体層３において基板２とは反対側
の面にはｎ側電極７が形成され、ｐ形半導体層５におい
て基板２とは反対側の面にはｐ側電極６が形成される。
ｎ形半導体層３およびｐ形半導体層５を含む半導体層に
おいて基板１とは反対側の面、すなわちｐ側電極６およ
びｎ側電極７を設けている面を以下では主チップ面と呼
ぶ。このＬＥＤチップ１を用いて照明用の光源装置を構
成する場合には、図２４に示すように、近紫外線により
励起されて黄色を発光する蛍光体を分散させた透光性合
成樹脂のカバー１２内にＬＥＤチップ１を配置すれば、
ＬＥＤチップ１から発光する青色の光とカバー１２内の
蛍光体からの黄色の光とを混色させて白色光の光源装置
を構成することができる。また、図示例では実装基板８
に対してフリップチップ実装を施してフェースダウン状
態で実装してある。なお、以下の実施形態においては、
ＬＥＤチップ１の主チップ面を正方形状に形成している
が、主チップ面の形状はこれに限定されるものではな
い。また、以下に説明する実施形態において、ｐ側電極
６とｎ側電極７とは入れ換え可能である。An n-side electrode 7 is formed on the surface of the n-type semiconductor layer 3 opposite to the substrate 2, and a p-side electrode 6 is formed on the surface of the p-type semiconductor layer 5 opposite to the substrate 2. You.
The surface of the semiconductor layer including the n-type semiconductor layer 3 and the p-type semiconductor layer 5 opposite to the substrate 1, that is, the surface on which the p-side electrode 6 and the n-side electrode 7 are provided is hereinafter referred to as a main chip surface. When a light source device for illumination is configured using the LED chip 1, as shown in FIG. 24, a cover 12 made of a light-transmitting synthetic resin in which a phosphor that emits yellow light when excited by near-ultraviolet light is dispersed. If you place the LED chip 1 inside
By mixing the blue light emitted from the LED chip 1 with the yellow light from the phosphor in the cover 12, a white light source device can be configured. In the illustrated example, the mounting substrate 8
Are mounted in a face-down state by flip-chip mounting. In the following embodiment,
Although the main chip surface of the LED chip 1 is formed in a square shape, the shape of the main chip surface is not limited to this. Further, in the embodiment described below, the p-side electrode 6 and the n-side electrode 7 are interchangeable.
【００３２】（実施形態１）本実施形態は請求項１、請
求項２に対応する。本実施形態では、図１に示すよう
に、ｐ側電極６およびｎ側電極７がＬＥＤチップ１の主
チップ面内において直線部６ａ，７ａを有し、直線部６
ａ，７ａが並行配置されるとともに直線部６ａ，７ａに
おいてｐ側電極６およびｎ側電極７を横切る方向（直交
する方向）ではｐ側電極６とｎ側電極７とが交互に配列
される。また、ｐ側電極６およびｎ側電極７について図
示例では直線部６ａ，７ａを２本ずつ等間隔に設けてあ
り、同種導電形の半導体層３，５（図２３参照）に接続
された直線部６ａ，７ａ同士は、直線部６ａ，７ａの一
端部に設けた導電部１３，１４によりそれぞれ接続され
る。つまり、ｎ側電極７の直線部７ａ間は導電部１３に
より電気的に接続され、ｐ側電極６の直線部６ａ間は導
電部１４により電気的に接続される。本実施形態ではＬ
ＥＤチップ１の主チップ面の１つの対角線上の角部付近
にｐ側電極６およびｎ側電極７とそれぞれ電気的に接続
された２つの給電部１５，１６をアルミニウム蒸着など
により形成してある。つまり、ｐ側電極６とｎ側電極７
とは、それぞれ２本ずつの直線部６ａ，７ａの間の部位
に１箇所ずつの給電部１５，１６を設けてあり、給電部
１５，１６から各直線部６ａ，７ａに分かれて電流が流
れるようにしてある。(Embodiment 1) This embodiment corresponds to claims 1 and 2. In the present embodiment, as shown in FIG. 1, the p-side electrode 6 and the n-side electrode 7 have linear portions 6a, 7a in the main chip surface of the LED chip 1, and the linear portion 6
The p-side electrodes 6 and the n-side electrodes 7 are alternately arranged in the direction (orthogonal direction) crossing the p-side electrode 6 and the n-side electrode 7 in the linear portions 6a, 7a. In the illustrated example, the p-side electrode 6 and the n-side electrode 7 are each provided with two straight portions 6a and 7a at equal intervals, and the straight portions connected to the semiconductor layers 3 and 5 of the same conductivity type (see FIG. 23). The portions 6a and 7a are connected to each other by conductive portions 13 and 14 provided at one ends of the linear portions 6a and 7a, respectively. That is, the linear portions 7a of the n-side electrode 7 are electrically connected by the conductive portion 13, and the linear portions 6a of the p-side electrode 6 are electrically connected by the conductive portion 14. In the present embodiment, L
In the vicinity of one diagonal corner of the main chip surface of the ED chip 1, two power supply portions 15, 16 electrically connected to the p-side electrode 6 and the n-side electrode 7, respectively, are formed by aluminum evaporation or the like. . That is, the p-side electrode 6 and the n-side electrode 7
Means that one power supply portion 15, 16 is provided at a portion between two linear portions 6a, 7a, respectively, and current flows from the power supply portions 15, 16 to each of the linear portions 6a, 7a. It is like that.
【００３３】しかして、本実施形態のＬＥＤチップ１に
おいて給電部１５，１６に通電して点灯させると、ｐ側
電極６およびｎ側電極７において並行配置された直線部
６ａ，７ａの間にそれぞれ発光領域が形成されるから、
１個のＬＥＤチップ１内で電流経路を集中させることな
く電流を流すことができ、ＬＥＤチップ１の発光面の輝
度を均一化させることができる。つまり、本実施形態で
はｐ側電極６とｎ側電極７とが対向する部位が従来構成
よりも多く、しかもｐ側電極６とｎ側電極７とが等距離
になる部位が多いから、電流密度の分布の偏りを低減し
て輝度の均斉度を高めることができる。When the power is supplied to the power supply portions 15 and 16 in the LED chip 1 of the present embodiment to light the LED chip 1, the p-side electrode 6 and the n-side electrode 7 are disposed between the linear portions 6a and 7a arranged in parallel. Because the light emitting area is formed,
A current can flow without concentrating a current path in one LED chip 1, and the luminance of the light emitting surface of the LED chip 1 can be made uniform. That is, in the present embodiment, there are more parts where the p-side electrode 6 and the n-side electrode 7 face each other than in the conventional configuration, and there are many parts where the p-side electrode 6 and the n-side electrode 7 are equidistant. Can be reduced to increase the luminance uniformity.
【００３４】図１に示した構成ではｐ側電極６およびｎ
側電極７において並行配置する部位が直線部６ａ，７ａ
として形成されていたが、図２に示すように、ｐ側電極
６およびｎ側電極７に蛇行する形状の波形部６ｂ，７ｂ
を形成し、波形部６ｂ，７ｂを並行させるようにしても
よい。あるいはまた、図３に示すように、ｐ側電極６お
よびｎ側電極７にＬ字状に屈曲させた屈曲部６ｃ，７ｃ
を形成し、屈曲部６ｃ，７ｃを並行させるようにしても
よい。図２および図３に示した構成例では、給電部１
５，１６を２本の波形部６ｂ，７ｂないし屈曲部６ｃ，
７ｃのうちの一方であって導電部１３，１４から離れた
端部に設けてある。いずれの構成においても、給電部１
５，１６の位置はｐ側電極６とｎ側電極７との間に流れ
る電流の電流密度が均一化されるように選択されてい
る。In the structure shown in FIG. 1, the p-side electrode 6 and n
In the side electrode 7, the portions arranged in parallel are the straight portions 6a, 7a.
As shown in FIG. 2, the p-side electrode 6 and the n-side electrode 7 have meandering waveform portions 6b, 7b.
May be formed, and the waveform portions 6b and 7b may be arranged in parallel. Alternatively, as shown in FIG. 3, the p-side electrode 6 and the n-side electrode 7 have bent portions 6c, 7c bent in an L shape.
And the bent portions 6c and 7c may be arranged in parallel. In the configuration examples shown in FIG. 2 and FIG.
5 and 16 are replaced by two corrugated portions 6b, 7b or bent portions 6c,
7c, which is provided at an end remote from the conductive portions 13 and 14. In either configuration, the power supply unit 1
The positions of 5 and 16 are selected so that the current density of the current flowing between the p-side electrode 6 and the n-side electrode 7 is made uniform.
【００３５】（実施形態２）本実施形態は請求項３に対
応する。本実施形態では、図４に示すように、ｐ側電極
６とｎ側電極７とがＬＥＤチップ１の主チップ面内にお
いて直線部６ａ，７ａを有し、直線部６ａ，７ａが並行
配置されるとともに直線部６ａ，７ａにおいてｐ側電極
６およびｎ側電極７を横切る方向（直交する方向）では
ｐ側電極６とｎ側電極７とが交互に配列される。また、
ｐ側電極６およびｎ側電極７について図示例では直線部
６ａ，７ａを２本ずつ等間隔に設けてある。ただし、実
施形態１とは異なり直線部６ａ，７ａはＬＥＤチップ１
内では電気的に接続されておらず独立している。したが
って、給電部１５，１６は各直線部６ａ，７ａごとに個
別に設けてある。また、ｐ側電極６の給電部１５を直線
部６ａの一端側に設けるとすれば、ｎ側電極７の給電部
１６は直線部７ａの他端側に設けるようにしてあり、直
線部６ａ，７ａの間で電流が分散して流れるようにして
ある。(Embodiment 2) This embodiment corresponds to claim 3. In the present embodiment, as shown in FIG. 4, the p-side electrode 6 and the n-side electrode 7 have linear portions 6a and 7a in the main chip surface of the LED chip 1, and the linear portions 6a and 7a are arranged in parallel. In addition, the p-side electrodes 6 and the n-side electrodes 7 are alternately arranged in a direction (orthogonal direction) crossing the p-side electrode 6 and the n-side electrode 7 in the linear portions 6a and 7a. Also,
In the illustrated example, the p-side electrode 6 and the n-side electrode 7 are provided with two straight portions 6a and 7a at regular intervals. However, unlike the first embodiment, the linear portions 6a and 7a are
It is not electrically connected inside and is independent. Therefore, the power supply sections 15 and 16 are provided individually for each of the straight sections 6a and 7a. Further, if the power supply portion 15 of the p-side electrode 6 is provided at one end of the linear portion 6a, the power supply portion 16 of the n-side electrode 7 is provided at the other end of the linear portion 7a. The current is dispersed and flows between 7a.
【００３６】本実施形態の構成では、ｐ側電極６および
ｎ側電極７において並行配置されていない部位の割合が
実施形態１よりも少なくなる結果、発光領域の電流密度
の偏りがより少なくなり、実施形態１の構成よりも輝度
の均斉度がさらに高くなる。In the configuration of the present embodiment, the proportion of the non-parallel portions in the p-side electrode 6 and the n-side electrode 7 is smaller than that in the first embodiment. As a result, the bias of the current density in the light emitting region is reduced. The luminance uniformity is higher than in the configuration of the first embodiment.
【００３７】実施形態１と同様に、直線部６ａ，７ａに
代えて波形部６ａ，７ａのように曲線状とすることも可
能であり、また図５に示すように、Ｌ字状に屈曲した屈
曲部６ｃ，７ｃを用いることも可能である。As in the first embodiment, it is also possible to form a curved portion like the wave portions 6a and 7a instead of the straight portions 6a and 7a, and to bend into an L-shape as shown in FIG. It is also possible to use the bent portions 6c and 7c.
【００３８】（実施形態３）本実施形態は請求項４に対
応する。すなわち、図６に示すように、図１に示した実
施形態１の構成と同様の構成を有したｐ側電極６および
ｎ側電極７を設け、さらに直線部６ａ，７ａの直交方向
にそれぞれ分岐する複数の枝部６ｄ，７ｄを設け、枝部
６ｄ，７ｄが互いに並行するように設置してある。本実
施形態では、図１に示した実施形態１の構成に比較する
と、対向するｐ側電極６とｎ側電極７との間の距離が短
かく、かつｐ側電極６およびｎ側電極７の発光面全体に
占める密度が大きいから、ＬＥＤチップ１を点灯させた
ときに発光面全体の輝度が実施形態１の構成よりもさら
に均一化される。(Embodiment 3) This embodiment corresponds to claim 4. That is, as shown in FIG. 6, a p-side electrode 6 and an n-side electrode 7 having the same configuration as that of the first embodiment shown in FIG. A plurality of branches 6d and 7d are provided, and the branches 6d and 7d are installed so as to be parallel to each other. In the present embodiment, the distance between the opposing p-side electrode 6 and the n-side electrode 7 is shorter than that of the configuration of the first embodiment shown in FIG. Since the density occupying the entire light-emitting surface is large, the brightness of the entire light-emitting surface when the LED chip 1 is turned on is made more uniform than in the configuration of the first embodiment.
【００３９】（実施形態４）本実施形態は請求項５に対
応する。本実施形態では、図７に示すように、ｐ側電極
６とｎ側電極７とを主チップ面においてそれぞれ渦巻き
状に形成してある。図示例ではｐ側電極６とｎ側電極７
とをともに中心から左回りの渦巻き状として並行配置し
てあり、中心から外側に向かってｐ側電極６とｎ側電極
７とを横切る方向ではｐ側電極６とｎ側電極７とが交互
に配列されるようにしてある。また、給電部１５，１６
は中心側の一端に設けてある。この構成によっても、発
光面全体に対してｐ側電極６とｎ側電極７とにおける互
いに並行していない部分の割合が図１に示した実施形態
１よりも少ないから、発光面の輝度をさらに均一化させ
ることが可能になる。ここに、渦巻き状として図７では
滑らかな曲線状の渦巻きを例示しているが、図８に示す
ように直線を連結した形状の渦巻きとしても同様の効果
が得られる。また、図８に示す構成では給電部１５，１
６を渦巻きの外側の端部としてあり、この構成ではチッ
プ面上で給電部１５，１６が離れて配置されるから電流
密度の分布の偏りを低減して発光面の輝度を均斉化しや
すくなる。(Embodiment 4) This embodiment corresponds to claim 5. In this embodiment, as shown in FIG. 7, the p-side electrode 6 and the n-side electrode 7 are each formed in a spiral shape on the main chip surface. In the illustrated example, the p-side electrode 6 and the n-side electrode 7
Are arranged in parallel in a counterclockwise spiral form from the center, and in a direction crossing the p-side electrode 6 and the n-side electrode 7 from the center outward, the p-side electrode 6 and the n-side electrode 7 are alternately arranged. They are arranged. In addition, the power supply units 15 and 16
Is provided at one end on the center side. According to this configuration as well, the ratio of the non-parallel portions of the p-side electrode 6 and the n-side electrode 7 to the entire light emitting surface is smaller than that of the first embodiment shown in FIG. It can be made uniform. Although FIG. 7 illustrates a spiral having a smooth curve as the spiral, a similar effect can be obtained by using a spiral having a shape in which straight lines are connected as shown in FIG. In the configuration shown in FIG.
Numeral 6 is the outer end of the spiral. In this configuration, since the power supply portions 15 and 16 are arranged apart from each other on the chip surface, the bias of the current density distribution is reduced, and the luminance of the light emitting surface is easily equalized.
【００４０】（実施形態５）本実施形態は請求項６、請
求項７、請求項８に対応する。本実施形態は図９に示す
ように、主チップ面においてｎ形半導体層３に複数個の
ｎ側電極７を設けるとともに、ｐ形半導体層５に複数個
のｐ側電極６を設けた構成を有する。図示例ではｐ側電
極６およびｎ側電極７のうち同種導電形の半導体層に対
応する電極間は異種導電形の半導体層に対応する電極間
の距離よりも大きくなっている。また、ｐ側電極６およ
びｎ側電極７のうち同種導電形の半導体層に対応する電
極間は等間隔となるように配列されている。要するに、
主チップ面の四隅のうち一方の対角線の両端部にはｐ側
電極６（給電部１５と兼用）が配置され、他方の対角線
の両端部にはｎ側電極７（給電部１６と兼用）が配置さ
れる。この構成により、異種導電形に対応する電極間で
等距離になる部分を従来構成よりも増やすことになり、
発光面の輝度を均一化することが可能になる。(Embodiment 5) This embodiment corresponds to claims 6, 7 and 8. As shown in FIG. 9, the present embodiment has a configuration in which a plurality of n-side electrodes 7 are provided on an n-type semiconductor layer 3 and a plurality of p-side electrodes 6 are provided on a p-type semiconductor layer 5 on the main chip surface. Have. In the illustrated example, the distance between the electrodes corresponding to the semiconductor layers of the same conductivity type of the p-side electrode 6 and the n-side electrode 7 is larger than the distance between the electrodes corresponding to the semiconductor layers of the different conductivity type. The electrodes of the p-side electrode 6 and the n-side electrode 7 corresponding to the semiconductor layers of the same conductivity type are arranged at equal intervals. in short,
At four ends of the four corners of the main chip surface, a p-side electrode 6 (also used as the power supply unit 15) is disposed at both ends of one diagonal, and an n-side electrode 7 (also used as the power supply unit 16) is provided at both ends of the other diagonal. Be placed. With this configuration, the portion that is equidistant between electrodes corresponding to different types of conductivity will be increased compared to the conventional configuration,
It is possible to make the luminance of the light emitting surface uniform.
【００４１】図１０に示すように、ｐ側電極６とｎ側電
極７とを３個ずつ設ける構成として、主チップ面の四隅
に４個の電極を配置するとともに残りの２個の電極を主
チップ面の中央部に配置する構成を採用してもよい。つ
まり、同種導電形の半導体層に対応する各３個の電極を
三角形状に配置するとともに２個の電極を主チップ面の
隣り合う隅部に配置し、残りの１個の電極を主チップ面
の中央部に配置しているのであって、異種導電形の半導
体層に対応する電極のうちの１つは上述した三角形の中
に位置するように配置される。この構成では、異種導電
形の半導体層に対応する電極間の電流経路が複数形成さ
れるから、発光面の輝度の均斉度が比較的高くなり、し
かも主チップ面の中央付近では異種導電形の半導体層に
対応する電極間の距離が他の部位よりも小さいから、発
光面の中央付近の輝度が周辺部分よりも高くなる。要す
るに全体としては発光面の輝度の均一性を保ちながら
も、中心付近の輝度を高くすることが可能になる。As shown in FIG. 10, three p-side electrodes 6 and three n-side electrodes 7 are provided so that four electrodes are arranged at the four corners of the main chip surface and the remaining two electrodes are mainly used. A configuration in which it is arranged at the center of the chip surface may be adopted. That is, three electrodes each corresponding to a semiconductor layer of the same conductivity type are arranged in a triangular shape, two electrodes are arranged in adjacent corners of the main chip surface, and the other electrode is connected to the main chip surface. And one of the electrodes corresponding to the semiconductor layers of different conductivity types is arranged so as to be located in the above-described triangle. In this configuration, since a plurality of current paths between the electrodes corresponding to the semiconductor layers of different conductivity types are formed, the uniformity of the luminance of the light emitting surface is relatively high, and near the center of the main chip surface, the different conductivity types are used. Since the distance between the electrodes corresponding to the semiconductor layer is smaller than other portions, the luminance near the center of the light emitting surface is higher than that at the peripheral portion. In short, it is possible to increase the luminance near the center while maintaining the uniformity of the luminance of the light emitting surface as a whole.
【００４２】（実施形態６）本実施形態は請求項９に対
応する。本実施形態では図１１に示すように、ｎ形半導
体層３とｐ形半導体層５にそれぞれ接続されるｐ側電極
６とｎ側電極７とのうちの一方の電極を直線状に形成
し、この電極により主チップ面を２つの領域に分割する
とともに、各領域ごとに他方の電極を設けた構成として
ある。図示例ではｐ側電極６を主チップ面の一方の対角
線に重なる直線状に形成して主チップ面を２つの領域に
分割し、ｎ側電極７を各領域ごとに設けてある。この構
成においても従来構成に比較するとｐ側電極６とｎ側電
極７との間の対向部分が多く形成されるから発光面の輝
度が均一化される。(Embodiment 6) This embodiment corresponds to claim 9. In the present embodiment, as shown in FIG. 11, one of the p-side electrode 6 and the n-side electrode 7 connected to the n-type semiconductor layer 3 and the p-type semiconductor layer 5, respectively, is formed linearly. The main chip surface is divided into two regions by these electrodes, and the other electrode is provided for each region. In the illustrated example, the p-side electrode 6 is formed in a straight line overlapping one diagonal of the main chip surface, the main chip surface is divided into two regions, and the n-side electrode 7 is provided for each region. Also in this configuration, as compared with the conventional configuration, more opposing portions are formed between the p-side electrode 6 and the n-side electrode 7, so that the luminance of the light emitting surface is made uniform.
【００４３】図１１に示す構成ではｎ側電極７を直線状
に形成しているが電極の形状は直線状に限定されるもの
ではなく、たとえばＳ字状のように曲線状に形成しても
同様の効果が得られる。主チップ面を分割する電極はｐ
側電極６とｎ側電極７とのどちらでもよい。In the configuration shown in FIG. 11, the n-side electrode 7 is formed in a straight line. However, the shape of the electrode is not limited to a straight line. Similar effects can be obtained. The electrode dividing the main chip surface is p
Either the side electrode 6 or the n-side electrode 7 may be used.
【００４４】また、ｐ側電極６とｎ側電極７との一方の
電極を図１２に示すようにＨ字状などに形成して領域を
分割してもよく、また２分割である必要もない。たとえ
ば、ｐ側電極６を十字状に形成することにより主チップ
面を４つの領域に分割し、各領域の中央部にそれぞれｎ
側電極７を配置する構成としてもよい。このように分割
する領域の個数を増やすと発光面の輝度の均一性をより
高めることが可能になる。Further, one of the p-side electrode 6 and the n-side electrode 7 may be formed in an H shape or the like as shown in FIG. 12 to divide the region, and it is not necessary to divide the region into two. . For example, by forming the p-side electrode 6 in a cross shape, the main chip surface is divided into four regions, and n regions are provided at the center of each region.
The side electrode 7 may be arranged. Increasing the number of regions to be divided in this way makes it possible to further improve the uniformity of the luminance of the light emitting surface.
【００４５】（実施形態７）本実施形態は請求項１１に
対応する。本実施形態では図１３に示すように、図１２
に示した実施形態６の構成に対して、Ｈ字状のｐ側電極
６において主チップ面の中央部に位置する直線部分に並
行するようにｎ側電極７を直線状に延長したものであ
る。この構成を採用すれば、図１２に示した実施形態６
の構成よりもｐ側電極６とｎ側電極７とが等距離になる
部分が増えるから、発光面の輝度をより均一化すること
が可能になる。なお、本実施形態においてもｐ側電極６
とｎ側電極７との関係を逆にしてもよい。(Embodiment 7) This embodiment corresponds to claim 11. In the present embodiment, as shown in FIG.
The n-side electrode 7 is extended linearly so as to be parallel to the linear portion located at the center of the main chip surface in the H-shaped p-side electrode 6 in the configuration of the sixth embodiment shown in FIG. . If this configuration is adopted, the sixth embodiment shown in FIG.
Since the portion where the p-side electrode 6 and the n-side electrode 7 are equidistant from each other is increased as compared with the configuration described above, the luminance of the light emitting surface can be made more uniform. In this embodiment, the p-side electrode 6 is also used.
And the relationship between n and the n-side electrode 7 may be reversed.
【００４６】（実施形態８）本実施形態は請求項１０に
対応する。本実施形態では図１４に示すように、ｐ側電
極６を日字状に形成し、主チップ面に長方形状の２つの
領域を形成してある。つまり、ｐ側電極６により全周を
囲んだ領域を２つ形成してあり、各領域ごとにｎ側電極
７を設けている。この構成では図１２に示した実施形態
６の構成に比較するとｐ側電極６とｎ側電極７との間の
電流経路が増加することになり、発光面における輝度の
均一性がさらに向上する。(Embodiment 8) This embodiment corresponds to claim 10. In the present embodiment, as shown in FIG. 14, the p-side electrode 6 is formed in a letter shape, and two rectangular regions are formed on the main chip surface. That is, two regions are formed around the entire circumference by the p-side electrode 6, and the n-side electrode 7 is provided for each region. In this configuration, the current path between the p-side electrode 6 and the n-side electrode 7 is increased as compared with the configuration of the sixth embodiment shown in FIG. 12, and the uniformity of luminance on the light emitting surface is further improved.
【００４７】本実施形態では、ｐ側電極６によって主チ
ップ面に２つの領域を形成しているが、領域の個数数は
２個に限定されるものではなく、たとえば図１５に示す
ように、田字状のｐ側電極６を形成して主チップ面を４
領域に分割してｐ側電極６に全周を囲まれた領域を４個
形成し、各領域の中央部にそれぞれｎ側電極７を配置し
てもよい。このような構成を採用すれば、図１４に示し
た構成に比較して発光面における輝度の均一性がさらに
向上する。本実施形態においても、ｐ側電極６とｎ側電
極７との関係を逆にしてもよい。In the present embodiment, two regions are formed on the main chip surface by the p-side electrode 6, but the number of regions is not limited to two. For example, as shown in FIG. A p-side electrode 6 is formed in the shape of a letter so that the main chip surface is 4
It is also possible to divide into four regions and form four regions around the entire periphery of the p-side electrode 6 and arrange the n-side electrode 7 at the center of each region. With such a configuration, the uniformity of luminance on the light emitting surface is further improved as compared with the configuration shown in FIG. Also in the present embodiment, the relationship between the p-side electrode 6 and the n-side electrode 7 may be reversed.
【００４８】（実施形態９）本実施形態は請求項１２に
対応する。本実施形態では、図１６に示すように、主チ
ップ面の略中央部にｐ側電極６を配置し、ｎ側電極７に
よってｐ側電極６の全周を囲んだ形としているものであ
る。ｐ側電極６は主チップ面の中央から３方向に直線部
分を放射状に延長し、一方、ｎ側電極７はｐ側電極６と
中心を一致させた円形部分の内側に中心に向かって３本
の直線部分を突設した形状に形成してあり、ｐ側電極６
とｎ側電極７との直線部分を等角度間隔で配置してあ
る。また、ｐ側電極６の給電部１５は主チップ面の中央
部とし、ｎ側電極７の給電部１６は円形部分の１箇所に
設定してある。この構成ではｐ側電極６とｎ側電極７と
が３回回転対称となる対称性を有した配置になる。本実
施形態のＬＥＤチップ１は、図２５に示した従来構成に
比較して、ｐ側電極６とｎ側電極７との対向部分が多い
から、発光面における輝度の均一性が向上する。なお、
本実施形態においてもｐ側電極６とｎ側電極７との配置
関係を逆にしてもよい。(Embodiment 9) This embodiment corresponds to claim 12. In the present embodiment, as shown in FIG. 16, the p-side electrode 6 is arranged substantially at the center of the main chip surface, and the entire periphery of the p-side electrode 6 is surrounded by the n-side electrode 7. The p-side electrode 6 extends linearly in three directions radially from the center of the main chip surface in three directions, while the n-side electrode 7 extends inward from the center of the circular part whose center coincides with the p-side electrode 6 toward the center. Is formed in a shape in which a straight line portion of the p-side electrode 6 is projected.
And a straight line portion with the n-side electrode 7 are arranged at equal angular intervals. The power supply section 15 of the p-side electrode 6 is set at the center of the main chip surface, and the power supply section 16 of the n-side electrode 7 is set at one of the circular portions. In this configuration, the p-side electrode 6 and the n-side electrode 7 have an arrangement having a symmetry of three-fold rotational symmetry. The LED chip 1 of the present embodiment has more opposing portions of the p-side electrode 6 and the n-side electrode 7 as compared with the conventional configuration shown in FIG. 25, so that the luminance uniformity on the light emitting surface is improved. In addition,
Also in the present embodiment, the arrangement relationship between the p-side electrode 6 and the n-side electrode 7 may be reversed.
【００４９】（実施形態１０）本実施形態は請求項１
３、請求項１４、請求項１５に対応する。本実施形態で
は、図１７に示すように、ｐ側電極６とｎ側電極７とを
同心円状に配置し、かつ円の中心から外側に向かってｐ
側電極６とｎ側電極７とを交互に入れ子状に配置してあ
る。つまり、中心のｐ側電極６を円環状のｎ側電極７に
より囲み、そのｎ側電極７を円環状のｐ側電極６で囲
み、さらにそのｐ側電極６をｎ側電極７で囲んだ形とし
てある。また、ｐ側電極６とｎ側電極７との隣接する電
極間の距離を等距離になるように構成してある。円環状
のｐ側電極６およびｎ側電極７には１箇所ずつ給電部１
５，１６が設けられる。本実施形態のＬＥＤチップ１
は、ｐ側電極６とｎ側電極７との間で等距離で対向する
部分が図１６に示した実施形態９よりも多くなり、発光
面の輝度の均一性がさらに向上する。(Embodiment 10) This embodiment is characterized by claim 1
This corresponds to claim 14, claim 15 and claim 15. In the present embodiment, as shown in FIG. 17, the p-side electrode 6 and the n-side electrode 7 are arranged concentrically and p
The side electrodes 6 and the n-side electrodes 7 are alternately nested. That is, the center p-side electrode 6 is surrounded by an annular n-side electrode 7, the n-side electrode 7 is surrounded by an annular p-side electrode 6, and the p-side electrode 6 is further surrounded by an n-side electrode 7. There is. Further, the distance between adjacent electrodes of the p-side electrode 6 and the n-side electrode 7 is configured to be equal. The power supply unit 1 is provided at each of the annular p-side electrode 6 and the n-side electrode 7.
5 and 16 are provided. LED chip 1 of the present embodiment
The number of portions where the p-side electrode 6 and the n-side electrode 7 oppose each other at equal distances is greater than in the ninth embodiment shown in FIG. 16, and the uniformity of the luminance of the light emitting surface is further improved.
【００５０】また、図１６の実施形態では、主チップ面
において互いに電気的に接続されていない複数個の独立
したｐ側電極６とｎ側電極７とが設けられ、各ｐ側電極
６とｎ側電極７とにそれぞれ給電部１５，１６を設けて
いるが、図１８または図１９に示すように、ｐ側電極６
とｎ側電極７とについて同種導電形の半導体層に対応す
る電極同士をそれぞれ接続する導電部１３，１４を設け
てもよい。この場合には、円環状のｐ側電極６とｎ側電
極７との一部を切除し、切除した部分を導電部１３，１
４が通るようにすればよい。この構成によっても図１７
に示した構成と同様の効果が得られる。In the embodiment shown in FIG. 16, a plurality of independent p-side electrodes 6 and n-side electrodes 7 which are not electrically connected to each other are provided on the main chip surface. Power supply portions 15 and 16 are provided on the side electrode 7 respectively, and as shown in FIG. 18 or FIG.
Conductive portions 13 and 14 for connecting the electrodes corresponding to the semiconductor layers of the same conductivity type with respect to the n-side electrode 7 may be provided. In this case, a part of the ring-shaped p-side electrode 6 and the n-side electrode 7 is cut off, and the cut-off part is replaced with the conductive portions 13 and 1.
4 may be passed. With this configuration, FIG.
The same effect as the configuration shown in FIG.
【００５１】（実施形態１１）本実施形態は請求項１６
に対応する。図１７に示した実施形態１０の構成では円
環状に形成したｐ側電極６およびｎ側電極７を用いてい
るが、本実施形態では、図２０に示すように、円環状で
はなく正方形状に形成したｐ側電極６とｎ側電極７とを
入れ子状に配列してある。つまり、ｐ側電極６とｎ側電
極７とのうち異種導電形の半導体層に対応する電極を囲
むほうの電極を、主チップ面の外周形状と相似形となる
環状に形成している。(Embodiment 11) This embodiment is directed to Claim 16
Corresponding to In the configuration of the tenth embodiment shown in FIG. 17, the p-side electrode 6 and the n-side electrode 7 formed in an annular shape are used, but in the present embodiment, as shown in FIG. The formed p-side electrode 6 and n-side electrode 7 are nested. That is, of the p-side electrode 6 and the n-side electrode 7, the electrode surrounding the electrode corresponding to the semiconductor layer of the different conductivity type is formed in an annular shape similar to the outer peripheral shape of the main chip surface.
【００５２】本実施形態の構成では、ｐ側電極６とｎ側
電極７とを同心円状に配列した構成に比較するとｐ側電
極６とｎ側電極７との距離が等距離になる部位が少なく
なるものの、ｐ側電極６ないしｎ側電極７を主チップ面
の外周縁のごく近傍まで形成することができるから、結
果的に主チップ面の中心部と周縁部との輝度差を小さく
することができる。In the configuration of the present embodiment, compared with the configuration in which the p-side electrode 6 and the n-side electrode 7 are arranged concentrically, there are fewer portions where the distance between the p-side electrode 6 and the n-side electrode 7 is equal. However, since the p-side electrode 6 to the n-side electrode 7 can be formed very close to the outer peripheral edge of the main chip surface, the luminance difference between the central portion and the peripheral portion of the main chip surface can be reduced as a result. Can be.
【００５３】（実施形態１２）本実施形態は請求項６、
請求項１７、請求項１８、請求項１９に対応する。本実
施形態では図２１に示すように主チップ面に複数個ずつ
設けたものであり（ｐ側電極６を５個、ｎ側電極７を４
個設けている）、ｐ側電極６とｎ側電極７とのうち異種
導電形の半導体層に対応する電極間の距離を等しくする
ように配置してある。また、主チップ面においてｐ側電
極６とｎ側電極７とが対称性を有するように配列してあ
る。具体的には、正方形の主チップ面の四隅と中心とに
それぞれｐ側電極６を配置し、各辺の中央にそれぞれｎ
側電極７を配置した形になる。ｐ側電極６とｎ側電極７
との配置パターンを上述のような形とすることにより、
縦横斜めの４本の対称線を持つ線対称性と、主チップ面
の中心を通る対称軸を有した４回の回転対称性とを有す
る配置パターンになる。本実施形態の構成では、ｐ側電
極６とｎ側電極７との間で電流経路が従来構成よりも多
いから、発光面の輝度の均一性が高くなる。(Embodiment 12) This embodiment is a sixth embodiment.
It corresponds to claim 17, claim 18, and claim 19. In this embodiment, a plurality of p-side electrodes 6 and four n-side electrodes 7 are provided on the main chip surface as shown in FIG.
Of the p-side electrode 6 and the n-side electrode 7 so as to make the distance between the electrodes corresponding to the semiconductor layers of different conductivity types equal. The p-side electrode 6 and the n-side electrode 7 are arranged so as to have symmetry on the main chip surface. Specifically, the p-side electrodes 6 are arranged at the four corners and the center of the square main chip surface, and n
It has a shape in which the side electrodes 7 are arranged. p-side electrode 6 and n-side electrode 7
By making the above arrangement pattern as above,
The arrangement pattern has line symmetry having four vertical and horizontal diagonal lines of symmetry and four times rotational symmetry having a symmetry axis passing through the center of the main chip surface. In the configuration of the present embodiment, the number of current paths between the p-side electrode 6 and the n-side electrode 7 is greater than in the conventional configuration, so that the luminance uniformity of the light emitting surface is improved.
【００５４】なお、ｐ側電極６とｎ側電極７との形状は
点状に限定されるものではなく、請求項９の発明と同様
に、主チップ面を複数の領域に分割する形状にｐ側電極
６を形成し分割された各領域にｎ側電極７を配置する構
成を採用してもよい。たとえば、図２２に示すように、
ｐ側電極６の外周を正六角形とするとともに３本の対角
線上にもｐ側電極６を形成して主チップ面に６個の領域
を形成し、正三角形となる各領域の中心にｎ側電極７を
配置する構成としてもよい。この構成では、ｐ側電極６
とｎ側電極７との配置パターンが、６本の対称線を有す
る線対称性を持ち、かつ６回の回転対称性を有すること
になる。請求項９に対応する図１１ないし図１５に示し
た構成に比較してｐ側電極６とｎ側電極７との配置パタ
ーンの対称性が高い本実施形態の構成では、これらの構
成よりも発光面における輝度の均一性がより高くなる。
（実施形態１３）本実施形態は、図２３に示すように、
図１１に示した実施形態６の構成に対してｐ側電極６を
線状ではなく主チップ面のほぼ全面を覆う金属膜により
面状に形成し、さらにｎ側電極７を主チップ面の一方の
対角線の両端部に設けた構成としてある。図示例ではｐ
形半導体層５の表面から基板２に跨る部位を絶縁膜１７
で覆ってあり、ｐ側電極６およびｎ側電極７の各給電部
１５，１６はそれぞれ絶縁膜１７に形成した窓孔１８を
通して露出させている。また、実装基板８に設けた導電
体１０に給電部１５，１６を電気的に接続するために、
半田または金のような金属のバンプ１９を設けている。
また、実装基板８における合成樹脂の絶縁層８ａに金属
のダイ２０を挿入し、ＬＥＤチップ１とダイ２０との間
の充填材１１として熱伝導性の良好な接着剤を用いてい
る。この構成によって、ＬＥＤチップ１からの放熱性を
良好にしている。なお、バンプ１９を設ける代わりに導
電性接着剤によってｐ側電極６およびｎ側電極７を導電
体１０に接続してもよい。本実施形態の構成によっても
上述した他の構成と同様にｐ側電極６とｎ側電極７との
間の電流経路が従来構成よりも多いから、発光面の輝度
の均一性を向上させることができる。Incidentally, the shapes of the p-side electrode 6 and the n-side electrode 7 are not limited to a dot shape, and the p-side electrode 6 and the n-side electrode 7 may be formed in a shape that divides the main chip surface into a plurality of regions, similarly to the ninth aspect. A configuration in which the side electrode 6 is formed and the n-side electrode 7 is arranged in each divided region may be adopted. For example, as shown in FIG.
The outer periphery of the p-side electrode 6 is formed into a regular hexagon, and the p-side electrode 6 is also formed on three diagonal lines to form six regions on the main chip surface. The electrode 7 may be arranged. In this configuration, the p-side electrode 6
And the n-side electrode 7 have a line symmetry having six lines of symmetry and a rotational symmetry of six times. In the configuration of the present embodiment, in which the arrangement pattern of the p-side electrode 6 and the n-side electrode 7 is higher in symmetry than in the configurations shown in FIGS. The brightness uniformity on the surface is higher.
(Embodiment 13) In this embodiment, as shown in FIG.
In contrast to the configuration of the sixth embodiment shown in FIG. 11, the p-side electrode 6 is not linear but is formed in a planar shape with a metal film covering substantially the entire surface of the main chip, and the n-side electrode 7 is formed on one side of the main chip surface. Are provided at both ends of the diagonal line. In the example shown, p
A portion extending from the surface of the semiconductor layer 5 to the substrate 2 is covered with the insulating film 17.
The power supply portions 15 and 16 of the p-side electrode 6 and the n-side electrode 7 are exposed through window holes 18 formed in the insulating film 17, respectively. Further, in order to electrically connect the power supply units 15 and 16 to the conductor 10 provided on the mounting substrate 8,
A bump 19 made of metal such as solder or gold is provided.
Further, a metal die 20 is inserted into the synthetic resin insulating layer 8a of the mounting substrate 8, and an adhesive having good thermal conductivity is used as the filler 11 between the LED chip 1 and the die 20. With this configuration, the heat radiation from the LED chip 1 is improved. Note that the p-side electrode 6 and the n-side electrode 7 may be connected to the conductor 10 by a conductive adhesive instead of providing the bump 19. According to the configuration of the present embodiment, similarly to the other configurations described above, the current path between the p-side electrode 6 and the n-side electrode 7 is larger than that of the conventional configuration, so that the uniformity of the luminance of the light emitting surface can be improved. it can.
【００５５】上述した実施形態のうちｐ側電極６とｎ側
電極７との少なくとも一方が複数の給電部１５，１６を
備えるもの（つまり、複数個のｐ側電極６あるいは複数
個のｎ側電極７が独立して設けられているもの）では、
発光面の輝度分布に偏りを少なくするように個々の給電
部１５，１６の間で電流を制御することにより、発光面
における輝度の均一性を一層向上させることが可能であ
る。In the above-described embodiment, at least one of the p-side electrode 6 and the n-side electrode 7 includes a plurality of power supply portions 15 and 16 (that is, a plurality of p-side electrodes 6 or a plurality of n-side electrodes 7). 7 is provided independently)
By controlling the current between the individual power supply units 15 and 16 so as to reduce the bias in the luminance distribution on the light emitting surface, it is possible to further improve the uniformity of the luminance on the light emitting surface.
【００５６】[0056]
【発明の効果】請求項１の発明は、基板上に形成された
ｐ形半導体層およびｎ形半導体層と、ｐ形半導体層およ
びｎ形半導体層において基板の反対側である主チップ面
にそれぞれ接続されたｐ側電極およびｎ側電極とを備
え、前記主チップ面内においてｐ側電極およびｎ側電極
の少なくとも一部がそれぞれ互いに並行配置され、ｐ側
電極およびｎ側電極において並行配置された部位を横切
る方向ではｐ側電極とｎ側電極とが交互に配列されてい
るものであり、従来構成に比較するとｐ側電極とｎ側電
極との間で対向する部分が多くなるとともに等距離にな
る部分が多くなるから、従来構成に比較して主チップ面
での電流密度の分布に偏りが少なくなり、結果的に発光
面の輝度の均斉度が高くなる。According to the present invention, the p-type semiconductor layer and the n-type semiconductor layer formed on the substrate and the main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer are respectively provided. A p-side electrode and an n-side electrode connected to each other, and at least a part of the p-side electrode and the n-side electrode are respectively arranged in parallel in the main chip surface, and are arranged in parallel in the p-side electrode and the n-side electrode. In the direction crossing the site, the p-side electrode and the n-side electrode are alternately arranged. Compared with the conventional configuration, the opposing portions between the p-side electrode and the n-side electrode are increased and the distance is equal. Since the number of parts increases, the bias in the distribution of current density on the main chip surface is reduced as compared with the conventional configuration, and as a result, the uniformity of luminance on the light emitting surface is increased.
【００５７】請求項２の発明は、請求項１の発明におい
て、前記ｐ側電極および前記ｎ側電極において、並行配
置された部位が等間隔になるように配列されているの
で、ｐ側電極とｎ側電極との間で等距離になる部分が多
いことにより、発光面の輝度の均一性をより向上させる
ことができる。According to a second aspect of the present invention, in the first aspect of the present invention, in the p-side electrode and the n-side electrode, portions arranged in parallel are arranged so as to be at equal intervals. Since there are many portions that are equidistant from the n-side electrode, the uniformity of luminance on the light emitting surface can be further improved.
【００５８】請求項３の発明は、請求項１の発明におい
て、前記ｐ側電極と前記ｎ側電極との少なくとも一方に
ついては、並行配置された部位が主チップ面上では電気
的に接続されていないものであり、主チップ面内におい
てｐ側電極とｎ側電極とが並行していない部分の割合が
少なく、主チップ面での電流密度の分布の偏りが少なく
なり発光面内における輝度の均一性に優れる。According to a third aspect of the present invention, in the first aspect of the present invention, at least one of the p-side electrode and the n-side electrode is electrically connected to a portion arranged in parallel on the main chip surface. The ratio of the portion where the p-side electrode and the n-side electrode are not parallel in the main chip surface is small, the bias of the current density distribution on the main chip surface is reduced, and the luminance is uniform in the light emitting surface. Excellent in nature.
【００５９】請求項４の発明は、請求項１の発明におい
て、前記ｐ側電極および前記ｎ側電極において、並行配
置された部位を横切る方向にそれぞれ分岐しかつ互いに
並行する複数の枝部が形成されているものであり、ｐ側
電極とｎ側電極との距離が枝部によって近距離になり、
しかも互いに対向する部位が多くなるから、発光面内に
おける輝度の均一性に優れる。According to a fourth aspect of the present invention, in the first aspect of the present invention, the p-side electrode and the n-side electrode are formed with a plurality of branch portions which are respectively branched in a direction crossing the portions arranged in parallel and parallel to each other. The distance between the p-side electrode and the n-side electrode becomes short due to the branch,
In addition, since the number of portions facing each other increases, the brightness uniformity in the light emitting surface is excellent.
【００６０】請求項５の発明は、請求項１の発明におい
て、前記主チップ面内において複数のｐ側電極およびｎ
側電極の少なくとも一部がそれぞれ互いに並行配置され
る渦巻き状に延長され、渦巻き状に形成される部位の中
心から外側に向かってｐ側電極およびｎ側電極を横切る
方向ではｐ側電極とｎ側電極とが交互に配列されている
ものであり、主チップ面の全体にｐ側電極とｎ側電極と
の対向する部分を形成することができ、発光面の輝度の
均一性が高くなる。According to a fifth aspect of the present invention, in the first aspect, a plurality of p-side electrodes and n
At least a part of the side electrode is extended in a spiral shape arranged in parallel with each other, and the p-side electrode and the n-side electrode extend in a direction crossing the p-side electrode and the n-side electrode from the center of the spirally formed portion to the outside. Since the electrodes and the electrodes are alternately arranged, a portion where the p-side electrode and the n-side electrode face each other can be formed on the entire main chip surface, and the uniformity of the luminance of the light emitting surface is improved.
【００６１】請求項６の発明は、基板上に形成されたｐ
形半導体層およびｎ形半導体層と、ｐ形半導体層および
ｎ形半導体層において基板の反対側である主チップ面に
それぞれ接続された複数個ずつのｐ側電極およびｎ側電
極とを備えるものであり、従来構成に比較すると、主チ
ップ面内でｐ側電極とｎ側電極との電流経路を分散させ
ることができ、発光面内における輝度の均一性に優れ
る。According to a sixth aspect of the present invention, there is provided a semiconductor device comprising:
A p-type semiconductor layer and an n-type semiconductor layer, and a plurality of p-side and n-side electrodes respectively connected to the main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer. In addition, as compared with the conventional configuration, the current paths of the p-side electrode and the n-side electrode can be dispersed in the main chip surface, and the luminance uniformity in the light emitting surface is excellent.
【００６２】請求項７の発明は、請求項６の発明におい
て、前記ｐ側電極および前記ｎ側電極のうち異種導電形
の半導体層に接続された電極間の距離を、同種導電形の
半導体層に接続された電極間の距離よりも小さくしたも
のであり、同種導電形の半導体層に接続された電極間が
近接しないことにより、発光面における輝度の均一性に
優れる。According to a seventh aspect of the present invention, in the invention of the sixth aspect, the distance between the p-side electrode and the n-side electrode connected to the semiconductor layer of a different conductivity type is set to be the same as that of the semiconductor layer of the same conductivity type. The distance between the electrodes connected to the semiconductor layer is smaller than the distance between the electrodes connected to the same type, and the uniformity of the luminance on the light emitting surface is excellent because the electrodes connected to the semiconductor layer of the same conductivity type are not close to each other.
【００６３】請求項８の発明は、請求項７の発明におい
て、前記ｐ側電極と前記ｎ側電極のうち異種導電形の半
導体層に接続された電極間が等間隔に配列されているも
のであり、ｐ側電極とｎ側電極との間に流れる電流の電
流密度の偏りが少なくなり、発光面の輝度の均一性を高
めることができる。According to an eighth aspect of the present invention, in the seventh aspect of the present invention, between the p-side electrode and the n-side electrode, electrodes connected to semiconductor layers of different conductivity types are arranged at equal intervals. In addition, the bias of the current density of the current flowing between the p-side electrode and the n-side electrode is reduced, and the uniformity of the luminance of the light emitting surface can be improved.
【００６４】請求項９の発明は、基板上に形成されたｐ
形半導体層およびｎ形半導体層と、ｐ形半導体層および
ｎ形半導体層において基板の反対側である主チップ面に
それぞれ接続されたｐ側電極およびｎ側電極とを備え、
前記主チップ面がｐ側電極およびｎ側電極との一方によ
り複数の領域に分割され、各領域内にそれぞれ他方が配
置されるものであり、主チップ面においてｐ側電極とｎ
側電極との対向部分が従来構成よりも多くなるから、発
光面の輝度の均一性に優れる。According to a ninth aspect of the present invention, there is provided a semiconductor device comprising:
A p-type semiconductor layer and an n-type semiconductor layer, and a p-side electrode and an n-side electrode connected to a main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer, respectively.
The main chip surface is divided into a plurality of regions by one of a p-side electrode and an n-side electrode, and the other is disposed in each region.
Since the number of portions facing the side electrodes is larger than in the conventional configuration, the uniformity of the luminance of the light emitting surface is excellent.
【００６５】請求項１０の発明は、請求項９の発明にお
いて、前記ｐ側電極と前記ｎ側電極とのうちの前記一方
が前記各領域をそれぞれ全周に亘って囲むように形成さ
れるものであり、ｐ側電極とｎ側電極との間の電流密度
の分布の偏りが少なくなり、発光面の輝度の均一性が高
くなる。According to a tenth aspect, in the ninth aspect, the one of the p-side electrode and the n-side electrode is formed so as to surround each of the regions over the entire circumference. The bias in the distribution of the current density between the p-side electrode and the n-side electrode is reduced, and the uniformity of the luminance of the light emitting surface is increased.
【００６６】請求項１１の発明は、請求項９の発明にお
いて、前記ｐ側電極と前記ｎ側電極とのうちの前記他方
が前記一方に設けた線状部分に並行配置される線状の部
分を備えるものであり、ｐ側電極とｎ側電極との対向部
分が多いから、発光面における輝度の均一性に優れる。According to an eleventh aspect of the present invention, in the ninth aspect of the present invention, the linear portion in which the other of the p-side electrode and the n-side electrode is arranged in parallel with the linear portion provided on the one side. Since the p-side electrode and the n-side electrode have many opposing portions, the uniformity of luminance on the light emitting surface is excellent.
【００６７】請求項１２の発明は、基板上に形成された
ｐ形半導体層およびｎ形半導体層と、ｐ形半導体層およ
びｎ形半導体層において基板の反対側である主チップ面
にそれぞれ接続されたｐ側電極およびｎ側電極とを備
え、ｐ側電極およびｎ側電極との一方が主チップ面の中
心部に配置され、前記一方を囲む形で他方が配置されて
いるものであり、従来構成に比較すると、主チップ面に
おいてｐ側電極とｎ側電極との対向部分が多くなるか
ら、発光面の輝度の均一性に優れる。According to a twelfth aspect of the present invention, a p-type semiconductor layer and an n-type semiconductor layer formed on a substrate are respectively connected to a main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer. A p-side electrode and an n-side electrode, one of the p-side electrode and the n-side electrode is disposed at the center of the main chip surface, and the other is disposed so as to surround the one. Compared to the configuration, the number of opposing portions of the p-side electrode and the n-side electrode on the main chip surface is increased, so that the uniformity of the luminance of the light emitting surface is excellent.
【００６８】請求項１３の発明は、請求項１２の発明に
おいて、前記ｐ側電極と前記ｎ側電極とが交互に入れ子
状に配列されているものであり、主チップ面内において
ｐ側電極とｎ側電極との対向部分が従来構成よりも多い
から、発光面の輝度の均一性が高くなる。According to a thirteenth aspect, in the twelfth aspect, the p-side electrodes and the n-side electrodes are alternately arranged in a nested manner, and the p-side electrodes and the n-side electrodes are arranged within the main chip plane. Since the number of portions facing the n-side electrode is larger than in the conventional configuration, the uniformity of luminance on the light emitting surface is improved.
【００６９】請求項１４の発明は、請求項１３の発明に
おいて、前記ｐ側電極と前記ｎ側電極とが等間隔になる
ように配列されているものであり、ｐ側電極とｎ側電極
との間の電極間距離の等しい部分が多くなることによっ
て、電流密度の分布の偏りが少なくなり、発光面の輝度
の均一性に優れる。According to a fourteenth aspect, in the thirteenth aspect, the p-side electrode and the n-side electrode are arranged at equal intervals, and the p-side electrode and the n-side electrode are connected to each other. By increasing the portion where the distance between the electrodes is equal, the bias of the current density distribution is reduced, and the uniformity of the luminance of the light emitting surface is excellent.
【００７０】請求項１５の発明は、請求項１３または請
求項１４の発明において、前記ｐ側電極と前記ｎ側電極
とが同心円状に配列されているものであり、ｐ側電極と
ｎ側電極との電極間の距離を主チップ面の全体でほぼ等
しくすることが可能になり、発光面における輝度の均一
性に優れる。According to a fifteenth aspect, in the thirteenth or fourteenth aspect, the p-side electrode and the n-side electrode are arranged concentrically, and the p-side electrode and the n-side electrode Can be made substantially equal over the entire main chip surface, and the light emitting surface is excellent in uniformity of luminance.
【００７１】請求項１６の発明は、請求項１３または請
求項１４の発明において、前記ｐ側電極と前記ｎ側電極
とを主チップ面の外周形状の相似形状としたものであ
り、主チップ面の外周縁付近まで電極を形成することが
でき、主チップ面の外周縁付近と中央付近との輝度差を
少なくすることができる。According to a sixteenth aspect, in the thirteenth or fourteenth aspect, the p-side electrode and the n-side electrode have a similar shape to the outer peripheral shape of the main chip surface. Can be formed up to the vicinity of the outer peripheral edge of the main chip surface, and the difference in luminance between the vicinity of the outer peripheral edge of the main chip surface and the vicinity of the center can be reduced.
【００７２】請求項１７の発明は、請求項１または請求
項６または請求項９または請求項１２の発明において、
前記ｎ側電極と前記ｐ側電極との配置パターンが、前記
主チップ面内で線対称性を有するものであり、電極の配
置に対称性が与えられているから、電流密度の分布の偏
りを低減することができ、発光面における輝度の均一性
に優れる。The invention of claim 17 is the invention according to claim 1 or claim 6 or claim 9 or claim 12,
The arrangement pattern of the n-side electrode and the p-side electrode has a line symmetry in the plane of the main chip, and the symmetry is given to the arrangement of the electrodes. The luminance can be reduced, and the luminance uniformity on the light emitting surface is excellent.
【００７３】請求項１８の発明は、請求項１または請求
項６または請求項９または請求項１２の発明において、
前記ｎ側電極と前記ｐ側電極との配置パターンが、前記
主チップ面内で２回以上の回転対称性を有するものであ
り、電極の配置に対称性が与えられているから、電流密
度の分布の偏りを低減することができ、発光面における
輝度の均一性に優れる。The invention of claim 18 is the invention according to claim 1 or claim 6 or claim 9 or claim 12,
The arrangement pattern of the n-side electrode and the p-side electrode has a rotational symmetry of two or more times in the plane of the main chip, and the symmetry is given to the arrangement of the electrodes. The distribution bias can be reduced, and the luminance uniformity on the light emitting surface is excellent.
【００７４】請求項１９の発明は、請求項１または請求
項６または請求項９または請求項１２の発明において、
前記ｎ側電極と前記ｐ側電極との配置パターンが、前記
主チップ面内で２回以上の回転対称性を有するととも
に、２本以上の対称線に関して線対称性を有するもので
あり、電極の配置に対称性が与えられているから、電流
密度の分布の偏りを低減することができ、発光面におけ
る輝度の均一性に優れる。The invention of claim 19 is the invention according to claim 1 or claim 6 or claim 9 or claim 12,
The arrangement pattern of the n-side electrode and the p-side electrode has rotational symmetry two or more times in the main chip plane and has line symmetry with respect to two or more lines of symmetry. Since the arrangement is symmetrical, the bias of the current density distribution can be reduced, and the luminance uniformity on the light emitting surface is excellent.
【００７５】請求項２０の発明は、請求項１または請求
項６または請求項９の発明において、前記ｎ側電極と前
記ｐ側電極とにそれぞれ給電する給電部を設け、ｎ側電
極とｐ側電極との少なくとも一方の給電部を複数個設け
たものであり、発光面の輝度分布に偏りを少なくするよ
うに個々の給電部の間で電流を制御することにより、発
光面における輝度の均一性を向上させることができる。According to a twentieth aspect of the present invention, in the first, sixth, or ninth aspect of the present invention, a power supply portion is provided for supplying power to the n-side electrode and the p-side electrode, respectively. A plurality of electrodes and at least one power supply unit are provided, and by controlling the current between the individual power supply units so as to reduce the bias in the luminance distribution of the light emitting surface, the uniformity of the luminance on the light emitting surface is obtained. Can be improved.
【図１】本発明の実施形態１を示す概略平面図である。FIG. 1 is a schematic plan view showing a first embodiment of the present invention.
【図２】同上の他の構成例を示す概略平面図である。FIG. 2 is a schematic plan view showing another configuration example of the above.
【図３】同上の別の構成例を示す概略平面図である。FIG. 3 is a schematic plan view showing another configuration example of the above.
【図４】本発明の実施形態２を示す概略平面図である。FIG. 4 is a schematic plan view showing Embodiment 2 of the present invention.
【図５】同上の他の構成例を示す概略平面図である。FIG. 5 is a schematic plan view showing another configuration example of the above.
【図６】本発明の実施形態３を示す概略平面図である。FIG. 6 is a schematic plan view showing Embodiment 3 of the present invention.
【図７】本発明の実施形態４を示す概略平面図である。FIG. 7 is a schematic plan view showing Embodiment 4 of the present invention.
【図８】同上の他の構成例を示す概略平面図である。FIG. 8 is a schematic plan view showing another configuration example of the above.
【図９】本発明の実施形態５を示す概略平面図である。FIG. 9 is a schematic plan view showing Embodiment 5 of the present invention.
【図１０】同上の他の構成例を示す概略平面図である。FIG. 10 is a schematic plan view showing another configuration example of the above.
【図１１】本発明の実施形態６を示す概略平面図であ
る。FIG. 11 is a schematic plan view showing Embodiment 6 of the present invention.
【図１２】同上の他の構成例を示す概略平面図である。FIG. 12 is a schematic plan view showing another configuration example of the above.
【図１３】本発明の実施形態７を示す概略平面図であ
る。FIG. 13 is a schematic plan view showing Embodiment 7 of the present invention.
【図１４】本発明の実施形態８を示す概略平面図であ
る。FIG. 14 is a schematic plan view showing Embodiment 8 of the present invention.
【図１５】同上の他の構成例を示す概略平面図である。FIG. 15 is a schematic plan view showing another configuration example of the above.
【図１６】本発明の実施形態９を示す概略平面図であ
る。FIG. 16 is a schematic plan view showing Embodiment 9 of the present invention.
【図１７】本発明の実施形態１０を示す概略平面図であ
る。FIG. 17 is a schematic plan view showing Embodiment 10 of the present invention.
【図１８】同上の他の構成例を示す概略平面図である。FIG. 18 is a schematic plan view showing another configuration example of the above.
【図１９】同上の別の構成例を示す概略平面図である。FIG. 19 is a schematic plan view showing another configuration example of the above.
【図２０】本発明の実施形態１１を示す概略平面図であ
る。FIG. 20 is a schematic plan view showing Embodiment 11 of the present invention.
【図２１】本発明の実施形態１２を示す概略平面図であ
る。FIG. 21 is a schematic plan view showing a twelfth embodiment of the present invention.
【図２２】同上の他の構成例を示す概略平面図である。FIG. 22 is a schematic plan view showing another configuration example of the above.
【図２３】本発明の実施形態１３を示し、（ａ）は概略
平面図、（ｂ）は断面図である。FIG. 23 shows Embodiment 13 of the present invention, in which (a) is a schematic plan view and (b) is a cross-sectional view.
【図２４】本発明に係るＬＥＤチップの使用例を示す断
面図である。FIG. 24 is a sectional view showing a usage example of the LED chip according to the present invention.
【図２５】従来構成を示し、（ａ）は平面図、（ｂ）は
断面図である。25A and 25B show a conventional configuration, in which FIG. 25A is a plan view and FIG. 25B is a cross-sectional view.
【図２６】従来構成を示すフェースダウン状態での実装
状態を示す断面図である。FIG. 26 is a cross-sectional view showing a mounting state in a face-down state showing a conventional configuration.
１ ＬＥＤチップ ２ 基板 ３ ｎ形半導体層 ４ 発光層 ５ ｐ形半導体層 ６ ｐ側電極 ７ ｎ側電極 １３，１４ 導電部 １５，１６ 給電部 REFERENCE SIGNS LIST 1 LED chip 2 substrate 3 n-type semiconductor layer 4 light-emitting layer 5 p-type semiconductor layer 6 p-side electrode 7 n-side electrode 13, 14 conductive part 15, 16 power supply part
───────────────────────────────────────────────────── フロントページの続き (72)発明者 木村 秀吉 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 塩浜 英二 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 葛原 一功 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 高見 茂成 大阪府門真市大字門真1048番地松下電工株 式会社内 Ｆターム(参考） 5F041 AA03 AA05 CA12 CA40 CA93 FF11 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideyoshi Kimura 1048 Kazumasa Kadoma, Osaka Pref.Matsushita Electric Works, Ltd. 72) Inventor Kazunori Kuzuhara 1048 Kadoma Kadoma, Kadoma-shi, Osaka Pref. Matsushita Electric Works Co., Ltd. AA05 CA12 CA40 CA93 FF11
Claims (20)
ｎ形半導体層と、ｐ形半導体層およびｎ形半導体層にお
いて基板の反対側である主チップ面にそれぞれ接続され
たｐ側電極およびｎ側電極とを備え、前記主チップ面内
においてｐ側電極およびｎ側電極の少なくとも一部がそ
れぞれ互いに並行配置され、ｐ側電極およびｎ側電極に
おいて並行配置された部位を横切る方向ではｐ側電極と
ｎ側電極とが交互に配列されていることを特徴とするＬ
ＥＤチップ。1. A semiconductor device comprising: a p-type semiconductor layer and an n-type semiconductor layer formed on a substrate; a p-side electrode connected to a main chip surface of the p-type semiconductor layer and the n-type semiconductor layer opposite to the substrate; an n-side electrode, at least a part of the p-side electrode and at least a part of the n-side electrode are respectively arranged in parallel in the plane of the main chip, and the p-side electrode and the n-side electrode in the direction traversing the portions arranged in parallel with each other. Characterized in that the electrodes and the n-side electrodes are alternately arranged.
ED chip.
て、並行配置された部位が等間隔になるように配列され
ていることを特徴とする請求項１記載のＬＥＤチップ。2. The LED chip according to claim 1, wherein, in the p-side electrode and the n-side electrode, portions arranged in parallel are arranged at equal intervals.
とも一方については、並行配置された部位が主チップ面
上では電気的に接続されていないことを特徴とする請求
項１記載のＬＥＤチップ。3. The LED according to claim 1, wherein at least one of the p-side electrode and the n-side electrode has a portion arranged in parallel and not electrically connected on the main chip surface. Chips.
て、並行配置された部位を横切る方向にそれぞれ分岐し
かつ互いに並行する複数の枝部が形成されていることを
特徴とする請求項１記載のＬＥＤチップ。4. The p-side electrode and the n-side electrode, wherein a plurality of branch portions are formed, each branching in a direction crossing a portion arranged in parallel and being parallel to each other. LED chip.
極およびｎ側電極の少なくとも一部がそれぞれ互いに並
行配置される渦巻き状に延長され、渦巻き状に形成され
る部位の中心から外側に向かってｐ側電極およびｎ側電
極を横切る方向ではｐ側電極とｎ側電極とが交互に配列
されていることを特徴とする請求項１記載のＬＥＤチッ
プ。5. A plurality of p-side electrodes and at least a part of n-side electrodes are spirally extended in parallel with each other in the main chip surface, and extend outward from the center of the spirally formed portion. The LED chip according to claim 1, wherein the p-side electrode and the n-side electrode are alternately arranged in a direction crossing the p-side electrode and the n-side electrode.
ｎ形半導体層と、ｐ形半導体層およびｎ形半導体層にお
いて基板の反対側である主チップ面にそれぞれ接続され
た複数個ずつのｐ側電極およびｎ側電極とを備えること
を特徴とするＬＥＤチップ。6. A p-type semiconductor layer and an n-type semiconductor layer formed on a substrate, and a plurality of p-type semiconductor layers and n-type semiconductor layers connected to a main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer, respectively. An LED chip comprising a p-side electrode and an n-side electrode.
異種導電形の半導体層に接続された電極間の距離を、同
種導電形の半導体層に接続された電極間の距離よりも小
さくしたことを特徴とする請求項６記載のＬＥＤチッ
プ。7. A distance between electrodes connected to semiconductor layers of different conductivity types of the p-side electrode and the n-side electrode is made smaller than a distance between electrodes connected to semiconductor layers of the same conductivity type. The LED chip according to claim 6, wherein:
導電形の半導体層に接続された電極間が等間隔に配列さ
れていることを特徴とする請求項７記載のＬＥＤチッ
プ。8. The LED chip according to claim 7, wherein between the p-side electrode and the n-side electrode, electrodes connected to semiconductor layers of different conductivity types are arranged at equal intervals.
ｎ形半導体層と、ｐ形半導体層およびｎ形半導体層にお
いて基板の反対側である主チップ面にそれぞれ接続され
たｐ側電極およびｎ側電極とを備え、前記主チップ面が
ｐ側電極およびｎ側電極との一方により複数の領域に分
割され、各領域内にそれぞれ他方が配置されることを特
徴とするＬＥＤチップ。9. A p-type semiconductor layer and an n-type semiconductor layer formed on a substrate, a p-side electrode connected to a main chip surface of the p-type semiconductor layer and the n-type semiconductor layer opposite to the substrate, and An LED chip comprising an n-side electrode, wherein the main chip surface is divided into a plurality of regions by one of a p-side electrode and an n-side electrode, and the other is disposed in each region.
の前記一方が前記各領域をそれぞれ全周に亘って囲むよ
うに形成されることを特徴とする請求項９記載のＬＥＤ
チップ。10. The LED according to claim 9, wherein the one of the p-side electrode and the n-side electrode is formed so as to surround each of the regions over the entire circumference.
Chips.
の前記他方が前記一方に設けた線状部分に並行配置され
る線状の部分を備えることを特徴とする請求項９記載の
ＬＥＤチップ。11. The device according to claim 9, wherein the other of the p-side electrode and the n-side electrode has a linear portion arranged in parallel with a linear portion provided on the one side. LED chip.
びｎ形半導体層と、ｐ形半導体層およびｎ形半導体層に
おいて基板の反対側である主チップ面にそれぞれ接続さ
れたｐ側電極およびｎ側電極とを備え、ｐ側電極および
ｎ側電極との一方が主チップ面の中心部に配置され、前
記一方の周囲を囲む形で他方が配置されていることを特
徴とするＬＥＤチップ。12. A p-type semiconductor layer and an n-type semiconductor layer formed on a substrate, a p-side electrode connected to a main chip surface opposite to the substrate in the p-type semiconductor layer and the n-type semiconductor layer, and An LED chip comprising: an n-side electrode; one of a p-side electrode and an n-side electrode is disposed at a central portion of a main chip surface, and the other is disposed so as to surround the periphery of the one.
に入れ子状に配列されていることを特徴とする請求項１
２記載のＬＥＤチップ。13. The device according to claim 1, wherein the p-side electrodes and the n-side electrodes are alternately nested.
2. The LED chip according to 2.
隔になるように配列されていることを特徴とする請求項
１３記載のＬＥＤチップ。14. The LED chip according to claim 13, wherein said p-side electrode and said n-side electrode are arranged at equal intervals.
円状に配列されていることを特徴とする請求項１３また
は請求項１４記載のＬＥＤチップ。15. The LED chip according to claim 13, wherein the p-side electrode and the n-side electrode are arranged concentrically.
ップ面の外周形状の相似形状であることを特徴とする請
求項１３または請求項１４記載のＬＥＤチップ。16. The LED chip according to claim 13, wherein the p-side electrode and the n-side electrode have a similar shape to the outer peripheral shape of the main chip surface.
パターンが、前記主チップ面内で線対称性を有すること
を特徴とする請求項１または請求項６または請求項９ま
たは請求項１２記載のＬＥＤチップ。17. The arrangement pattern of the n-side electrode and the p-side electrode has a line symmetry in the plane of the main chip. 13. The LED chip according to item 12.
パターンが、前記主チップ面内で２回以上の回転対称性
を有することを特徴とする請求項１または請求項６また
は請求項９または請求項１２記載のＬＥＤチップ。18. The arrangement pattern according to claim 1, wherein the arrangement pattern of the n-side electrode and the p-side electrode has a rotational symmetry of two or more times in the plane of the main chip. The LED chip according to claim 9 or 12.
パターンが、前記主チップ面内で２回以上の回転対称性
を有するとともに、２本以上の対称線に関して線対称性
を有することを特徴とする請求項１または請求項６また
は請求項９または請求項１２記載のＬＥＤチップ。19. An arrangement pattern of the n-side electrode and the p-side electrode has rotational symmetry at least twice in the plane of the main chip and has line symmetry with respect to two or more symmetry lines. The LED chip according to claim 1, claim 6, claim 9, or claim 12.
ぞれ給電する給電部を設け、ｎ側電極とｐ側電極との少
なくとも一方の給電部を複数個設けたことを特徴とする
請求項１または請求項６または請求項９記載のＬＥＤチ
ップ。20. A power supply unit for supplying power to each of the n-side electrode and the p-side electrode, and a plurality of power supply units for at least one of the n-side electrode and the p-side electrode are provided. The LED chip according to claim 1 or claim 6 or claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001124555A JP2002319704A (en) | 2001-04-23 | 2001-04-23 | Led chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001124555A JP2002319704A (en) | 2001-04-23 | 2001-04-23 | Led chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002319704A true JP2002319704A (en) | 2002-10-31 |
Family
ID=18973921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001124555A Pending JP2002319704A (en) | 2001-04-23 | 2001-04-23 | Led chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002319704A (en) |
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