JP2002299163A - Variable capacitance element - Google Patents
Variable capacitance elementInfo
- Publication number
- JP2002299163A JP2002299163A JP2001102710A JP2001102710A JP2002299163A JP 2002299163 A JP2002299163 A JP 2002299163A JP 2001102710 A JP2001102710 A JP 2001102710A JP 2001102710 A JP2001102710 A JP 2001102710A JP 2002299163 A JP2002299163 A JP 2002299163A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin film
- conductor layer
- thin
- upper electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、薄膜誘電体層を有
する可変容量素子に関し、より詳細には高周波素子用キ
ャパシタ等に応用することができ、電圧印加によりその
容量を大きく変化させることが可能なチタン酸ストロン
チウムバリウム誘電体材料を用いた薄膜可変容量素子に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance element having a thin film dielectric layer, and more particularly, to a variable capacitance element having a thin-film dielectric layer, which can be applied to a capacitor for a high-frequency element, and whose capacitance can be largely changed by applying a voltage. The present invention relates to a thin film variable capacitance element using a novel strontium barium titanate dielectric material.
【０００２】[0002]
【従来の技術】従来、常誘電体であるチタン酸ストロン
チウム（ＳｒＴｉＯ3）薄膜（A.Walkenhorst et al.,Ap
pl.Phys.Lett.60(1992)1744）や、強誘電体であるチタ
ン酸ストロンチウムバリウム（Ｂａ，Ｓｒ）ＴｉＯ3薄
膜（Cem Bascri et.al.,J.Appl.Phys 82(1997)2497）に
ついて、電圧印加による非線形な誘電率変化が報告され
ている。また、これらチタン酸ストロンチウムやチタン
酸ストロンチウムバリウム等のペロブスカイト構造強誘
電体酸化物薄膜を用いた薄膜コンデンサが提案されてい
る（特開平１１−２６００６６７号など）。2. Description of the Related Art Conventionally, a strontium titanate (SrTiO 3 ) thin film (A. Walkenhorst et al., Ap.
60 (1992) 1744) and strontium barium titanate (Ba, Sr) TiO 3 thin film as a ferroelectric (Cem Bascri et.al., J. Appl. Phys 82 (1997) 2497). As for, a non-linear change in dielectric constant due to voltage application has been reported. Further, a thin film capacitor using a ferroelectric oxide thin film having a perovskite structure such as strontium titanate or strontium barium titanate has been proposed (Japanese Patent Application Laid-Open No. 11-2600667).
【０００３】これらの容量可変型の薄膜コンデンサは、
図2に示すように、下部電極層、誘電体層、上部電極層
とを順次被着形成していた。[0003] These variable-capacity thin-film capacitors are:
As shown in FIG. 2, a lower electrode layer, a dielectric layer, and an upper electrode layer were sequentially formed.
【０００４】まず、支持基板１１上に下部電極層１２と
なる導体層を被着形成した後、パターン加工を施す。次
に、下部電極層１２上に誘電体膜１３を形成する。その
後、誘電体膜１３上に上部電極層１４となる導体層を形
成した後、パターン加工を施していた。[0004] First, after a conductor layer to be the lower electrode layer 12 is formed on the support substrate 11 by patterning, pattern processing is performed. Next, a dielectric film 13 is formed on the lower electrode layer 12. Thereafter, a conductor layer to be the upper electrode layer 14 is formed on the dielectric film 13 and then patterned.
【０００５】[0005]
【発明が解決しようとする課題】高周波領域で動作する
薄膜コンデンサにおいて、各電極層の損失を低減させる
ことが重要である。このためには下部電極層１２及び上
部電極層１４の厚みを厚くすることが必要になる。しか
し、実際には、下部電極層１２の厚みを増加させること
は困難である。In a thin film capacitor operating in a high frequency range, it is important to reduce the loss of each electrode layer. For this purpose, it is necessary to increase the thickness of the lower electrode layer 12 and the upper electrode layer 14. However, it is actually difficult to increase the thickness of the lower electrode layer 12.
【０００６】なぜなら、下部電極層１２の厚みを増加さ
せると、下部電極層１２と誘電体層１３の被覆性が悪く
なる。また、基板１１と下部電極層１２との間で剥離が
発生する。さらに、誘電体層１３と下部電極層１２との
間で剥離が発生する。これらは、下部電極層１２の厚み
を厚くすることにより、基板１１や誘電体層１３の熱膨
張係数の差に起因する応力が大きくなるためである。[0006] When the thickness of the lower electrode layer 12 is increased, the coverage between the lower electrode layer 12 and the dielectric layer 13 is deteriorated. Further, separation occurs between the substrate 11 and the lower electrode layer 12. Further, separation occurs between the dielectric layer 13 and the lower electrode layer 12. These are because, by increasing the thickness of the lower electrode layer 12, the stress caused by the difference in the coefficient of thermal expansion between the substrate 11 and the dielectric layer 13 increases.
【０００７】特に、このような可変容量素子では、下部
電極層１２と上部電極層１４との間の誘電体層１３に１
０Ｖ程度の比較的高い容量制御電圧を印加しなくてはな
いことを考慮すると、上述の両電極層１２、１４の厚み
を厚くすることが非常に重要となる。In particular, in such a variable capacitance element, the dielectric layer 13 between the lower electrode layer 12 and the upper electrode layer
Considering that a relatively high capacitance control voltage of about 0 V must be applied, it is very important to increase the thickness of the above-mentioned two electrode layers 12 and 14.
【０００８】また、上述の従来の可変容量型コンデンサ
では、上部電極層１４が下部電極層１２との短絡を防止
するために、誘電体層１３の周囲にエアブリッジ１５を
形成していた。即ち、上部電極層１４の一部が、ボンデ
ィングワイヤのように空中に位置しているため、実際に
マザーボードなどに搭載することは非常に困難であり、
実用に耐え得るものではなかった。In the above-mentioned conventional variable capacitance type capacitor, the air bridge 15 is formed around the dielectric layer 13 in order to prevent the upper electrode layer 14 from short-circuiting with the lower electrode layer 12. That is, since a part of the upper electrode layer 14 is located in the air like a bonding wire, it is very difficult to actually mount it on a motherboard or the like.
It was not practical.
【０００９】本発明は上述の問題点に鑑みて案出された
ものであり、その目的は、誘電体層の剥離が発生するこ
とがなく、しかも、容量上部電極層での低抵抗化が容易
で、且つ誘電体層に比較的高い容量制御電圧を印加して
も耐え得る構造の可変容量素子を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to prevent the dielectric layer from peeling off and to easily reduce the resistance of the capacitor upper electrode layer. Another object of the present invention is to provide a variable capacitance element having a structure that can withstand a relatively high capacitance control voltage applied to a dielectric layer.
【００１０】[0010]
【課題を解決するための手段】本発明は、支持基板上
に、第１薄膜下地導体層と第２薄膜下地導体層とを離間
させて被着形成し、前記第１薄膜下地導体層と第２薄膜
下地導体層とに跨がるように、外部電圧の印加により誘
電率が変化する薄膜誘電体層を被着形成し、前記第１薄
膜下地導体層上に第１上部電極層を被着形成するととも
に、前記第１薄膜下地導体層上に配置された薄膜誘電体
層の一部及び第２薄膜下地導体層上に第２上部電極層を
被着形成したことを特徴とする可変容量素子である。According to the present invention, a first thin-film underlying conductor layer and a second thin-film underlying conductor layer are formed on a supporting substrate at a distance from each other. (2) A thin film dielectric layer whose dielectric constant changes by application of an external voltage is formed so as to straddle the thin film underlying conductor layer, and a first upper electrode layer is formed on the first thin film underlying conductor layer. And a second upper electrode layer formed on a part of the thin film dielectric layer disposed on the first thin film underlying conductor layer and on the second thin film underlying conductor layer. It is.
【００１１】これにより、薄膜誘電体層を挟持する一方
の容量電極は、第１薄膜下地導体層及び第１上部電極層
とで構成される。また、他方の容量電極は、第２薄膜下
地導体層及び第２上部電極層とで構成される。また、誘
電体層の容量発生領域は、第１薄膜下地導体層と第２上
部電極層との対向部分となる。Thus, one capacitor electrode sandwiching the thin-film dielectric layer is composed of the first thin-film base conductor layer and the first upper electrode layer. The other capacitor electrode includes a second thin film base conductor layer and a second upper electrode layer. Further, the capacitance generating region of the dielectric layer is a portion where the first thin film base conductor layer and the second upper electrode layer face each other.
【００１２】また、前記第１薄膜下地導体層及び第２薄
膜下地導体層は、Auを主成分とする材料からなる。尚、
第１上部電極層、第２上部電極層もAuを主成分とする材
料とすることが望ましい。Further, the first thin film base conductor layer and the second thin film base conductor layer are made of a material containing Au as a main component. still,
It is preferable that the first upper electrode layer and the second upper electrode layer are also made of a material containing Au as a main component.
【００１３】さらに、第１薄膜下地導体層及び第２薄膜
下地導体層の厚みｔ１は、第１上部電極層及び第２上部
電極層の厚みｔ２よりも厚いものである。Further, the thickness t1 of the first thin film underlying conductor layer and the second thin film underlying conductor layer is larger than the thickness t2 of the first upper electrode layer and the second upper electrode layer.
【作用】本発明によれば、薄膜誘電体層に対して外部電
圧の印加を印加するとともに、容量成分を抽出する手段
は、第１容量電極及び第２容量電極である。そしていず
れの容量電極は、薄膜下地導体層と上部電極層との積層
構造である。即ち、この容量電極が積層構造であるた
め、容量電極自身の低抵抗化が容易となる。また、容量
電極の厚みを一定にして、薄膜下地導体層の厚みを極小
化できるため、薄膜下地導体層と支持基板との密着性を
向上させることができる。また、薄膜下地導体層と誘電
体層との密着性を維持し、しかも、薄膜誘電体層が薄膜
下地導体層の稜線で段切れが発生することも防止でき
る。According to the present invention, the means for applying the external voltage to the thin film dielectric layer and extracting the capacitance component is the first capacitance electrode and the second capacitance electrode. Each of the capacitor electrodes has a laminated structure of a thin film base conductor layer and an upper electrode layer. That is, since the capacitance electrode has a laminated structure, the resistance of the capacitance electrode itself can be easily reduced. In addition, since the thickness of the capacitor electrode can be kept constant and the thickness of the thin-film underlying conductor layer can be minimized, the adhesion between the thin-film underlying conductor layer and the support substrate can be improved. Further, it is possible to maintain the adhesion between the thin-film underlying conductor layer and the dielectric layer, and to prevent the thin-film dielectric layer from being disconnected at the ridge line of the thin-film underlying conductor layer.
【００１４】また、従来のようにエアブリッジなどを形
成することなく、両容量電極どうしの短絡が防止でき
る。さらに、容量電極が緻密化されているため、バンプ
端子などの形成も容易で、マザーボードにこの素子を実
装する場合でも、容易に実装できる。Further, it is possible to prevent a short circuit between the two capacitance electrodes without forming an air bridge or the like as in the prior art. Further, since the capacitance electrodes are dense, it is easy to form bump terminals and the like, and even when this element is mounted on a motherboard, it can be easily mounted.
【００１５】また、薄膜下地導体層及び上部電極層をAu
を用いることにより、非酸化性金属であるため酸化防止
層の形成が不要となり、一層、容量電極の導体損失を低
減できる。また、薄膜下地導体層と上部電極とを同一金
属材料であるため、両者を積層するにあたり、その密着
性が良好となる。Further, the thin film base conductor layer and the upper electrode layer are made of Au.
By using a non-oxidizing metal, there is no need to form an antioxidant layer, and the conductor loss of the capacitor electrode can be further reduced. Further, since the thin-film base conductor layer and the upper electrode are made of the same metal material, the adhesion between them is improved when they are laminated.
【００１６】[0016]
【発明の実施の形態】以下、本発明の可変容量素子を図
面に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A variable capacitance element according to the present invention will be described below with reference to the drawings.
【００１７】図１は、本発明の可変容量素子の断面構造
を示す断面図である。本発明の可変容量素子は、支持基
板１上に、第１薄膜下地導体層２１と第２薄膜下地導体
層２２と離間して被着形成する。この離間部分を符号x
で示す。そして、第１薄膜下地導体層２１と第２薄膜下
地導体層２２とに跨がるように、外部電圧の印加により
誘電率が変化する薄膜誘電体層３が被着される。さら
に、第１薄膜下地導体層２１上に第１上部電極層４１が
被着形成され、同時に、第１薄膜下地導体層２１上に配
置された薄膜誘電体層３の一部（符号aで示す）及び第
２薄膜下地導体層２２上に第２上部電極層４２が被着形
成されている。FIG. 1 is a sectional view showing a sectional structure of a variable capacitance element according to the present invention. The variable capacitance element according to the present invention is formed on the support substrate 1 with the first thin-film base conductor layer 21 and the second thin-film base conductor layer 22 separated from each other. This separation part is denoted by x
Indicated by Then, the thin film dielectric layer 3 whose dielectric constant changes by application of an external voltage is applied so as to straddle the first thin film underlying conductor layer 21 and the second thin film underlying conductor layer 22. Further, a first upper electrode layer 41 is formed on the first thin-film underlying conductor layer 21 and, at the same time, a portion of the thin-film dielectric layer 3 disposed on the first thin-film underlying conductor layer 21 (indicated by the symbol a). ) And the second upper electrode layer 42 is formed on the second thin film base conductor layer 22.
【００１８】即ち、第１容量電極２は、第１薄膜下地導
体層２１及び第１上部電極層４１とで構成される。ま
た、第２容量電極４は、第２薄膜下地導体層２２及び第
２上部電極層４２とで構成される。また、薄膜誘電体層
３の容量発生領域は、第１薄膜下地導体層２１と第2上
部電極層４２とが対向する領域、即ち、ａの領域であ
る。That is, the first capacitor electrode 2 is composed of the first thin film base conductor layer 21 and the first upper electrode layer 41. The second capacitor electrode 4 includes the second thin film base conductor layer 22 and the second upper electrode layer 42. The capacitance generating region of the thin-film dielectric layer 3 is a region where the first thin-film underlying conductor layer 21 and the second upper electrode layer 42 face each other, that is, a region a.
【００１９】支持基板１は、高周波動作において誘電損
が小さいもの、例えば、アルミナ等のセラミック基板、
ガラス基板、樹脂基板等の絶縁性基板、シリコン、ゲル
マニウム等の半導体基板及びＧａＡｓ、ＩｎＧａＡｓ等
の化合物半導体基板等を用いることができる。特に、強
度、耐熱性、コスト等の点でセラミック基板が好まし
い。The support substrate 1 has a small dielectric loss in high frequency operation, for example, a ceramic substrate such as alumina,
An insulating substrate such as a glass substrate or a resin substrate, a semiconductor substrate such as silicon or germanium, and a compound semiconductor substrate such as GaAs or InGaAs can be used. In particular, a ceramic substrate is preferable in terms of strength, heat resistance, cost, and the like.
【００２０】第１容量電極２を構成する第１薄膜下地導
体層２１及び第２容量電極４を構成する第２薄膜下地導
体層２２は、薄膜誘電体層３の成膜時の成膜温度に耐え
ることができるものであればよい。具体的には、高周波
領域で動作させた時、電極部分での導体損を極小化する
ため、Auが好ましい。例えば、電極材料のAuは、非酸化
性金属であるため、酸化防止膜の形成は不要である。ま
た、図では省略しているが、支持基板１と第１薄膜下地
導体層２１、第２薄膜下地導体層２２との密着性を向上
させるため、支持基板１と第１薄膜下地導体層２１、第
２薄膜下地導体層２２との界面に密着層としてＴｉまた
はＴｉＯ2などを介在させても構わない。The first thin-film base conductor layer 21 forming the first capacitance electrode 2 and the second thin-film base conductor layer 22 forming the second capacitance electrode 4 are heated to a film forming temperature when the thin-film dielectric layer 3 is formed. Anything that can withstand it is acceptable. Specifically, Au is preferable in order to minimize conductor loss at the electrode portion when operated in a high frequency region. For example, Au as an electrode material is a non-oxidizing metal, so that it is not necessary to form an antioxidant film. Although not shown in the drawing, in order to improve the adhesion between the support substrate 1 and the first thin film underlying conductor layer 21 and the second thin film underlying conductor layer 22, the support substrate 1 and the first thin film underlying conductor layer 21, Ti or TiO2 may be interposed as an adhesion layer at the interface with the second thin film base conductor layer 22.
【００２１】この第１薄膜下地導体層２１、第２薄膜下
地導体層２２は、同じ工程にて形成される。具体的な形
成方法としては、支持基板１の略全面に、上記電極材料
となる導体層（Ａuの単層またはＴi／Ａu層の多層）
を、公知の方法、例えば、電子ビーム蒸着法、スパッタ
法等の真空プロセス、印刷法、ＭＯＤ法、ゾルゲル法等
の塗布熱分解法等種々の方法で所望の膜厚に形成する。
その後、上記導体層を、フォトリソグラフィ及びエッチ
ング法、リフトオフ等により所望の形状にパターニング
することにより形成する。The first thin film conductor layer 21 and the second thin film conductor layer 22 are formed in the same step. As a specific forming method, a conductor layer (a single layer of Au or a multi-layer of Ti / Au layers) serving as the electrode material is formed on substantially the entire surface of the support substrate 1.
Is formed to a desired film thickness by various known methods, for example, a vacuum process such as an electron beam evaporation method and a sputtering method, a coating method such as a printing method, a MOD method, and a sol-gel method.
Thereafter, the conductor layer is formed by patterning into a desired shape by photolithography, etching, lift-off, or the like.
【００２２】これにより、例えば、互いに離間された第
１薄膜下地導体層２１、第２薄膜下地導体層２２を形成
することができる。Thus, for example, the first thin-film base conductor layer 21 and the second thin-film base conductor layer 22 that are separated from each other can be formed.
【００２３】ここで、第１薄膜下地導体層２１、第２薄
膜下地導体層２２の膜厚ｔ１は、０.１から３.０μｍ程
度が好ましい。ここで、重要なことは、第１薄膜下地導
体層２１、第２薄膜下地導体層２２の膜厚ｔ１は、薄膜
誘電体層３を形成した時、第１薄膜下地導体層２１、第
２薄膜下地導体層２２の端面稜線部分で段切れが発生し
ないように設定することが重要である。Here, the thickness t1 of the first thin-film underlying conductor layer 21 and the second thin-film underlying conductor layer 22 is preferably about 0.1 to 3.0 μm. What is important here is that the thickness t1 of the first thin-film underlying conductor layer 21 and the second thin-film underlying conductor layer 22 is determined when the thin-film dielectric layer 3 is formed. It is important to make settings so as not to cause disconnection at the edge line of the base conductor layer 22.
【００２４】また、第１薄膜下地導体層２１、第２薄膜
下地導体層２２の離間ｘの距離は、１０μｍである。The distance x between the first thin-film underlying conductor layer 21 and the second thin-film underlying conductor layer 22 is 10 μm.
【００２５】薄膜誘電体層３は、第１薄膜下地導体層２
１、第２薄膜下地導体層２２の離間する領域xを中心
に、第１薄膜下地導体層２１、第２薄膜下地導体層２２
に跨がるように被着形成される。尚、図では、第１薄膜
下地導体層２１上に被着される薄膜誘電体層３が大面積
となっている。尚、この第１薄膜下地導体層２１上に被
覆された薄膜誘電体層３が容量発生領域ａとなる。The thin film dielectric layer 3 is composed of the first thin film base conductor layer 2
1, the first thin-film underlying conductor layer 21 and the second thin-film underlying conductor layer 22 around a region x separated from the second thin-film underlying conductor layer 22
Is formed so as to straddle. In the figure, the thin film dielectric layer 3 applied on the first thin film conductor layer 21 has a large area. In addition, the thin film dielectric layer 3 coated on the first thin film base conductor layer 21 becomes a capacitance generation region a.
【００２６】この薄膜誘電体層３は、（Ｂａ1-x Ｓｒ
x ）ＴｉＯ3 （ただし、０＜ｘ＜１．０）で表されるペ
ロブスカイト型結晶構造を有する強誘電体酸化物薄膜で
ある。この薄膜誘電体層３は、上述したように、外部電
圧を印加することにより、その誘電率が変化するもので
ある。その膜厚は、誘電率の変化率などを考慮して適宜
調整することができ、例えば０．１５μｍ〜３μm程度
である。具体的には、（Ｂａ1-x Ｓｒx ）ＴｉＯ3 （た
だし、０＜ｘ＜１．０）となるように調整された誘電体
膜を、所定形状にパターニングして形成される。例え
ば、スパッタ法、蒸着法、ゾルゲル法、ＭＯＣＶＤ法、
ＭＯＤ法等の種々の方法で、第１薄膜下地導体層２１、
第２薄膜下地導体層２２上の全面（支持基板１の全面）
に薄膜誘電体層を形成し、その後、上記誘電体層をフォ
トリソグラフィ及びエッチング法、リフトオフ等により
所望の形状にパターニングすることにより形成する。This thin film dielectric layer 3 is made of (Ba 1-x Sr
x ) A ferroelectric oxide thin film having a perovskite crystal structure represented by TiO 3 (where 0 <x <1.0). As described above, the dielectric constant of the thin film dielectric layer 3 changes when an external voltage is applied. The film thickness can be appropriately adjusted in consideration of the change rate of the dielectric constant and the like, and is, for example, about 0.15 μm to 3 μm. Specifically, it is formed by patterning a dielectric film adjusted to satisfy (Ba 1-x Sr x ) TiO 3 (where 0 <x <1.0) into a predetermined shape. For example, sputtering, vapor deposition, sol-gel, MOCVD,
The first thin film base conductor layer 21 is formed by various methods such as the MOD method.
The entire surface on the second thin film base conductor layer 22 (the entire surface of the support substrate 1)
Then, a thin film dielectric layer is formed, and then the dielectric layer is formed by patterning it into a desired shape by photolithography, etching, lift-off, or the like.
【００２７】第１容量電極２を構成する第２上部電極層
４１及び第２容量電極４を構成する第２上部電極層４２
は、高周波領域で動作させた時、電極部分での導体損を
極小化するため、Auなどで形成される。例えば、電極材
料のAuは、非酸化性金属であるため、酸化防止膜の形成
は不要である。The second upper electrode layer 41 constituting the first capacitance electrode 2 and the second upper electrode layer 42 constituting the second capacitance electrode 4
Is formed of Au or the like in order to minimize conductor loss in the electrode portion when operated in a high frequency region. For example, Au as an electrode material is a non-oxidizing metal, so that it is not necessary to form an antioxidant film.
【００２８】ここで、第１上部電極層４１と第２上部電
極層４２とは、例えば第１薄膜下地導体層２１上に被着
された薄膜誘電体層３部分で離間されている。この離間
部分を符号Ｙで示している。そして、第１上部電極層４
１は、薄膜誘電体層３の一端部に重畳するように、第１
薄膜下地導体層２１上に積層されて配置される。第１上
部電極層４１が薄膜誘電体層３の一端部に重畳する部分
は、第１薄膜下地導体層２１上の薄膜誘電体層３の端部
であり、薄膜誘電体層３がこの端部からの剥離を防止す
るために重畳している。Here, the first upper electrode layer 41 and the second upper electrode layer 42 are separated from each other by, for example, a portion of the thin film dielectric layer 3 applied on the first thin film underlying conductor layer 21. This separated portion is indicated by the symbol Y. Then, the first upper electrode layer 4
1 is the first so as to overlap with one end of the thin film dielectric layer 3.
It is laminated and disposed on the thin film base conductor layer 21. The portion where the first upper electrode layer 41 overlaps one end of the thin-film dielectric layer 3 is the end of the thin-film dielectric layer 3 on the first thin-film base conductor layer 21, and the thin-film dielectric layer 3 is located at this end. In order to prevent peeling from the surface.
【００２９】第２上部電極層４２は、薄膜誘電体層３の
大部分を重畳するように、第２薄膜下地導体層２２上に
積層されて配置される。具体的には、第２上部電極層４
２は、第２薄膜下地導体層２２上に積層され、第２薄膜
下地導体層２２上に被覆された薄膜誘電体層３部分、離
間部分Ｘに被着された薄膜誘電体層３を越えて、第１薄
膜下地導体層２１上に被着された薄膜誘電体層３の一部
にまで延出されている。即ち、この第１薄膜下地導体層
２１の薄膜誘電体層３の被覆部分が、容量発生領域とな
る。The second upper electrode layer 42 is disposed on the second thin-film base conductor layer 22 so as to overlap most of the thin-film dielectric layer 3. Specifically, the second upper electrode layer 4
Reference numeral 2 denotes a portion of the thin-film dielectric layer 3 laminated on the second thin-film underlying conductor layer 22 and coated on the second thin-film underlying conductor layer 22 and beyond the thin-film dielectric layer 3 deposited on the separated portion X. Extending to a part of the thin-film dielectric layer 3 applied on the first thin-film base conductor layer 21. That is, the portion of the first thin film base conductor layer 21 that is covered with the thin film dielectric layer 3 becomes a capacitance generation region.
【００３０】この第１上部電極層４１と第２上部電極層
４２とは、同じ工程にて形成される。具体的な形成方法
としては、第１上部電極層４１、第２上部電極層４２と
なる導体層が、第１薄膜下地導体層２１、第２薄膜下地
導体層２２、薄膜誘電体層３を被覆するように支持基板
１の略全面に、公知の方法、例えば、電子ビーム蒸着
法、スパッタ法等の真空プロセス、印刷法、ＭＯＤ法、
ゾルゲル法等の塗布熱分解法等種々の方法で、所望の膜
厚ｔ２に形成する。その後、上記導体層を、フォトリソ
グラフィ及びエッチング法、リフトオフ等により所望の
形状にパターニングすることにより形成する。このパタ
ーニングにより、離間部分Ｙが形成され、第１薄膜下地
導体層２１上の薄膜誘電体層３上で、互いに離間された
第１上部電極層４１、第2上部電極層４２が形成される
ことになる。The first upper electrode layer 41 and the second upper electrode layer 42 are formed in the same step. As a specific forming method, a conductor layer serving as the first upper electrode layer 41 and the second upper electrode layer 42 covers the first thin film base conductor layer 21, the second thin film base conductor layer 22, and the thin film dielectric layer 3. A known method, for example, a vacuum process such as an electron beam evaporation method or a sputtering method, a printing method, a MOD method,
A desired film thickness t2 is formed by various methods such as a coating thermal decomposition method such as a sol-gel method. Thereafter, the conductor layer is formed by patterning into a desired shape by photolithography, etching, lift-off, or the like. By this patterning, the separated portion Y is formed, and the first upper electrode layer 41 and the second upper electrode layer 42 separated from each other are formed on the thin film dielectric layer 3 on the first thin film underlying conductor layer 21. become.
【００３１】ここで、第１上部電極層４１、第2上部電
極層４２の膜厚t２は、0.3から4.5μｍ程度である。こ
こで、重要なことは、第１上部電極層４１、第2上部電
極層４２の膜厚ｔ２は、第１薄膜下地導体層２１と積層
して構成される第１容量電極２、第２薄膜下地導体層２
２と積層して構成される第２容量電極４の導体損を考慮
して、極力厚く設定することが重要である。尚、第１上
部電極層４１と第2上部電極層４２との離間部分Ｙの距
離は、10μｍである。Here, the thickness t2 of the first upper electrode layer 41 and the second upper electrode layer 42 is about 0.3 to 4.5 μm. What is important here is that the film thickness t2 of the first upper electrode layer 41 and the second upper electrode layer 42 is the first capacitance electrode 2 and the second thin film Base conductor layer 2
It is important to set as thick as possible in consideration of the conductor loss of the second capacitor electrode 4 formed by laminating the second capacitor electrode 2 and the second capacitor electrode 2. The distance between the first upper electrode layer 41 and the second upper electrode layer 42 at a distance Y is 10 μm.
【００３２】ここで、離間部分Ｙを形成するためAuから
なる導体層をエッチング加工しなければならない。この
とき用いるエッチャント、例えば、シアン溶液またはヨ
ウ素とヨウ化カリウムの混合溶液である。このエッチャ
ントは、薄膜誘電体層３をエッチングしないという特徴
を持っているため、第１上部電極層４１、第2上部電極
層４２のみを容易にエッチングでき、薄膜誘電体層３の
保護するレジスト膜を形成する必要がない。その結果、
可変容量素子の作製プロセス全体が容易となる。Here, the conductor layer made of Au must be etched to form the separated portion Y. The etchant used at this time is, for example, a cyan solution or a mixed solution of iodine and potassium iodide. Since this etchant has a feature that the thin film dielectric layer 3 is not etched, only the first upper electrode layer 41 and the second upper electrode layer 42 can be easily etched, and the resist film which protects the thin film dielectric layer 3 is formed. Need not be formed. as a result,
The entire manufacturing process of the variable capacitance element is facilitated.
【００３３】上述のように可変容量素子は、第１容量電
極２と第２容量電極４との間に外部電圧を供給し、薄膜
誘電体層３の容量発生領域ａに所定電位を印加すると、
薄膜誘電体層３自身の誘電率が変化する。これより、第
１の容量電極２と第２の容量電極４とから得られる容量
値を可変制御することができる。As described above, when the variable capacitance element supplies an external voltage between the first capacitance electrode 2 and the second capacitance electrode 4 and applies a predetermined potential to the capacitance generation region a of the thin film dielectric layer 3,
The dielectric constant of the thin film dielectric layer 3 itself changes. Thus, the capacitance values obtained from the first capacitance electrode 2 and the second capacitance electrode 4 can be variably controlled.
【００３４】第１の容量電極２と第２容量電極４との間
に印加する電圧は、誘電体材料の種類、膜厚又は用途等
により適宜調整することができるが、例えば、薄膜誘電
体層３のリーク電流、電源の実用性等の観点から、10Ｖ
程度以下が望ましい。The voltage applied between the first capacitance electrode 2 and the second capacitance electrode 4 can be appropriately adjusted according to the type, thickness, or application of the dielectric material. 10V from the viewpoint of leakage current of 3 and practicality of power supply
Less than or equal to the degree is desirable.
【００３５】また、印加電圧に対応して変化する容量の
変化率（〔電圧印加後の容量−０Ｖでの容量〕／０Ｖで
の容量×１００）は、大きければ大きいほど好ましく、
例えば−２５％程度以上が挙げられる。The rate of change of the capacity ([capacity at 0 V after application of voltage−capacity at 0 V] / capacitance at 0 V × 100) is preferably as large as possible.
For example, about -25% or more is mentioned.
【００３６】さらに、上記外部制御電圧の印加に応じて
変化する薄膜誘電体層３の誘電率は、誘電体材料の種
類、薄膜誘電体層３の膜厚、第２容量電極４の対向面積
及びその形成方法、第１上部電極層４１、第２上部電極
層４２の加工精度等により異なるが、例えば200〜500程
度となる。Further, the dielectric constant of the thin film dielectric layer 3 which changes according to the application of the external control voltage depends on the type of the dielectric material, the thickness of the thin film dielectric layer 3, the facing area of the second capacitor electrode 4, and Although it depends on the formation method, the processing accuracy of the first upper electrode layer 41, and the processing accuracy of the second upper electrode layer 42, it is about 200 to 500, for example.
【００３７】上述の構造において、第１上部電極層４
１、第２上部電極層４２上に、保護膜５を被着形成して
も構わない。この保護膜５を形成するにあたり、マザー
ボード基板と接続するバンプ端子６、７などを形成する
領域に貫通孔を形成しなくてはならない。そして、この
第１上部電極層４１に第１バンプ端子６を、第２上部電
極層４２に第２バンプ端子７を形成する。このバンプ端
子６、７の材料が、例えば半田である場合には、貫通孔
から露出する第１上部電極層４１、第2上部電極層４２
上にＮｉなどの半田拡散防止層を形成する必要がある。In the above structure, the first upper electrode layer 4
First, the protective film 5 may be formed on the second upper electrode layer 42. In forming the protective film 5, a through hole must be formed in a region where bump terminals 6, 7 and the like to be connected to the motherboard substrate are formed. Then, the first bump terminals 6 are formed on the first upper electrode layer 41 and the second bump terminals 7 are formed on the second upper electrode layer 42. When the material of the bump terminals 6 and 7 is, for example, solder, the first upper electrode layer 41 and the second upper electrode layer 42 exposed from the through holes are provided.
It is necessary to form a solder diffusion preventing layer of Ni or the like thereon.
【００３８】このように保護膜５中に形成される貫通孔
の位置は（バンプ端子６、７が形成される領域）は、第
１薄膜下地導体層２１と第１上部電極層４１とが積層し
あう領域及び第２薄膜下地導体層２２と第2上部電極層
４２とが積層する領域である。これは、バンプ端子６、
７を形成する際の機械的な応力、熱的な応力が容量発生
領域ａに及ばないようにするためである。The position of the through hole formed in the protective film 5 (the area where the bump terminals 6 and 7 are formed) is such that the first thin film base conductor layer 21 and the first upper electrode layer 41 are laminated. This is a region where the second thin-film base conductor layer 22 and the second upper electrode layer 42 are laminated. This is the bump terminal 6,
This is to prevent the mechanical stress and the thermal stress when forming No. 7 from reaching the capacity generation region a.
【００３９】以上のように、本発明では、薄膜誘電体層
３を挟持する第１容量電極２と第２容量電極４を一定と
した場合、第１上部電極層４１、第１上部電極層４２の
厚みt２を相対的に厚くでき、薄膜誘電体層３の下地と
なる第１薄膜下地導体層２１、第２薄膜下地導体層２２
の厚みｔ１を相対的に薄くできる。例えば、第１薄膜下
地導体層２１、第２薄膜下地導体層２２の厚みｔ１を
０．１〜３．０μｍ、第１上部電極層４１、第１上部電
極層４２の厚みt２を０．３〜４．５μｍで、ｔ１＜t２
とする。As described above, in the present invention, when the first capacitor electrode 2 and the second capacitor electrode 4 sandwiching the thin film dielectric layer 3 are fixed, the first upper electrode layer 41 and the first upper electrode layer 42 Of the first thin-film conductor layer 21 and the second thin-film conductor layer 22 serving as the underlayer of the thin-film dielectric layer 3.
Can be made relatively thin. For example, the thickness t1 of the first thin-film base conductor layer 21 and the second thin-film base conductor layer 22 is 0.1 to 3.0 μm, and the thickness t2 of the first upper electrode layer 41 and the first upper electrode layer 42 is 0.3 to 0.3 μm. 4.5 μm, t1 <t2
And
【００４０】即ち、薄膜誘電体層３を形成するにあた
り、その下地となる第１薄膜下地導体層２１、第２薄膜
下地導体層２２の端部で薄膜誘電体層３の段切れが発生
せず、また、上述のように１０Ｖ程度の外部電圧を印加
しても第１容量電極２、第２容量電極４で電位の分布を
小さくすることができる。これにより、しかも、低抵
抗、低インダクタス化が可能となり、高周波動作に適し
た可変容量素子となる。That is, in forming the thin film dielectric layer 3, no disconnection of the thin film dielectric layer 3 occurs at the end portions of the first thin film conductor layer 21 and the second thin film conductor layer 22 which are the underlying layers. Further, even when an external voltage of about 10 V is applied as described above, the distribution of the potential at the first capacitance electrode 2 and the second capacitance electrode 4 can be reduced. As a result, the resistance and the inductance can be reduced, and the variable capacitance element is suitable for high-frequency operation.
【００４１】しかも、従来の構造のように、上部電極層
１４の一部がエアブリッジ１５などによって中空とはな
らないため、第１容量電極２、第２容量電極４に、マザ
ーボートに実装が容易なバンプ端子６、７を形成でき
る。Furthermore, unlike the conventional structure, a part of the upper electrode layer 14 does not become hollow due to the air bridge 15 or the like, so that it is easy to mount the first capacitor electrode 2 and the second capacitor electrode 4 on the mother boat. Bump terminals 6 and 7 can be formed.
【００４２】このような可変容量素子は、容量が高周波
回路の特性に影響して、フィルター透過特性、検出周波
数等を変化させることが可能となり、種々の高周波デバ
イス、例えば、高周波フィルター、インピーダンスアン
テナ、遅延素子、アレイアンテナ、結合型ストリップ線
路等の高周波デバイスに広く応用が可能となる。In such a variable capacitance element, the capacitance influences the characteristics of the high-frequency circuit, thereby making it possible to change the filter transmission characteristics, the detection frequency, etc., and various high-frequency devices such as high-frequency filters, impedance antennas, and the like. It can be widely applied to high-frequency devices such as delay elements, array antennas, and coupled strip lines.
【００４３】[0043]
【実施例】セラミック基板上にスパッタ法により成膜温
度２５０℃、Arガス圧５mTorrの条件下、膜厚２０nmの
ＴｉＯ2層および膜厚０.３μmのＡｕ膜を形成する。こ
のＡｕ膜をウェットエッチングにより所定の形状に加工
し、Ａｕからなる第１薄膜下地導体層２１、第２薄膜下
地導体層２２が形成できる。EXAMPLE A TiO 2 layer having a thickness of 20 nm and an Au film having a thickness of 0.3 μm are formed on a ceramic substrate by a sputtering method at a film forming temperature of 250 ° C. and an Ar gas pressure of 5 mTorr. This Au film is processed into a predetermined shape by wet etching, so that the first thin film underlying conductor layer 21 and the second thin film underlying conductor layer 22 made of Au can be formed.
【００４４】次に、このようにして形成したＡｕからな
る第１薄膜下地導体層２１、第２薄膜下地導体層２２上
に、（Ｂａ1-x Ｓｒx ）ＴｉＯ3 （ただし、０＜ｘ＜
１．０）で表される誘電体材料をスパッタ法により成膜
温度４００℃、Arガス圧７２ｍＴｏｒｒＯ2ガス圧１８
ｍＴｏｒｒの条件下、膜厚０.１５μmの薄膜誘電体層を
形成する。次いで、この薄膜誘電体層をエッチングによ
り、第１薄膜下地導体層２１と第２薄膜下地導体層２２
との離間部分Ｘを覆う所定形状の薄膜誘電体層３を形成
した。Next, (Ba 1 -x Sr x ) TiO 3 (where 0 <x <) is formed on the first thin film conductor layer 21 and the second thin film conductor layer 22 made of Au thus formed.
1.0) by sputtering, a film forming temperature of 400 ° C., an Ar gas pressure of 72 mTorrO 2 gas pressure of 18
Under a condition of mTorr, a thin film dielectric layer having a thickness of 0.15 μm is formed. Next, the first thin-film underlying conductor layer 21 and the second thin-film underlying conductor layer 22 are etched by etching the thin-film dielectric layer.
A thin film dielectric layer 3 having a predetermined shape is formed so as to cover the portion X separated from the thin film.
【００４５】さらに、このようにして形成した第１薄膜
下地導体層２１、第２薄膜下地導体層２２、薄膜誘電体
層３上にスパッタ法により成膜温度２５０℃、Ａｒガス
圧５ｍＴｏｒrの条件下、膜厚０.６μｍのＡｕ膜を形成
した。このＡｕ膜をエッチングにより所定の形状に加工
し、第１上部電極層４１、第２上部電極層４２を形成し
た。Further, on the first thin-film underlying conductor layer 21, the second thin-film underlying conductor layer 22, and the thin-film dielectric layer 3 formed as described above, the film was formed at a temperature of 250 ° C. and an Ar gas pressure of 5 mTorr by sputtering. An Au film having a thickness of 0.6 μm was formed. The Au film was processed into a predetermined shape by etching to form a first upper electrode layer 41 and a second upper electrode layer.
【００４６】ただし、本発明の実施の形態においては、
誘電体膜に（Ｂａ1-x Ｓｒx ）ＴｉＯ3 （ただし、０＜
ｘ＜１．０）を用いたが、薄膜コンデンサを作製するに
おいては、誘電体膜材料を特定しない。However, in the embodiment of the present invention,
(Ba 1-x Sr x ) TiO 3 (where 0 <
x <1.0), but the material of the dielectric film is not specified in producing the thin film capacitor.
【００４７】[0047]
【発明の効果】本発明の薄膜コンデンサは、薄膜誘電体
層を互いに離間して第１薄膜下地導体層と第２薄膜下地
導体層とに跨がるように形成し、また、第１上部電極層
を第１薄膜下地導体層上に、第２上部電極層を第２薄膜
下地導体層上に配置されている。即ち、第１薄膜下地導
体層と第１上部電極層とで第１容量電極が、第２薄膜下
地導体層と第２上部電極層とで第２容量電極が形成され
ている。According to the thin film capacitor of the present invention, the thin film dielectric layers are formed so as to be separated from each other and to straddle the first thin film underlying conductor layer and the second thin film underlying conductor layer. The layer is arranged on the first thin film conductor layer, and the second upper electrode layer is arranged on the second thin film conductor layer. That is, the first capacitor electrode is formed by the first thin-film base conductor layer and the first upper electrode layer, and the second capacitor electrode is formed by the second thin-film base conductor layer and the second upper electrode layer.
【００４８】この構造により第１薄膜下地導体層と第１
上部電極層との密着性及び第２薄膜下地導体層と第２上
部電極層との密着性が向上し、また、第１上部電極層、
第２上部電極層の膜厚を増加させた場合においても、各
種導体層や薄膜誘電体層の剥れを防ぐことができる。ま
た、夫々の第１薄膜下地導体層、第２薄膜下地導体層、
第１上部電極層、第２上部電極層の電極料にそれぞれＡ
ｕを用いることにより、容量電極の導体損を低減でき
る。With this structure, the first thin film base conductor layer and the first thin film
The adhesion to the upper electrode layer and the adhesion between the second thin film base conductor layer and the second upper electrode layer are improved.
Even when the thickness of the second upper electrode layer is increased, it is possible to prevent the various conductor layers and the thin film dielectric layer from peeling off. In addition, each of the first thin film underlying conductor layer, the second thin film underlying conductor layer,
The electrode materials of the first upper electrode layer and the second upper electrode layer are respectively A
By using u, the conductor loss of the capacitor electrode can be reduced.
【００４９】また、容量電極の低抵抗化により、容量発
生領域での容量電極の電位の分布を抑え、外部電圧を印
加しても耐える非常に実用性に高い可変容量素子とな
る。Also, by reducing the resistance of the capacitance electrode, the distribution of the potential of the capacitance electrode in the capacitance generation region is suppressed, and the variable capacitance element is extremely practical and can withstand an external voltage.
【図１】本発明の可変容量素子の概略断面図である。FIG. 1 is a schematic sectional view of a variable capacitance element according to the present invention.
【図２】従来の可変容量素子の概略断面図である。FIG. 2 is a schematic sectional view of a conventional variable capacitance element.
１、支持基板 ２ 第１容量電極 ２１ 第１薄膜下地導体層 ４１ 第１上部電極層 ４ 第２容量電極 ２２ 第２薄膜下地導体層 ４２ 第２上部電極層 ３ 薄膜誘電体層 DESCRIPTION OF SYMBOLS 1, Support substrate 2 1st capacitor electrode 21 1st thin film base conductor layer 41 1st upper electrode layer 4 2nd capacitor electrode 22 2nd thin film base conductor layer 42 2nd upper electrode layer 3 thin film dielectric layer
Claims (3)
薄膜下地導体層とを離間させて被着形成し、前記第１薄
膜下地導体層と第２薄膜下地導体層とに跨がるように、
外部電圧の印加により誘電率が変化する薄膜誘電体層を
被着形成し、 前記第１薄膜下地導体層上に第１上部電極層を被着形成
するとともに、前記第１薄膜下地導体層上に配置された
薄膜誘電体層の一部及び第２薄膜下地導体層上に第２上
部電極層を被着形成したことを特徴とする可変容量素
子。A first thin film base conductor layer and a second thin film base conductor layer on a supporting substrate;
The thin film base conductor layer is formed so as to be spaced apart from the thin film base conductor layer, and extends over the first thin film base conductor layer and the second thin film base conductor layer.
Forming a thin film dielectric layer whose dielectric constant changes by application of an external voltage, forming a first upper electrode layer on the first thin film underlying conductor layer, and forming a first upper electrode layer on the first thin film underlying conductor layer; A variable capacitance element, wherein a second upper electrode layer is formed on a part of the disposed thin film dielectric layer and on the second thin film base conductor layer.
導体層は、Auを主成分とする材料からなることを特徴と
する請求項1記載の可変容量素子。2. The variable capacitance element according to claim 1, wherein said first thin film base conductor layer and said second thin film base conductor layer are made of a material containing Au as a main component.
導体層の厚みｔ１は、第１上部電極層及び第２上部電極
層の厚みｔ２よりも厚いことを特徴とする請求項1記載
の可変容量素子。3. The semiconductor device according to claim 1, wherein a thickness t1 of each of the first thin-film underlying conductor layer and the second thin-film underlying conductor layer is greater than a thickness t2 of the first upper electrode layer and the second upper electrode layer. Variable capacitance element.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001102710A JP2002299163A (en) | 2001-03-30 | 2001-03-30 | Variable capacitance element |
| US10/113,776 US6806553B2 (en) | 2001-03-30 | 2002-03-28 | Tunable thin film capacitor |
| US10/927,272 US7012317B2 (en) | 2001-03-30 | 2004-08-26 | Tunable thin film capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001102710A JP2002299163A (en) | 2001-03-30 | 2001-03-30 | Variable capacitance element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002299163A true JP2002299163A (en) | 2002-10-11 |
Family
ID=18955869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001102710A Pending JP2002299163A (en) | 2001-03-30 | 2001-03-30 | Variable capacitance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002299163A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7898792B2 (en) | 2005-10-18 | 2011-03-01 | Murata Manufacturing Co., Ltd | Thin-film capacitor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01206614A (en) * | 1988-02-15 | 1989-08-18 | Mitsumi Electric Co Ltd | Manufacture of capacitor |
| JPH11260667A (en) * | 1998-03-10 | 1999-09-24 | Sharp Corp | Variable-capacitance element for high frequency and manufacture thereof |
| JP2000357631A (en) * | 1998-12-22 | 2000-12-26 | Matsushita Electric Ind Co Ltd | Flexible thin film capacitor and its manufacture |
-
2001
- 2001-03-30 JP JP2001102710A patent/JP2002299163A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01206614A (en) * | 1988-02-15 | 1989-08-18 | Mitsumi Electric Co Ltd | Manufacture of capacitor |
| JPH11260667A (en) * | 1998-03-10 | 1999-09-24 | Sharp Corp | Variable-capacitance element for high frequency and manufacture thereof |
| JP2000357631A (en) * | 1998-12-22 | 2000-12-26 | Matsushita Electric Ind Co Ltd | Flexible thin film capacitor and its manufacture |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7898792B2 (en) | 2005-10-18 | 2011-03-01 | Murata Manufacturing Co., Ltd | Thin-film capacitor |
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