JPH01206614A - Manufacture of capacitor - Google Patents
Manufacture of capacitorInfo
- Publication number
- JPH01206614A JPH01206614A JP63032399A JP3239988A JPH01206614A JP H01206614 A JPH01206614 A JP H01206614A JP 63032399 A JP63032399 A JP 63032399A JP 3239988 A JP3239988 A JP 3239988A JP H01206614 A JPH01206614 A JP H01206614A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- capacitor
- conductive layer
- thin film
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010409 thin film Substances 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052802 copper Inorganic materials 0.000 claims abstract description 10
- 239000010949 copper Substances 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000919 ceramic Substances 0.000 abstract description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009713 electroplating Methods 0.000 abstract description 4
- 229910052759 nickel Inorganic materials 0.000 abstract description 4
- 239000010408 film Substances 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 3
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 6
- 229910002113 barium titanate Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、電子回路に使用されるコンデンサの製造法
に関するものであり、特に、銅メッキとスパッタリング
等による薄膜によって形成するコンデンサの製造法に関
するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing capacitors used in electronic circuits, and in particular to a method for manufacturing capacitors formed by thin films such as copper plating and sputtering. It is something.
［従来の技術］
従来のチップコンデンサは別紙添付の第１３図に示すよ
うに、銀パラジウム（Ａｇ−Ｐｄ）等で形成した端子電
極（ＩＸＩ）に夫々電極板（２）（２）・・・を突設し
、チタン酸バリウム（３）を介して相互に積層して形成
していた。そして、第１４図のように基板（４）上に設
けられた電極（５）（５）へ、前記端子（１）（１）の
下面をハンダ付して固着していた。[Prior Art] As shown in the attached Figure 13, a conventional chip capacitor has terminal electrodes (IXI) formed of silver-palladium (Ag-Pd), etc., and electrode plates (2), (2), etc., respectively. They were formed by protruding from each other and stacking them on each other with barium titanate (3) interposed therebetween. Then, as shown in FIG. 14, the lower surfaces of the terminals (1) (1) were fixed by soldering to the electrodes (5) (5) provided on the substrate (4).
し発明が解決しようとする課題］
前述した従来のチップコンデンサは、夫々の電極板（２
）（２）・・・間が５０〜６０μｍであり、厚みが大で
あった。依って、大容量のコンデンサを形成する場合は
、電極板（２）（２）・・・の面積を拡大するか或は電
極板（２Ｘ２）・・・の積層枚数を増加させねばならず
、コンデンサが大型になるという問題点があった。[Problems to be Solved by the Invention] The conventional chip capacitor described above has two electrode plates (two
)(2)... The distance was 50 to 60 μm, and the thickness was large. Therefore, when forming a large capacity capacitor, it is necessary to increase the area of the electrode plates (2), (2), etc., or increase the number of laminated electrode plates (2×2), etc. There was a problem that the capacitor became large.
而も、前記チタン酸バリウム（３）の表面は微細な凹凸
があり、稀にピンホールが発生した場合は裏面側と導通
して電気的短絡が生じることがあった。However, the surface of the barium titanate (3) has minute irregularities, and in rare cases where a pinhole occurs, it may be electrically connected to the back side, causing an electrical short circuit.
又、チタン酸バリウム（３）を焼成しであるので、空気
中の水分が含浸してコンデンサの特性が悪化する虞れを
有していた。そこで、この発明は薄型で大容量であり、
且つ、信頼性の高いコンデンサの製造法を提供すること
を目的とする。Furthermore, since the barium titanate (3) is fired, there is a risk that moisture in the air may impregnate the capacitor, thereby degrading the characteristics of the capacitor. Therefore, this invention is thin and has a large capacity.
Another object of the present invention is to provide a method for manufacturing a capacitor with high reliability.
［課題を解決するための手段］
この発明は、上記目的を達成するために提案せられたも
のであり、基板上に銅メッキにて導電層を設け、エツチ
ングにより第１の電極を形成し、スパッタリングによっ
て前記導電層表面に誘導体の薄膜を設け、更に、その表
面へ銅メッキにて導電層を設けた後エツチングにより第
２の電極を形成し、第１の電極と第２の電極との間に静
電容量を形成できるようにしたことを特徴とするコンデ
ンサの製造法を提供せんとするものである。[Means for Solving the Problems] The present invention was proposed to achieve the above object, and includes providing a conductive layer on a substrate by copper plating, forming a first electrode by etching, A thin film of a dielectric is provided on the surface of the conductive layer by sputtering, and a conductive layer is further provided on the surface by copper plating, and then a second electrode is formed by etching, and a second electrode is formed between the first electrode and the second electrode. It is an object of the present invention to provide a method for manufacturing a capacitor, which is characterized in that a capacitance can be formed in a capacitor.
［作用］
この発明は、基板上にメッキ処理によって導電層を設け
、エツチングによって第１の電極を形成する。そして、
その表面へ例えばスパッタリングにて誘電体の薄膜を設
け、更に、前記基板の表面に導電層を設けてエツチング
により該薄膜の上部に第２の電極を形成する。斯くして
、第１の電極と第２の電極との間に誘電体の薄膜が形成
され、双方の電極間に静電容量が発生してコンデンサが
形成される。而も、メッキ処理によって導電層を設ける
ため製造コストを著しく低減でき、且つ、電極パターン
の形成も容易である。又、電極間を極めて薄くすること
ができ、大容量のコンデンサの製造が可能となる。[Operation] In the present invention, a conductive layer is provided on a substrate by plating, and a first electrode is formed by etching. and,
A dielectric thin film is provided on the surface by, for example, sputtering, and a conductive layer is further provided on the surface of the substrate, and a second electrode is formed on the thin film by etching. In this way, a dielectric thin film is formed between the first electrode and the second electrode, and capacitance is generated between both electrodes to form a capacitor. Moreover, since the conductive layer is provided by plating, manufacturing costs can be significantly reduced, and electrode patterns can be easily formed. Furthermore, the gap between the electrodes can be made extremely thin, making it possible to manufacture a capacitor with a large capacity.
［実施例］
以下、この発明の一実施例を別紙添付図面に従って詳述
する。第１図（３）（ト）に於て符号Ｑｏ）はアルミナ
等を焼成して形成したセラミック白基板を示し、このセ
ラミック白基板θ０）へ無電解の化学メッキでニッケル
被膜Ｑ＋）を施し、これを電極として銅の電気メッキに
て所定の厚み（１０〜１００μｍ）を有する導電層（１
２を設け、第２図（ａ）（ハ）の如くエツチングにより
表面へ第１の電極（ｌ■を形成する。そして、第３図（
３）（ハ）の如く、表面の所定部分に高純度（９９，９
％）の酸化アルミ（ＡＬ２０．）をスパッタリングして
数μｍの誘電体の薄膜（ゆを設ける。[Example] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings. In Fig. 1 (3) (g), the symbol Qo) indicates a ceramic white substrate formed by firing alumina or the like, and a nickel coating Q+) is applied to this ceramic white substrate θ0) by electroless chemical plating. Using this as an electrode, conductive layer (1
2, and form a first electrode (l) on the surface by etching as shown in FIGS. 2(a) and (c). Then, as shown in FIG.
3) As shown in (c), high purity (99,9
%) aluminum oxide (AL20.) is sputtered to form a dielectric thin film of several micrometers.
更に、銅の電気メッキにて両面に導電層を設け、第４図
（→（ハ）に示す如（、エツチングによって前記表面へ
第２の電極θつを設けた後、必要に応じて表面に樹脂コ
ート等の絶縁被膜を施して腐食を防止する。斯くして、
第５図に示すようなチップコンデンサ（１６）が形成さ
れるのである。Furthermore, a conductive layer is provided on both sides by copper electroplating, and after providing second electrodes θ on the surface by etching, as shown in FIG. Apply an insulating coating such as a resin coat to prevent corrosion.In this way,
A chip capacitor (16) as shown in FIG. 5 is formed.
ここで、前記チップコンデンサ（＋１９は第４図（（至
）（ハ）に於て、第１の電極（１■と第２の電極（Ｉ５
ｉ）とが重合する部位の対向面積（Ｓ）に応じて静電容
量が決定される。第１の電極（１等と第２の電極（１つ
との間隔、即ち誘電体の薄膜（ロ）の厚みをｔとし、誘
電率をεとすれば両電極間の静電容量（Ｃ）は次式で表
わ例えば、前記双方の電極θ■θつの対向面積（Ｓ）が
１ｍｍ２であり、且つ誘電体の薄膜（ロ）の厚みが１μ
ｍの場合、酸化アルミ（Ａｌ２Ｏ２）の誘電率（ε）は
約９程度であるので、
（ｌ Ｘｌ０−３）２
ｃ、 ＝８．８ Ｘｌ０−１２Ｘ９ ＸＩ Ｘｌ０−６
＝７９ＸＩＯ−１２（Ｆ ）
即ち、当該チップコンデンサ（＋６）の静電容量（Ｃ０
）は８０ｐＦとなり、極めて大容量のコンデンサが形成
される。Here, the chip capacitor (+19) is connected to the first electrode (1■) and the second electrode (I5) in FIG.
The capacitance is determined according to the facing area (S) of the site where the and i) are polymerized. If t is the distance between the first electrode (1st grade) and the second electrode (1st grade), that is, the thickness of the dielectric thin film (b), and ε is the dielectric constant, then the capacitance (C) between the two electrodes is For example, if the opposing area (S) of both electrodes θ■θ is 1 mm2, and the thickness of the dielectric thin film (B) is 1 μ
m, the dielectric constant (ε) of aluminum oxide (Al2O2) is about 9, so (l Xl0-3)2 c, = 8.8 Xl0-12X9 XI Xl0-6 = 79XIO-12(F) That is, the capacitance (C0
) is 80 pF, forming an extremely large capacitor.
次に、本発明の製造法によって同時に多数のコンデンサ
（１＠ （＋６１・・・を製造する手順を説明する。尚
、第１図（ａ）（ハ）乃至第５図に於ける同一構成部分
には、同一符号を付して説明する。第６図乃至第８図は
セラミックの連結基板（０を示したもので、該連結基板
（ｒｔ）の一方向にスリット＠（日・−・を穿設してあ
り、このスリット（日（ト）・・・と直交してスナップ
ライン（１９）（ハ）・・・が刻設されている。第９図
（ａ）（ハ）（Ｃ）乃至第１２図（→（ハ）（Ｃ）は、
夫々第６図のＢ−Ｂ線要部を示したものであり、夫々各
図（ａ）は表面側を示し、各図（ハ）は裏面側を示し、
更に各図（Ｃ）は縦断面を示している。そして、前記ス
リット（日（四−・・とスナップライン■（つ・・・に
て夫々セラミック白基板θ０）Ｃ０）・・・のチップの
大きさが設定されている。第９図（ａ）（ハ）（Ｃ）の
連結基板（ｒ’）へ無電解の化学メッキでニッケル被膜
θ１）を施し、これを電極として銅の電気メッキにて導
電層（ゆを設ける。然るとき、前記スリット（日内も当
然メッキ処理されて導電層（ゆが設けられる。次に第１
０図（３）（ハ）（Ｃ）に示すように、夫々のチップ表
面をエツチングして第１の電極（１■（ｌ■・・・を形
成し、且つ裏面の不要部分を除去する。そして、第１１
図（ａ）（ハ）（Ｃ）の如く、表面の所定部分に前記高
純度の酸化アルミ（ＡｈＯ：＋）をスパッタリングして
、数μｍの誘電体の薄膜（Ａ）（→・・・を設ける。更
に、銅メッキにて前記連結基板（０の両面に導電層を設
け、エツチングによって第１２図（ａ）（ハ）（Ｃ）の
ように、各チップ表面に第２の電極（００ツ・・・を形
成すると共に、裏面の不要部分を除去して端子電極Ｇ１
１（ｎ−・・を設ける。然るのち、前記スナップライン
（鴎（＋９）・・・を切欠すれば各チップに分割され、
第５図に示したチップコンデンサ（＋６）を形成するこ
とができる。 □尚、前記スリット（ＩＦ５ （１・
・・によってスリット（ト）内面にも導電層がメッキさ
れ、端子電極（イ）（イ）が形成されるのである。Next, a procedure for simultaneously manufacturing a large number of capacitors (1@(+61...) using the manufacturing method of the present invention will be explained. 6 to 8 show a ceramic connecting substrate (0 is shown), and a slit @ (day...) is provided in one direction of the connecting substrate (rt). A snap line (19) (c)... is engraved perpendicularly to this slit ((g)). Fig. 9 (a) (c) (c) From Figure 12 (→ (C) (C),
Each figure shows the main part along line B-B in Fig. 6, and each figure (a) shows the front side, each figure (c) shows the back side,
Furthermore, each figure (C) shows a longitudinal section. Then, the size of the chip of the slit (ceramic white substrate θ0) C0 is set at the snap line (4-... and snap line 2) (respectively). Fig. 9(a) (C) A nickel film θ1) is applied to the connection substrate (r') of (C) by electroless chemical plating, and a conductive layer (Y) is provided by copper electroplating using this as an electrode. (Naturally, a conductive layer (distortion) is provided by plating.Next, the first
As shown in FIGS. 0(3)(c) and (c), the surface of each chip is etched to form a first electrode (1) (1), and unnecessary portions of the back surface are removed. And the 11th
As shown in Figures (a), (c), and (c), the high-purity aluminum oxide (AhO:+) is sputtered onto a predetermined portion of the surface to form a dielectric thin film (A) (→...) of several μm. Further, a conductive layer is provided on both sides of the connection board (0) by copper plating, and a second electrode (00) is formed on the surface of each chip by etching as shown in FIGS. . . . and remove unnecessary parts on the back side to form the terminal electrode G1.
1 (n-...). Then, by cutting out the snap line (鴴(+9)...), it is divided into each chip,
A chip capacitor (+6) shown in FIG. 5 can be formed. □In addition, the slit (IF5 (1・
..., the inner surface of the slit (G) is also plated with a conductive layer, and the terminal electrodes (A) and (A) are formed.
［発明の効果］
この発明は上記一実施例にて詳述したように、メッキ処
理によって電極を設け、各電極間にスパッタリング等に
よって誘電体の薄膜を形成している。従って、前記電極
間を極めて薄くすることができ大容量の静電容量値を得
ることができる。而も、メッキ処理及びスパッタリング
等による薄膜によって各層を形成するため、連結基板で
同時に複数個のチップコンデンサを製造することが可能
であり、製作コストを著しく低減することができる。又
、スパッタリング等にて形成された誘電体の薄膜表面は
極めて平滑となり、ピンポール等の発生する虞れが防止
でき、且つ、電極間に電気的短絡が生じる憂いがなくな
る。依って、歩留りを良好にして信頼性が向上される等
正に諸種の効果を奏する発明である。尚、この発明の実
施例は叙述せる如き構成を有するものであるが、この発
明の精神を逸脱しない範囲に於て種々の改変を為すこと
ができ、そして、この発明がそれに及ぶことは当然であ
る。[Effects of the Invention] As described in detail in the above embodiment, the present invention provides electrodes by plating, and forms a dielectric thin film between each electrode by sputtering or the like. Therefore, the distance between the electrodes can be made extremely thin, and a large capacitance value can be obtained. Moreover, since each layer is formed by a thin film formed by plating, sputtering, etc., it is possible to simultaneously manufacture a plurality of chip capacitors using a connecting substrate, and the manufacturing cost can be significantly reduced. Furthermore, the surface of the dielectric thin film formed by sputtering or the like becomes extremely smooth, preventing the possibility of pin poles and the like, and eliminating the fear of electrical short circuits occurring between electrodes. Therefore, this invention has various effects such as improving yield and improving reliability. Although the embodiments of this invention have the configuration described above, various modifications can be made without departing from the spirit of this invention, and it is natural that this invention extends to such modifications. be.
第１図乃至第２図は本発明の一実施例を示したものであ
る。第１図（ａ）（ハ）乃至第４図（→（ハ）はチップ
コンデンサの製造手順を示したもので、夫々各図（ａ）
は縦断面図、各図（ハ）は平面図である。第５図はチッ
プコンデンサの斜面図、第６図は連結基板の平面図、第
７図は同側面図、第８図は第６図のＡ−Ａ線縦断面図で
ある。第９図（ａ）（ハ）（Ｃ）乃至第１２図＜ａ＞（
ハ）（Ｃ）は連結基板の製造手順を示した第６図Ｂ−Ｂ
線の要部拡大図で、夫々（→は表面図、各図（ハ）は裏
面図、各図（Ｃ）は縦断面図である。第１３図及び第１
４図は従来例を示したものであり、第１３図はチップコ
ンデンサの縦断面図、第１４図はチップコンデンサを基
板へ取付けた状態を示す要部縦断面図である。
１０：セラミック白基板 １２：導電層１３：第１の電
極 １４：誘電体の薄膜１５：第２の電極 １
６：チップコンデンサ「 ○
ｒ−寸
味
★１泊1 and 2 show an embodiment of the present invention. Figures 1 (a) (c) to 4 (→ (c) show the manufacturing procedure of chip capacitors; each figure (a)
is a longitudinal sectional view, and each figure (c) is a plan view. 5 is a perspective view of the chip capacitor, FIG. 6 is a plan view of the connecting board, FIG. 7 is a side view of the same, and FIG. 8 is a longitudinal sectional view taken along the line A--A in FIG. 6. Figures 9(a)(c)(C) to 12<a>(
C) (C) is Figure 6 B-B showing the manufacturing procedure of the connecting board.
These are enlarged views of the main parts of the lines, respectively (→ is a front view, each figure (C) is a back view, and each figure (C) is a longitudinal cross-sectional view.
FIG. 4 shows a conventional example, FIG. 13 is a longitudinal cross-sectional view of a chip capacitor, and FIG. 14 is a longitudinal cross-sectional view of essential parts showing a state in which the chip capacitor is attached to a substrate. 10: Ceramic white substrate 12: Conductive layer 13: First electrode 14: Dielectric thin film 15: Second electrode 1
6: Chip capacitor “○ r-size★1 night
Claims (1)
第１の電極を形成し、スパッタリング等によつて前記導
電層表面に誘導体の薄膜を設け、更に、その表面へ銅メ
ッキにて導電層を設けた後エッチングにより第２の電極
を形成し、第１の電極と第２の電極との間に静電容量を
形成できるようにしたことを特徴とするコンデンサの製
造法。A conductive layer is provided on the substrate by copper plating, a first electrode is formed by etching, a thin film of a dielectric is provided on the surface of the conductive layer by sputtering, etc., and a conductive layer is further applied to the surface by copper plating. A method for manufacturing a capacitor, characterized in that a second electrode is formed by etching after being provided, so that a capacitance can be formed between the first electrode and the second electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63032399A JPH01206614A (en) | 1988-02-15 | 1988-02-15 | Manufacture of capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63032399A JPH01206614A (en) | 1988-02-15 | 1988-02-15 | Manufacture of capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01206614A true JPH01206614A (en) | 1989-08-18 |
Family
ID=12357876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63032399A Pending JPH01206614A (en) | 1988-02-15 | 1988-02-15 | Manufacture of capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01206614A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002299163A (en) * | 2001-03-30 | 2002-10-11 | Kyocera Corp | Variable capacitance element |
-
1988
- 1988-02-15 JP JP63032399A patent/JPH01206614A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002299163A (en) * | 2001-03-30 | 2002-10-11 | Kyocera Corp | Variable capacitance element |
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