JP2002237185A - Semiconductor memory, and switching method of semiconductor memory - Google Patents
Semiconductor memory, and switching method of semiconductor memoryInfo
- Publication number
- JP2002237185A JP2002237185A JP2001035366A JP2001035366A JP2002237185A JP 2002237185 A JP2002237185 A JP 2002237185A JP 2001035366 A JP2001035366 A JP 2001035366A JP 2001035366 A JP2001035366 A JP 2001035366A JP 2002237185 A JP2002237185 A JP 2002237185A
- Authority
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- Japan
- Prior art keywords
- external power
- power supply
- circuit
- semiconductor memory
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体記憶装置に
関し、更に言えば、外部電源を降圧して内部電源を作り
動作させるＤＲＡＭ等の半導体記憶装置において、例え
ば外部電源電圧５Ｖ（内部降圧電位３．３Ｖ）版と外部
電源電圧３．３Ｖ単一版の異なる仕様の製品をメタルレ
チクル等の切り替えで作るメモリに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device such as a DRAM which operates by generating an internal power supply by stepping down an external power supply. The present invention relates to a memory for producing a product having different specifications between a .3V) version and a single version of an external power supply voltage of 3.3V by switching a metal reticle or the like.
【０００２】[0002]
【従来の技術】従来の半導体記憶装置、特にＤＲＡＭは
プロセスの微細化に伴いＬＳＩ内部の信頼性を確保する
ため、外部電源を降圧回路を用いて降圧し、内部電源を
発生させて内部回路を動作させている。2. Description of the Related Art In a conventional semiconductor memory device, especially a DRAM, in order to secure reliability inside an LSI with miniaturization of a process, an external power supply is stepped down using a step-down circuit, and an internal power supply is generated to generate an internal circuit. It is working.
【０００３】この場合、ＤＲＡＭ特有のワード線電位は
内部の電源よりも高い電圧レベルが必要なため、ＶPP
（＞ＶCC）発生回路等のチャージポンプ回路を使い昇圧
電位を発生させて、ワード線駆動回路の電源として使う
のが一般的であった。In this case, since the word line potential peculiar to the DRAM requires a higher voltage level than the internal power supply, VPP
(> VCC) In general, a booster potential is generated using a charge pump circuit such as a generating circuit and used as a power supply for a word line drive circuit.
【０００４】即ち、図２に示すように外部電源１０（例
えば、外部電源電圧５Ｖ）を降圧回路１１により所望の
内部降圧電位（例えば、内部電源電位３．３Ｖ）まで降
圧し、この内部降圧電位を用いて内部メモリ回路１２を
動作させる。また、ワード線駆動回路１４を動作させる
場合には、ＶPP発生回路１３を用いて前記内部降圧電位
を所望電位までに昇圧し、当該ワード線駆動回路１４を
動作させている。That is, as shown in FIG. 2, an external power supply 10 (for example, an external power supply voltage of 5 V) is stepped down by a step-down circuit 11 to a desired internal step-down potential (for example, an internal power supply potential of 3.3 V). To operate the internal memory circuit 12. When the word line drive circuit 14 is operated, the internal step-down potential is raised to a desired potential by using the VPP generation circuit 13, and the word line drive circuit 14 is operated.
【０００５】[0005]
【発明が解決しようとする課題】上述したようにＶPP発
生回路１３は、チャージポンプ回路から成り、ポンプの
駆動用に大きな容量が必要となる。そのため、チップサ
イズが大きくなるといった問題があった。As described above, the VPP generation circuit 13 is composed of a charge pump circuit, and requires a large capacity for driving the pump. Therefore, there is a problem that the chip size becomes large.
【０００６】また、降圧回路で発生させる内部電源電圧
は、電流駆動能力がある程度制限されるため、センスア
ンプの動作時等、ピーク電流が大きく流れると、その電
位が大きく変動するといった問題もあった。In addition, since the current drive capability of the internal power supply voltage generated by the step-down circuit is limited to some extent, there is a problem that the potential fluctuates greatly when a large peak current flows during operation of a sense amplifier or the like. .
【０００７】[0007]
【課題を解決するための手段】そこで、本発明の半導体
記憶装置は上記課題に鑑み、外部電源と、前記外部電源
から供給される外部電源電圧を所望電位まで降圧する降
圧回路と、前記降圧回路に接続された内部メモリ回路
と、前記外部電源が接続されたワード線駆動回路とから
成る第１の半導体記憶装置と、外部電源と、前記外部電
源が接続された内部メモリ回路と、前記外部電源から供
給される外部電源電圧を所望電位まで昇圧する昇圧回路
と、前記昇圧回路に接続されたワード線駆動回路とから
成る第２の半導体記憶装置とをマスク切り替えすること
を特徴とする。SUMMARY OF THE INVENTION In view of the above problems, a semiconductor memory device of the present invention has an external power supply, a step-down circuit for stepping down an external power supply voltage supplied from the external power supply to a desired potential, and a step-down circuit. A first semiconductor memory device comprising an internal memory circuit connected to the external power supply and a word line drive circuit connected to the external power supply; an external power supply; an internal memory circuit connected to the external power supply; And a second semiconductor memory device including a booster circuit for boosting an external power supply voltage supplied from the booster circuit to a desired potential and a word line drive circuit connected to the booster circuit.
【０００８】[0008]
【発明の実施の形態】以下、本発明の半導体記憶装置に
係る一実施形態について図面を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device according to the present invention will be described below with reference to the drawings.
【０００９】ここで、本発明の特徴は、外部電源を降圧
して内部電源を作り動作させるＤＲＡＭ等の半導体記憶
装置において、例えば外部電源電圧５Ｖ（内部降圧電位
３．３Ｖ）版と外部電源電圧３．３Ｖ単一版の異なる仕
様の製品をメタルレチクル等で切り替え可能にしたこと
である。Here, a feature of the present invention is that, in a semiconductor memory device such as a DRAM which operates by making an internal power supply by stepping down an external power supply, for example, an external power supply voltage of 5 V (internal step-down potential of 3.3 V) and an external power supply voltage A product of different specifications of a single 3.3V version can be switched with a metal reticle or the like.
【００１０】図１（ａ）は本発明の半導体記憶装置にお
ける、外部電源電圧５Ｖ（内部降圧電位３．３Ｖ）版の
実施形態で、図１（ｂ）は外部電源電圧３．３Ｖ単一版
の実施形態を説明するための図である。FIG. 1A shows an embodiment of an external power supply voltage of 5 V (internal step-down potential of 3.3 V) in a semiconductor memory device of the present invention, and FIG. 1B shows a single external power supply voltage of 3.3 V. It is a figure for explaining an embodiment.
【００１１】即ち、図１（ａ）に示すように外部電源電
圧５Ｖ（内部降圧電位３．３Ｖ）版の場合、外部電源１
（外部電源電圧５Ｖ）を降圧回路２により所望の内部降
圧電位（内部電源電位３．３Ｖ）まで降圧し、この内部
降圧電位を用いて内部メモリ回路３を動作させる。That is, as shown in FIG. 1A, in the case of the external power supply voltage 5 V (internal step-down potential 3.3 V) version, the external power supply 1
(External power supply voltage 5 V) is reduced to a desired internal step-down potential (internal power supply potential 3.3 V) by the step-down circuit 2, and the internal memory circuit 3 is operated using the internal step-down potential.
【００１２】また、ワード線駆動回路４を動作させる場
合には、従来技術で説明したような昇圧電位の代わりに
前記外部電源１から外部電源電圧を直接供給している。When the word line drive circuit 4 is operated, an external power supply voltage is directly supplied from the external power supply 1 instead of the boosted potential as described in the prior art.
【００１３】そして、使わなくなったＶP P発生回路５
内の大きな容量は、内部電源の安定化容量として用い
る。Then, the unused VPP generation circuit 5
The large capacity inside is used as the stabilization capacity of the internal power supply.
【００１４】更に、低電圧版、即ち外部電源電圧３．３
Ｖ単一版の場合には、図１（ｂ）に示すように外部電源
１（外部電源電圧３．３Ｖ）を直接、内部メモリ回路３
に供給して当該内部メモリ回路３を動作させる。Further, a low voltage version, ie, an external power supply voltage 3.3
In the case of the V single version, the external power supply 1 (external power supply voltage 3.3 V) is directly supplied to the internal memory circuit 3 as shown in FIG.
To operate the internal memory circuit 3.
【００１５】また、ワード線駆動回路４を動作させる場
合には、前記外部電源１（外部電源電圧３．３Ｖ）をＶ
PP発生回路５を用いてワード線昇圧電位まで昇圧し、当
該ワード線駆動回路４を動作させている。When the word line drive circuit 4 is operated, the external power supply 1 (external power supply voltage 3.3 V) is
The word line drive circuit 4 is operated by raising the voltage to the word line boost potential using the PP generation circuit 5.
【００１６】このとき、降圧回路は未使用で、内部メモ
リ回路３には外部電源が直接供給されるため、電位変動
は少なく、安定化容量は必要なくなる。At this time, since the step-down circuit is not used and the external power is directly supplied to the internal memory circuit 3, the potential fluctuation is small and the stabilizing capacity is not required.
【００１７】このように本発明では、外部電源５Ｖ版の
場合、内部電源電位の安定化が図れ、またＶPP発生回路
５を使用していないため、省電力化が図れる。As described above, according to the present invention, in the case of the external power supply 5 V version, the internal power supply potential can be stabilized, and power consumption can be reduced because the VPP generation circuit 5 is not used.
【００１８】更に、本発明では上記外部電源５Ｖ版と低
電圧版がメタル等のレチクル切り替えで生産可能とな
り、開発コストの低減化並びに納期期間の短縮化が図れ
る。Further, in the present invention, the external power supply 5V version and the low voltage version can be produced by switching the reticle of metal or the like, so that the development cost can be reduced and the delivery period can be shortened.
【００１９】[0019]
【発明の効果】本発明によれば、外部電源が高電圧版の
場合、内部電源電位の安定化が図れ、また昇圧回路を使
用しないため、省電力化が図れる。According to the present invention, when the external power supply is a high-voltage version, the potential of the internal power supply can be stabilized, and power consumption can be reduced because no booster circuit is used.
【００２０】また、外部電源が低電圧版の場合、内部メ
モリ回路に外部電源が直接供給されるため、電位変動が
少なくて済む。Further, when the external power supply is of a low voltage version, the external power supply is directly supplied to the internal memory circuit, so that the potential fluctuation can be reduced.
【００２１】更に、外部電源が異なる（高電圧版と低電
圧版）仕様の製品をメタル等のレチクル切り替えで生産
可能となり、開発コストの低減化並びに納期期間の短縮
化が図れる。Further, it is possible to produce products with different external power supplies (high-voltage version and low-voltage version) by switching the reticle of metal or the like, thereby reducing development costs and shortening the delivery period.
【図１】本発明の一実施形態の半導体記憶装置を示す断
面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present invention.
【図２】従来の半導体記憶装置を示す図である。FIG. 2 is a diagram showing a conventional semiconductor memory device.
１ 外部電源 ２ 降圧回路 ３ 内部メモリ回路 ４ ワード線駆動回路 ５ ＶPP発生回路 1 external power supply 2 step-down circuit 3 internal memory circuit 4 word line drive circuit 5 VPP generation circuit
Claims (5)
で降圧する降圧回路と、 前記降圧回路に接続された内部メモリ回路と、 前記外部電源が接続されたワード線駆動回路とから成る
ことを特徴とする半導体記憶装置。An external power supply; a step-down circuit that steps down an external power supply voltage supplied from the external power supply to a desired potential; an internal memory circuit connected to the step-down circuit; and a word line connected to the external power supply A semiconductor memory device comprising a driving circuit.
続されていることを特徴とする請求項１に記載の半導体
記憶装置。2. The semiconductor memory device according to claim 1, wherein a capacitor in a booster circuit is connected to said step-down circuit.
で昇圧する昇圧回路と、 前記昇圧回路に接続されたワード線駆動回路とから成る
ことを特徴とする半導体記憶装置。3. An external power supply; an internal memory circuit to which the external power supply is connected; a booster circuit for boosting an external power supply voltage supplied from the external power supply to a desired potential; and a word line connected to the booster circuit A semiconductor memory device comprising a driving circuit.
で降圧する降圧回路と、 前記降圧回路に接続された内部メモリ回路と、 前記外部電源が接続されたワード線駆動回路とから成る
第１の半導体記憶装置と、 外部電源と、 前記外部電源が接続された内部メモリ回路と、 前記外部電源から供給される外部電源電圧を所望電位ま
で昇圧する昇圧回路と、 前記昇圧回路に接続されたワード線駆動回路とから成る
第２の半導体記憶装置とをマスク切り替えすることを特
徴とする半導体記憶装置の切り替え方法。4. An external power supply, a step-down circuit for stepping down an external power supply voltage supplied from the external power supply to a desired potential, an internal memory circuit connected to the step-down circuit, and a word line connected to the external power supply A first semiconductor memory device including a driving circuit; an external power supply; an internal memory circuit to which the external power supply is connected; a booster circuit that boosts an external power supply voltage supplied from the external power supply to a desired potential; A method of switching a semiconductor memory device, comprising mask-switching a second semiconductor memory device including a word line drive circuit connected to a booster circuit.
クル切り替えであることを特徴とする請求項４に記載の
半導体記憶装置の切り替え方法。5. The method according to claim 4, wherein the mask switching step is a metal reticle switching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001035366A JP2002237185A (en) | 2001-02-13 | 2001-02-13 | Semiconductor memory, and switching method of semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001035366A JP2002237185A (en) | 2001-02-13 | 2001-02-13 | Semiconductor memory, and switching method of semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002237185A true JP2002237185A (en) | 2002-08-23 |
Family
ID=18898816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001035366A Pending JP2002237185A (en) | 2001-02-13 | 2001-02-13 | Semiconductor memory, and switching method of semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002237185A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008243281A (en) * | 2007-03-27 | 2008-10-09 | Elpida Memory Inc | Power voltage generating circuit |
-
2001
- 2001-02-13 JP JP2001035366A patent/JP2002237185A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008243281A (en) * | 2007-03-27 | 2008-10-09 | Elpida Memory Inc | Power voltage generating circuit |
| US8493132B2 (en) | 2007-03-27 | 2013-07-23 | Elpida Memory, Inc. | Supply voltage generating circuit |
| US8860499B2 (en) | 2007-03-27 | 2014-10-14 | Ps4 Luxco S.A.R.L. | Supply voltage generating circuit |
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