JP4719425B2 - Two-stage internal voltage generation circuit and method - Google Patents

Two-stage internal voltage generation circuit and method Download PDF

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JP4719425B2
JP4719425B2 JP2004080708A JP2004080708A JP4719425B2 JP 4719425 B2 JP4719425 B2 JP 4719425B2 JP 2004080708 A JP2004080708 A JP 2004080708A JP 2004080708 A JP2004080708 A JP 2004080708A JP 4719425 B2 JP4719425 B2 JP 4719425B2
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チュン チェン，チエン
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本発明は集積回路における内部電圧生成回路、特に、消費電力が低く、低消費電力集積回路に適した二段階内部電圧生成回路に関する。   The present invention relates to an internal voltage generation circuit in an integrated circuit, and more particularly to a two-stage internal voltage generation circuit that has low power consumption and is suitable for a low power consumption integrated circuit.

科学技術の進歩及び環境保護の意識が高まることにつれて、集積回路が高速度化かつ低消費電力化に向かって進化しつつある。ゆえに、各種電子製品がさらに省電力化、軽量化、薄型化される一方、それらの機能が従来より向上されている。   Integrated circuits are evolving toward higher speeds and lower power consumption as science and technology advance and environmental protection is increased. Therefore, various electronic products are further reduced in power consumption, weight and thickness, while their functions are improved compared to the conventional ones.

低消費電力の集積回路のうち、例えば、ＤＲＡＭ（Ｄｉｒｅｃｔ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）に関して、いかに低消費電力化を達成することができるかは、回路設計上の一つ課題となっている。特に、ＤＲＡＭの応用はパーソナル・コンピュータにとどまらず、消費性電子製品にも及んでいるので、低消費電力化ための回路設計は更に不可欠になる。   Of the integrated circuits with low power consumption, for example, how to achieve low power consumption for a DRAM (Direct Random Access Memory) is a problem in circuit design. In particular, since the application of DRAM extends not only to personal computers but also to consumer electronic products, circuit design for reducing power consumption becomes even more indispensable.

図１は、従来の内部電圧生成回路の一例を示す回路図である。   FIG. 1 is a circuit diagram showing an example of a conventional internal voltage generation circuit.

図１に示す内部電圧生成回路１０は、固定した電圧を安定に生成するための内部電圧源であり、生成された内部電圧ＶＩＮＴが外部電圧源から供給される外部電圧ＶＥＸＴと異なる。例えば、外部電圧ＶＥＸＴは２．３Ｖから２．７Ｖの範囲に変動するのに対して、内部電圧ＶＩＮＴは２．１Ｖに固定される。   The internal voltage generation circuit 10 shown in FIG. 1 is an internal voltage source for stably generating a fixed voltage, and the generated internal voltage VINT is different from the external voltage VEXT supplied from the external voltage source. For example, the external voltage VEXT varies from 2.3V to 2.7V, while the internal voltage VINT is fixed at 2.1V.

図１に示すように、内部電圧生成回路１０は、比較器１２、ＮＭＯＳパワートランジスタ１４、抵抗Ｒ１、及び抵抗Ｒ２からなる。内部電圧生成回路１０は、フィードバック回路を有し、該フィードバック回路は、抵抗Ｒ１と抵抗Ｒ２により、ＮＭＯＳパワートランジスタ１４から出力される内部電圧ＶＩＮＴを分圧し、フィードバック電圧を比較器１２に出力する。比較器１２は、フィードバック電圧と基準電圧ＶＲＥＦＤＣとを比較し、そしてＮＭＯＳパワートランジスタ１４を制御し、所望の内部電圧ＶＩＮＴを出力する。   As shown in FIG. 1, the internal voltage generation circuit 10 includes a comparator 12, an NMOS power transistor 14, a resistor R1, and a resistor R2. The internal voltage generation circuit 10 includes a feedback circuit. The feedback circuit divides the internal voltage VINT output from the NMOS power transistor 14 by the resistors R1 and R2, and outputs the feedback voltage to the comparator 12. The comparator 12 compares the feedback voltage with the reference voltage VREFDC, controls the NMOS power transistor 14, and outputs a desired internal voltage VINT.

従来の内部電圧生成回路１０において、抵抗Ｒ１と抵抗Ｒ２が直列され、かつ、その両端部が内部電源とグラウンドに接続されているので、かなりの直流電流を消耗する。具体的に、この回路が動作すると、必ず相当な電力を消費する。この種の内部電圧生成回路をＤＲＡＭに使う場合、また、その消費直流電流が６００μＡであるとすれば、ＤＲＡＭがリフレッシュされる時に、ＤＲＡＭにおいて８組の内部電圧生成回路が動作するので、その消費した平均直流電流は、
（６００μＡ×８×１００ｎｓ）／１６μｓ＝３０μＡとなる。 In the conventional internal voltage generation circuit 10, the resistor R1 and the resistor R2 are connected in series, and both ends thereof are connected to the internal power source and the ground, so that a considerable direct current is consumed. Specifically, when this circuit operates, it always consumes considerable power. When this type of internal voltage generation circuit is used in a DRAM, and if the consumption DC current is 600 μA, when the DRAM is refreshed, eight sets of internal voltage generation circuits operate in the DRAM. The average DC current
(600 μA × 8 × 100 ns) / 16 μs = 30 μA.

この消費電流が非常に大きいので、この種のＤＲＡＭは低消費電力集積回路と言えない。即ち、従来の内部電圧生成回路１０は低消費電力化に適しない。   Since this current consumption is very large, this type of DRAM cannot be said to be a low power consumption integrated circuit. That is, the conventional internal voltage generation circuit 10 is not suitable for low power consumption.

本発明の目的は、内部電圧生成回路の消費電力を低減し、低消費電力集積回路に適した内部電圧生成回路及び方法を提供することにある。   An object of the present invention is to provide an internal voltage generation circuit and method suitable for a low power consumption integrated circuit by reducing the power consumption of the internal voltage generation circuit.

以上の目的を達成するために、本発明の二段階内部電圧生成回路は、入力された外部電圧に応じて、第１の内部電圧を生成する第１の内部電圧生成回路、及び前記第１の内部電圧生成回路より消費電力が低く、第２の内部電圧を生成する第２の内部電圧生成回路を有し、前記第２の内部電圧が安定した後に、前記第１の内部電圧生成回路は前記第１の内部電圧の生成を停止する。   In order to achieve the above object, a two-stage internal voltage generation circuit according to the present invention includes a first internal voltage generation circuit that generates a first internal voltage according to an input external voltage, and the first internal voltage generation circuit. It has a second internal voltage generation circuit that consumes less power than the internal voltage generation circuit and generates a second internal voltage, and after the second internal voltage has stabilized, the first internal voltage generation circuit The generation of the first internal voltage is stopped.

本発明の最適な実施例として、前記第２の内部電圧生成回路は、第１の制御信号に基づき、前記外部電圧を昇圧し、昇圧電圧を出力する電圧昇圧生成回路、前記電圧昇圧生成回路に接続され、第２の制御信号に基づき、前記昇圧電圧を降圧し安定させ、入力ゲート電圧を出力する入力ゲート電圧生成回路、及び前記入力ゲート電圧生成回路に接続され、前記入力ゲート電圧に基づき、前記第２の内部電圧を出力する電力出力回路を有する。   As an optimal embodiment of the present invention, the second internal voltage generating circuit boosts the external voltage based on a first control signal, and outputs a boosted voltage to the voltage boosting generating circuit. Connected to the input gate voltage generating circuit for reducing and stabilizing the boosted voltage and outputting an input gate voltage based on the second control signal, and the input gate voltage generating circuit, and based on the input gate voltage, A power output circuit configured to output the second internal voltage;

前記第１の内部電圧生成回路は、第３の制御信号に基づき、前記第１の内部電圧の生成を停止する。   The first internal voltage generation circuit stops generating the first internal voltage based on a third control signal.

前記電力出力回路は、パワートランジスタであり、具体的に、ＮＭＯＳパワートランジスタである。   The power output circuit is a power transistor, specifically, an NMOS power transistor.

本発明の二段階内部電圧生成方法は、第１の内部電圧生成回路と、当該第１の内部電圧生成回路より消費電力が低い第２の内部電圧生成回路とを備えた二段階内部電圧生成回路による内部電圧を生成する方法であって、入力された外部電圧に応じて前記第１の内部電圧生成回路が第１の内部電圧を生成する工程、前記第２の内部電圧生成回路は第２の内部電圧を生成する工程、及び前記第２の内部電圧が安定した後、前記第１の内部電圧生成回路は前記第１の内部電圧の生成を停止する工程を有する。   A two-stage internal voltage generation method according to the present invention includes a first internal voltage generation circuit and a second internal voltage generation circuit that consumes less power than the first internal voltage generation circuit. In which the first internal voltage generation circuit generates the first internal voltage in accordance with the input external voltage, and the second internal voltage generation circuit includes the second internal voltage generation circuit. A step of generating an internal voltage, and a step of stopping the generation of the first internal voltage by the first internal voltage generation circuit after the second internal voltage is stabilized.

本発明の最適な実施例として、前記第２の内部電圧生成回路により前記第２の内部電圧を生成する工程は、第１の制御信号に基づき、前記外部電圧を昇圧し、前記昇圧電圧を出力する工程、第２の制御信号に基づき、前記昇圧電圧を降圧し安定させ、前記入力ゲート電圧を出力する工程、及び前記入力ゲート電圧に基づき、前記第２の内部電圧を出力する工程を有する。   As an optimal embodiment of the present invention, the step of generating the second internal voltage by the second internal voltage generating circuit boosts the external voltage and outputs the boosted voltage based on a first control signal. A step of reducing and stabilizing the boosted voltage based on a second control signal, outputting the input gate voltage, and a step of outputting the second internal voltage based on the input gate voltage.

以上の本発明は、二段階式の内部電圧生成回路構造を採用し、消費電力の高い第１の内部電圧生成回路が先に安定した第１の内部電圧を生成し、消費電力の低い第２の内部電圧生成回路が生成した第２の内部電圧が安定した後に、第１の内部電圧生成回路は第１の内部電圧の生成を停止する。   The present invention employs a two-stage internal voltage generation circuit structure, and the first internal voltage generation circuit with high power consumption generates the first stable internal voltage first, and the second with low power consumption. After the second internal voltage generated by the first internal voltage generation circuit is stabilized, the first internal voltage generation circuit stops generating the first internal voltage.

以上の本発明により、内部電圧生成回路の消費電力を低減させ、低消費電力集積回路に適した内部電圧生成回路を提供することができる。   According to the present invention described above, it is possible to provide an internal voltage generation circuit suitable for a low power consumption integrated circuit by reducing the power consumption of the internal voltage generation circuit.

本発明の以上の目的、特徴及び利点をより明確にするために、次に添付した図面を参照しながら、本発明の好適な実施形態を詳細に説明する。   In order to make the above objects, features and advantages of the present invention clearer, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図２は本発明の二段階内部電圧生成回路の一例を示す回路図である。   FIG. 2 is a circuit diagram showing an example of the two-stage internal voltage generation circuit of the present invention.

図２に示す二段階内部電圧生成回路は、第１の内部電圧生成回路１００と第２の内部電圧生成回路２００とを備えている。第２の内部電圧生成回路２００は、第１の内部電圧生成回路１００より消費電力が低い。例えば、動作時に第１の内部電圧生成回路１００が消費する直流電流は６００μＡであり、この第１の内部電圧生成回路１００をＤＲＡＭに使うとすると、ＤＲＡＭがリフレッシュされる時に、ＤＲＡＭにおいて８組の第１の内部電圧生成回路１００が動作し、その消費した平均直流電流は３０μＡとなる。   The two-stage internal voltage generation circuit shown in FIG. 2 includes a first internal voltage generation circuit 100 and a second internal voltage generation circuit 200. The second internal voltage generation circuit 200 consumes less power than the first internal voltage generation circuit 100. For example, the DC current consumed by the first internal voltage generation circuit 100 during operation is 600 μA. If the first internal voltage generation circuit 100 is used in a DRAM, when the DRAM is refreshed, eight sets of the DC current are consumed in the DRAM. The first internal voltage generation circuit 100 operates and the consumed average DC current is 30 μA.

これに対して、第２の内部電圧生成回路２００を採用した場合は、平均直流電流消費は僅か０．５μＡであるとの計算結果が得られた。   On the other hand, when the second internal voltage generation circuit 200 was employed, a calculation result was obtained that the average DC current consumption was only 0.5 μA.

第１の内部電圧生成回路１００は、第１の内部電圧源を提供し、安定した第１の内部電圧ＶＩＮＴ１を出力する。電源が供給された時に、外部電圧ＶＥＸＴが印加されると、第１の内部電圧生成回路１００は安定した第１の内部電圧ＶＩＮＴ１を出力する。   The first internal voltage generation circuit 100 provides a first internal voltage source and outputs a stable first internal voltage VINT1. When the external voltage VEXT is applied when the power is supplied, the first internal voltage generation circuit 100 outputs a stable first internal voltage VINT1.

好ましくは、第１の内部電圧生成回路１００は第３の制御信号ＣＨＲＤＹ３に基づいて、第１の内部電圧ＶＩＮＴ１の生成を停止する。   Preferably, the first internal voltage generation circuit 100 stops generating the first internal voltage VINT1 based on the third control signal CHRDY3.

第２の内部電圧生成回路２００は、第２の内部電圧源を提供し、安定した第２の内部電圧ＶＩＮＴ２を出力する。   The second internal voltage generation circuit 200 provides a second internal voltage source and outputs a stable second internal voltage VINT2.

本発明の一つの特徴は、第２の内部電圧ＶＩＮＴ２が安定した後に、第１の内部電圧生成回路１００は第３の制御信号ＣＨＲＤＹ３に基づいて第１の内部電圧ＶＩＮＴ１の生成を停止することにある。   One feature of the present invention is that after the second internal voltage VINT2 is stabilized, the first internal voltage generation circuit 100 stops generating the first internal voltage VINT1 based on the third control signal CHRDY3. is there.

図３は図１に示す第１の内部電圧生成回路１００を示す回路図である。   FIG. 3 is a circuit diagram showing the first internal voltage generation circuit 100 shown in FIG.

第１の内部電圧生成回路１００は、比較器１０２、ＮＭＯＳトランジスタ１０４、第１の抵抗１０６、及び第２の抵抗１０８からなる。   The first internal voltage generation circuit 100 includes a comparator 102, an NMOS transistor 104, a first resistor 106, and a second resistor 108.

ＮＭＯＳトランジスタ１０４は、その第１の不純物領域（ソース）に外部電圧ＶＥＸＴが入力され、その第２の不純物領域（ドレイン）からは第１の内部電圧ＶＩＮＴ１が出力される。   In the NMOS transistor 104, the external voltage VEXT is input to the first impurity region (source), and the first internal voltage VINT1 is output from the second impurity region (drain).

第１の抵抗１０６の一端はＮＭＯＳトランジスタ１０４の第２の不純物領域（ドレイン）に接続され、第２の抵抗１０８の一端は第１の抵抗１０６の他端と接続し、フィードバック電圧を提供する。第２の抵抗１０８の他端がグラウンドに接続されている。   One end of the first resistor 106 is connected to the second impurity region (drain) of the NMOS transistor 104, and one end of the second resistor 108 is connected to the other end of the first resistor 106 to provide a feedback voltage. The other end of the second resistor 108 is connected to the ground.

第１の抵抗１０６と第２の抵抗１０８により、ＮＭＯＳトランジスタ１０４から出力された第１の内部電圧ＶＩＮＴ１が分圧され、フィードバック電圧として比較器１０２に出力される。比較器１０２は、そのフィードバック電圧と基準電圧ＶＲＥＦＤＣとを比較し、ＮＭＯＳトランジスタ１０４のゲート電極に制御電圧を出力し、ＮＭＯＳトランジスタ１０４を制御し、安定した第１の内部電圧ＶＩＮＴ１を出力する。   The first resistor 106 and the second resistor 108 divide the first internal voltage VINT1 output from the NMOS transistor 104 and output the divided voltage to the comparator 102 as a feedback voltage. The comparator 102 compares the feedback voltage with the reference voltage VREFDC, outputs a control voltage to the gate electrode of the NMOS transistor 104, controls the NMOS transistor 104, and outputs a stable first internal voltage VINT1.

図４は図１に示す第２の内部電圧生成回路２００を示す回路図である。   FIG. 4 is a circuit diagram showing the second internal voltage generation circuit 200 shown in FIG.

第２の内部電圧生成回路２００は、電圧昇圧生成回路２０２、入力ゲート電圧生成回路２０４、及び電力出力回路２０６を備えている。   The second internal voltage generation circuit 200 includes a voltage boost generation circuit 202, an input gate voltage generation circuit 204, and a power output circuit 206.

昇圧生成回路２０２は、第１の制御信号ＣＨＲＤＹ１に基づき、外部電圧ＶＥＸＴを昇圧し、昇圧電圧ＶＰＰを出力する。   The boost generation circuit 202 boosts the external voltage VEXT based on the first control signal CHRDY1, and outputs the boost voltage VPP.

入力ゲート電圧生成回路２０４は、電圧昇圧生成回路２０２に接続され、第２の制御信号ＣＨＲＤＹ２に基づき、昇圧電圧ＶＰＰを降圧し安定させ、入力ゲート電圧ｖＧＩを出力する。   The input gate voltage generation circuit 204 is connected to the voltage boost generation circuit 202, and lowers and stabilizes the boost voltage VPP based on the second control signal CHRDY2, and outputs the input gate voltage vGI.

電力出力回路２０６は、入力ゲート電圧生成回路２０４に接続され、入力ゲート電圧ｖＧＩに基づき、安定に第２の内部電圧ＶＩＮＴ２を出力する。   The power output circuit 206 is connected to the input gate voltage generation circuit 204, and stably outputs the second internal voltage VINT2 based on the input gate voltage vGI.

電力出力回路２０６として、ＮＭＯＳパワートランジスタ２０８を用いる。   An NMOS power transistor 208 is used as the power output circuit 206.

該パワートランジスタ２０８のゲート電極は、入力ゲート電圧生成回路２０４に接続され、第１の不純物領域（ドレイン）に外部電圧ＶＥＸＴが入力され、第２の不純物領域（ソース）から第２の内部電圧ＶＩＮＴ２が出力される。   The gate electrode of the power transistor 208 is connected to the input gate voltage generation circuit 204, the external voltage VEXT is input to the first impurity region (drain), and the second internal voltage VINT2 is supplied from the second impurity region (source). Is output.

上記のＮＭＯＳパワートランジスタ１０４と２０８は、周知のものであり、本発明はこれらに限定されない。安定した大きいパワーを供給できる他の素子を用いても良く、また、ＭＯＳ類のパワートランジスタを用いなくても良い。   The NMOS power transistors 104 and 208 are well known, and the present invention is not limited to these. Other elements capable of supplying a stable and large power may be used, and MOS power transistors may not be used.

図５は、図１に示す本実施形態の二段階内部電圧生成回路の動作を示すタイミングチャートである。   FIG. 5 is a timing chart showing the operation of the two-stage internal voltage generation circuit of the present embodiment shown in FIG.

図５に示すように、外部電圧ＶＥＸＴが入力されると、具体的に、外部電圧ＶＥＸＴが立ち上がるときに、第１の内部電圧生成回路１００が第１の内部電圧ＶＩＮＴ１を生成し、第１の内部電圧ＶＩＮＴ１が上昇する。   As shown in FIG. 5, when the external voltage VEXT is input, specifically, when the external voltage VEXT rises, the first internal voltage generation circuit 100 generates the first internal voltage VINT1, The internal voltage VINT1 rises.

続いて、第１の制御信号ＣＨＲＤＹ１がＯＮにセットされ、それに応じて、電圧昇圧生成回路２０２が昇圧電圧ＶＰＰを出力し、昇圧電圧ＶＰＰが上昇する。   Subsequently, the first control signal CHRDY1 is set to ON, and accordingly, the voltage boost generation circuit 202 outputs the boost voltage VPP, and the boost voltage VPP increases.

続いて、第２の制御信号ＣＨＲＤＹ２がＯＮにセットされ、それに応じて、入力ゲート電圧生成回路２０４が入力ゲート電圧ｖＧＩを出力する。電力出力回路２０６は、入力ゲート電圧ｖＧＩに基づき、第２の内部電圧ＶＩＮＴ２を安定に出力する。   Subsequently, the second control signal CHRDY2 is set to ON, and the input gate voltage generation circuit 204 outputs the input gate voltage vGI accordingly. The power output circuit 206 stably outputs the second internal voltage VINT2 based on the input gate voltage vGI.

その後、第１の内部電圧生成回路１００は、第３の制御信号ＣＨＲＤＹ３に基づき、第１の内部電圧ＶＩＮＴ１の生成を停止する。   Thereafter, the first internal voltage generation circuit 100 stops generating the first internal voltage VINT1 based on the third control signal CHRDY3.

以上のように、本発明は、二段階式の内部電圧生成回路構造を採用し、消費電力の高い第１の内部電圧生成回路１００が先に安定した第１の内部電圧ＶＩＮＴ１を生成し、消費電力の低い第２の内部電圧生成回路２００が生成した第２の内部電圧ＶＩＮＴ２が安定した後に、第１の内部電圧生成回路１００は第１の内部電圧ＶＩＮＴ１の生成を停止する。このように、内部電圧生成回路の消費電力を低減させることができる。   As described above, the present invention employs a two-stage internal voltage generation circuit structure, and the first internal voltage generation circuit 100 with high power consumption generates the first internal voltage VINT1 that has been stabilized first. After the second internal voltage VINT2 generated by the low-power second internal voltage generation circuit 200 is stabilized, the first internal voltage generation circuit 100 stops generating the first internal voltage VINT1. Thus, the power consumption of the internal voltage generation circuit can be reduced.

以上、本発明の好ましい実施形態を説明したが、本発明はこの実施形態に限定されず、本発明の趣旨を離脱しない限り、本発明に対するあらゆる変更は本発明の範囲に属する。   The preferred embodiment of the present invention has been described above, but the present invention is not limited to this embodiment, and all modifications to the present invention are within the scope of the present invention unless departing from the spirit of the present invention.

従来技術における内部電圧生成回路の一例を示す回路図である。It is a circuit diagram which shows an example of the internal voltage generation circuit in a prior art. 本発明の二段階内部電圧生成回路の一例を示す回路図である。It is a circuit diagram which shows an example of the two-step internal voltage generation circuit of this invention. 第１の内部電圧生成回路１００を示す回路図である。2 is a circuit diagram showing a first internal voltage generation circuit 100. FIG. 第２の内部電圧生成回路２００を示す回路図である。FIG. 6 is a circuit diagram showing a second internal voltage generation circuit 200. 本発明の二段階内部電圧生成回路の動作を示すタイミングチャートである。It is a timing chart which shows operation | movement of the two-step internal voltage generation circuit of this invention.

符号の説明Explanation of symbols

１０ 内部電圧生成回路
１２ 比較器
１４ ＮＭＯＳトランジスタ
１００ 第１の内部電圧生成回路
１０２ 比較器
１０４ ＮＭＯＳトランジスタ
１０６ 第１の抵抗
１０８ 第２の抵抗
２００ 第２の内部電圧生成回路
２０２ 電圧昇圧生成回路
２０４ 入力ゲート電圧生成回路
２０６ 電力出力回路
２０８ ＮＭＯＳトランジスタ DESCRIPTION OF SYMBOLS 10 Internal voltage generation circuit 12 Comparator 14 NMOS transistor 100 1st internal voltage generation circuit 102 Comparator 104 NMOS transistor 106 1st resistance 108 2nd resistance 200 2nd internal voltage generation circuit 202 Voltage boost generation circuit 204 Input Gate voltage generation circuit 206 Power output circuit 208 NMOS transistor

Claims (9)

入力された外部電圧に応じて、第１の内部電圧を生成する第１の内部電圧生成回路；及び
前記第１の内部電圧生成回路より消費電力が低く、第２の内部電圧を生成する第２の内部電圧生成回路；
を有し、
前記第２の内部電圧が安定した後に、前記第１の内部電圧生成回路は前記第１の内部電圧の生成を停止し、
前記第２の内部電圧生成回路は、
第１の制御信号に基づき、前記外部電圧を昇圧し、昇圧電圧を出力する電圧昇圧生成回路；
前記電圧昇圧生成回路に接続され、第２の制御信号に基づき、前記昇圧電圧を降圧し安定させ、入力ゲート電圧を出力する入力ゲート電圧生成回路；及び
前記入力ゲート電圧生成回路に接続され、前記入力ゲート電圧に基づき、前記第２の内部電圧を出力する電力出力回路；
を有する；
二段階内部電圧生成回路。 A first internal voltage generating circuit that generates a first internal voltage according to an input external voltage; and a second internal power generating circuit that generates a second internal voltage with lower power consumption than the first internal voltage generating circuit. Internal voltage generation circuit;
Have
After the second internal voltage is stabilized, the first internal voltage generation circuit stops generating the first internal voltage ;
The second internal voltage generation circuit includes:
A voltage boost generation circuit that boosts the external voltage and outputs a boosted voltage based on a first control signal;
An input gate voltage generation circuit connected to the voltage boost generation circuit and configured to step down and stabilize the boost voltage based on a second control signal and to output an input gate voltage; and
A power output circuit connected to the input gate voltage generation circuit and outputting the second internal voltage based on the input gate voltage;
Having:
Two-stage internal voltage generation circuit. 前記第１の内部電圧生成回路は、第３の制御信号に基づき、前記第１の内部電圧の生成を停止する；
請求項１に記載の二段階内部電圧生成回路。 The first internal voltage generation circuit stops generating the first internal voltage based on a third control signal;
The two-stage internal voltage generation circuit according to claim 1 . 前記第１の内部電圧生成回路が、前記外部電圧に応じて、前記第１の内部電圧を生成し；
前記電圧昇圧生成回路が、前記第１の制御信号に基づき、前記昇圧電圧を出力し；
前記入力ゲート電圧生成回路が、前記第２の制御信号に基づき、前記入力ゲート電圧を出力し；
前記電力出力回路が、前記入力ゲート電圧に基づき、前記第２の内部電圧を出力し；
前記第１の内部電圧生成回路は、前記第３の制御信号に基づき、前記第１の内部電圧の生成を停止する；
請求項２に記載の二段階内部電圧生成回路。 The first internal voltage generation circuit generates the first internal voltage in response to the external voltage;
The voltage boost generation circuit outputs the boost voltage based on the first control signal;
The input gate voltage generation circuit outputs the input gate voltage based on the second control signal;
The power output circuit outputs the second internal voltage based on the input gate voltage;
The first internal voltage generation circuit stops generating the first internal voltage based on the third control signal;
The two-stage internal voltage generation circuit according to claim 2 . 前記電力出力回路は、パワートランジスタであり；
当該パワートランジスタのゲート電極に前記入力ゲート電圧が入力され、当該パワートランジスタの第１の不純物領域に前記外部電圧が入力され、当該パワートランジスタの第２の不純物領域から前記第２の内部電圧が出力される：
請求項１に記載の二段階内部電圧生成回路。 The power output circuit is a power transistor;
The input gate voltage is input to the gate electrode of the power transistor, the external voltage is input to the first impurity region of the power transistor, and the second internal voltage is output from the second impurity region of the power transistor. Is:
The two-stage internal voltage generation circuit according to claim 1 . 前記パワートランジスタは、ＮＭＯＳパワートランジスタである：
請求項４に記載の二段階内部電圧生成回路。 The power transistor is an NMOS power transistor:
The two-stage internal voltage generation circuit according to claim 4 . 前記第１の内部電圧生成回路は、
フィードバック電圧と基準電圧とを比較し、制御信号を出力する比較器；
ゲート電極に前記制御信号が入力され、第１の不純物領域に前記外部電圧が入力され、第２の不純物領域から前記第１の内部電圧が出力されるパワートランジスタ；
一端が前記パワートランジスタの第２の不純物領域に接続される第１の抵抗；
一端が前記第１の抵抗の他端と接続され前記フィードバック電圧を出力し、他端がグラウンドに接続される第２の抵抗；
を有する請求項１に記載の二段階内部電圧生成回路。 The first internal voltage generation circuit includes:
A comparator that compares the feedback voltage with a reference voltage and outputs a control signal;
A power transistor in which the control signal is input to a gate electrode, the external voltage is input to a first impurity region, and the first internal voltage is output from a second impurity region;
A first resistor having one end connected to the second impurity region of the power transistor;
A second resistor having one end connected to the other end of the first resistor to output the feedback voltage and the other end connected to ground;
The two-stage internal voltage generation circuit according to claim 1, comprising: 第１の内部電圧生成回路と、当該第１の内部電圧生成回路より消費電力が低い第２の内部電圧生成回路とを備えた二段階内部電圧生成回路による内部電圧を生成する方法であって：
入力された外部電圧に応じて、前記第１の内部電圧生成回路により第１の内部電圧を生成する工程；
前記第２の内部電圧生成回路により、第２の内部電圧を生成する工程；及び
前記第２の内部電圧が安定した後に、前記第１の内部電圧生成回路により前記第１の内部電圧の生成を停止する工程；
を有し、
前記第２の内部電圧生成回路により前記第２の内部電圧を生成する工程は、
第１の制御信号に基づき、前記外部電圧を昇圧し、前記昇圧電圧を出力する工程；
第２の制御信号に基づき、前記昇圧電圧を降圧し安定させ、前記入力ゲート電圧を出力する工程；及び
前記入力ゲート電圧に基づき、前記第２の内部電圧を出力する工程；
を有する；
二段階内部電圧生成方法。 A method of generating an internal voltage by a two-stage internal voltage generation circuit comprising a first internal voltage generation circuit and a second internal voltage generation circuit that consumes less power than the first internal voltage generation circuit:
Generating a first internal voltage by the first internal voltage generation circuit according to the input external voltage;
Generating a second internal voltage by the second internal voltage generation circuit; and generating the first internal voltage by the first internal voltage generation circuit after the second internal voltage has stabilized. Stopping the process;
I have a,
The step of generating the second internal voltage by the second internal voltage generation circuit includes:
Boosting the external voltage and outputting the boosted voltage based on a first control signal;
Reducing and stabilizing the boosted voltage based on a second control signal and outputting the input gate voltage; and
Outputting the second internal voltage based on the input gate voltage;
Having:
Two-stage internal voltage generation method. 前記第１の内部電圧生成回路は、第３の制御信号に基づき、前記第１の内部電圧の生成を停止する
請求項７に記載の二段階内部電圧生成方法。 The two-stage internal voltage generation method according to claim 7 , wherein the first internal voltage generation circuit stops generating the first internal voltage based on a third control signal. 前記第１の内部電圧生成回路が、前記外部電圧に応じて、前記第１の内部電圧を生成し；
前記第２の内部電圧生成回路が、第１の制御信号に基づき、前記外部電圧を昇圧し、前記昇圧電圧を出力し；
前記第２の内部電圧生成回路が、第２の制御信号に基づき、前記昇圧電圧を降圧し安定させ、前記入力ゲート電圧を出力し；
前記第２の内部電圧生成回路が、前記入力ゲート電圧に基づき、前記第２の内部電圧を出力し；
前記第１の内部電圧生成回路は、前記第３の制御信号に基づき、前記第１の内部電圧の生成を停止する；
請求項８に記載の二段階内部電圧生成方法。 The first internal voltage generation circuit generates the first internal voltage in response to the external voltage;
The second internal voltage generating circuit boosts the external voltage and outputs the boosted voltage based on a first control signal;
The second internal voltage generation circuit steps down and stabilizes the boosted voltage based on a second control signal, and outputs the input gate voltage;
The second internal voltage generation circuit outputs the second internal voltage based on the input gate voltage;
The first internal voltage generation circuit stops generating the first internal voltage based on the third control signal;
The two-stage internal voltage generation method according to claim 8 .
JP2004080708A 2004-03-19 2004-03-19 Two-stage internal voltage generation circuit and method Expired - Lifetime JP4719425B2 (en)

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