JP2001274376A - Low-resistant garium nitride buffer layer - Google Patents
Low-resistant garium nitride buffer layerInfo
- Publication number
- JP2001274376A JP2001274376A JP2000084613A JP2000084613A JP2001274376A JP 2001274376 A JP2001274376 A JP 2001274376A JP 2000084613 A JP2000084613 A JP 2000084613A JP 2000084613 A JP2000084613 A JP 2000084613A JP 2001274376 A JP2001274376 A JP 2001274376A
- Authority
- JP
- Japan
- Prior art keywords
- gan
- buffer layer
- layer
- algan
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 150000001875 compounds Chemical class 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 15
- 229910002601 GaN Inorganic materials 0.000 description 50
- 239000013078 crystal Substances 0.000 description 27
- 239000000758 substrate Substances 0.000 description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 16
- 239000002184 metal Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 230000005533 two-dimensional electron gas Effects 0.000 description 9
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 4
- 238000002128 reflection high energy electron diffraction Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 125000002524 organometallic group Chemical group 0.000 description 3
- 241000272522 Anas Species 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000002484 cyclic voltammetry Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は基板の上にエピタキ
シャル成長法で成膜される低抵抗ＧａＮ系緩衝層に関
し、更に詳しくは、ＦＥＴやＭＥＳＦＥＴのような各種
のＧａＮ系半導体素子の製造時に採用することにより、
当該半導体素子の基板裏面への動作電極の形成を可能に
した低抵抗ＧａＮ系緩衝層に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-resistance GaN-based buffer layer formed on a substrate by an epitaxial growth method, and more particularly to a method of manufacturing various GaN-based semiconductor devices such as FETs and MESFETs. By doing
The present invention relates to a low-resistance GaN-based buffer layer capable of forming an operation electrode on the back surface of a substrate of the semiconductor device.
【０００２】[0002]
【従来の技術】例えばＧａＮ系材料でＦＥＴを製造する
場合には、基板の上に例えばＭＯＣＶＤ法やＭＢＥ法の
ようなエピタキシャル成長法で所定の組成を有するＧａ
Ｎ系結晶層を順次積層してＦＥＴ層構造を形成すること
が必要である。その場合、ＧａＮ系材料と格子定数が一
致する基板材料は皆無であるため、異種材料から成る基
板が結晶成長用の基板として用いられている。通常はサ
ファイア基板が用いられている。2. Description of the Related Art For example, when an FET is manufactured from a GaN-based material, a Ga having a predetermined composition is formed on a substrate by an epitaxial growth method such as MOCVD or MBE.
It is necessary to form an FET layer structure by sequentially stacking N-type crystal layers. In this case, there is no substrate material whose lattice constant matches that of the GaN-based material, and thus a substrate made of a different material is used as a substrate for crystal growth. Usually, a sapphire substrate is used.
【０００３】しかしながら、このサファイア基板と結晶
成長するＧａＮ結晶との格子不整合率は２０％以上であ
るため、両者の格子不整合を緩和し、成膜されたＧａＮ
結晶における結晶欠陥を極力少なくすることを目的とし
て、サファイア基板の上には、一旦、緩衝層を成膜する
ことが行われている。通常、この緩衝層はノンドープの
状態で成膜され、そしてその上に所望する膜厚のｎ型Ｇ
ａＮ結晶層をｎ型活性層として成膜することによりＧａ
Ｎ系のＦＥＴ層構造が形成されることになる。However, since the lattice mismatch between the sapphire substrate and the GaN crystal that grows is 20% or more, the lattice mismatch between the GaN crystal and the grown GaN crystal is reduced, and
For the purpose of minimizing crystal defects in a crystal, a buffer layer is once formed on a sapphire substrate. Usually, this buffer layer is formed in a non-doped state, and an n-type G layer having a desired film thickness is formed thereon.
By forming an aN crystal layer as an n-type active layer, Ga
An N-based FET layer structure is formed.
【０００４】上記した緩衝層の成膜に関しては、従来か
ら次のような２段階成長法が適用されている。第１の方
法は、通常、ＭＯＣＶＤ法により、例えばトリエチルア
ルミニウム（ＴＥＡ）とアンモニア（ＮＨ3）を用い、
水素をキャリアガスとして用い、成長温度８００℃でサ
ファイア基板上に、一旦、厚み５nm程度の極薄なＡｌＮ
層を下部緩衝層として成膜し、ついで成長温度を１１０
０℃に上昇させ、トリメチルガリウム（ＴＭＧ）とアン
モニア（ＮＨ3）を用いて厚膜のノンドープＧａＮ結晶
層を上部緩衝層として前記ＡｌＮ層の上に成膜する方法
である。The following two-stage growth method has conventionally been applied to the formation of the buffer layer described above. The first method uses MOCVD, for example, using triethylaluminum (TEA) and ammonia (NH 3 ).
Using hydrogen as a carrier gas, an ultra-thin AlN having a thickness of about 5 nm is temporarily formed on a sapphire substrate at 800 ° C.
The layer is deposited as a lower buffer layer and then grown at a temperature of 110
This is a method in which the temperature is raised to 0 ° C. and a thick non-doped GaN crystal layer is formed as an upper buffer layer on the AlN layer using trimethylgallium (TMG) and ammonia (NH 3 ).
【０００５】また、第２の方法としては次のような方法
が適用されている。すなわち、ＭＯＣＶＤ法により、例
えばＴＭＧとＮＨ3を用い、水素をキャリアガスとして
用い、温度５００〜６００℃の低温下で厚み１〜２nm程
度の非晶質ＧａＮ層を下部緩衝層として成膜し、ついで
温度を１１００℃に上昇してエピタキシャル成長を行
い、前記非晶質ＧａＮ層の上に厚膜のノンドープＧａＮ
結晶層を上部緩衝層として成膜する方法である。The following method is applied as a second method. That is, an amorphous GaN layer having a thickness of about 1 to 2 nm is formed as a lower buffer layer at a low temperature of 500 to 600 ° C. by using, for example, TMG and NH 3 , using hydrogen as a carrier gas by MOCVD, Then, the temperature was increased to 1100 ° C. to perform epitaxial growth, and a thick non-doped GaN was formed on the amorphous GaN layer.
In this method, a crystal layer is formed as an upper buffer layer.
【０００６】このようにして成膜された従来のＧａＮ系
緩衝層は、結晶欠陥が多いという問題と、同時に、上部
緩衝層として成膜されている厚膜のノンドープＧａＮ結
晶層が高抵抗であるということに規定されて緩衝層全体
としては高抵抗になっているという問題を有している。The conventional GaN-based buffer layer formed as described above has a problem that it has many crystal defects, and at the same time, a thick non-doped GaN crystal layer formed as an upper buffer layer has high resistance. As a result, there is a problem that the overall resistance of the buffer layer is high.
【０００７】[0007]
【発明が解決しようとする課題】ところで、例えば縦型
のＧａＮ系ＦＥＴを製造しようとする場合には、基板と
して導電性材料から成る基板を用い、製造した素子の上
面と、下面（すなわち基板裏面）にそれぞれ動作電極を
形成することが必要になる。しかしながら、上記の従来
方法で形成したＦＥＴ構造においては、基板上に位置す
る緩衝層が高抵抗になっているため、基板の裏面に動作
電極を形成しても電極動作を示さないことになる。した
がって、縦型のＧａＮ系ＦＥＴを製造しようとする場合
には、緩衝層をノンドープの状態で、かつ低抵抗にする
ことが必要になる。When a vertical GaN-based FET is to be manufactured, for example, a substrate made of a conductive material is used as the substrate, and the upper and lower surfaces of the manufactured device (ie, the back surface of the substrate). ) Requires the formation of working electrodes. However, in the FET structure formed by the above-described conventional method, since the buffer layer located on the substrate has a high resistance, even if the working electrode is formed on the back surface of the substrate, no electrode operation is exhibited. Therefore, when attempting to manufacture a vertical GaN-based FET, it is necessary to make the buffer layer non-doped and have low resistance.
【０００８】本発明は、上記した要請に応えることがで
き、高純度であると同時に、低抵抗であるＧａＮ系緩衝
層の提供を目的とする。An object of the present invention is to provide a GaN-based buffer layer which can satisfy the above-mentioned demands and has a high purity and a low resistance.
【０００９】[0009]
【課題を解決するための手段】本発明者は上記した目的
を達成するために研究を重ねる過程で、ＨＥＭＴの場合
に代表されるように、互いに高純度である化合物半導体
のヘテロ接合界面には２次元電子ガス層が形成され、そ
の領域における電子は高い移動度を有するという事実に
着目した。そして、上記したＧａＮ系の緩衝層の場合で
も、複数の高純度なＧａＮ系材料を用いてヘテロ接合構
造を形成すれば、互いのヘテロ接合界面には２次元電子
ガス層が形成され、そのことにより、緩衝層を全体とし
て低抵抗化することが可能になるとの着想を抱き、その
着想に基づいて更に研究を重ねた結果、上記着想が正当
であることを確認し、本発明を開発するに至った。In order to achieve the above-mentioned object, the present inventor has repeatedly studied and found that a heterojunction interface between mutually pure compound semiconductors, as typified by HEMT, has been found. Attention was paid to the fact that a two-dimensional electron gas layer was formed, and the electrons in that region had high mobility. Even in the case of the GaN-based buffer layer described above, if a heterojunction structure is formed using a plurality of high-purity GaN-based materials, a two-dimensional electron gas layer is formed at the heterojunction interface between each other. Thus, the idea that it becomes possible to reduce the resistance of the buffer layer as a whole, and further studies based on the idea, as a result, confirmed that the idea is valid, and to develop the present invention Reached.
【００１０】すなわち、本発明の低抵抗ＧａＮ緩衝層
は、Ｇａを必須成分として含む窒化物系III−Ｖ族化合
物半導体から成る少なくとも２層の薄層をヘテロ接合し
た層構造になっていることを特徴とする。そして、この
ような層構造としては、ＡｌＧａＮ／ＧａＮ／ＡｌＧａ
Ｎ，ＧａＮ／ＡｌＧａＮ／ＧａＮ，ＧａＮ／ＩｎＧａＮ
／ＧａＮ，ＩｎＧａＮ／ＧａＮ／ＩｎＧａＮ，ＩｎＡｌ
ＧａＮ／ＧａＮ／ＩｎＡｌＧａＮ（ただし、ＩｎＡｌＧ
ａＮは、ＧａＮよりもバンドギャップエネルギーが大き
い組成になっている），ＧａＮ／ＩｎＡｌＧａＮ／Ｇａ
Ｎ，ＡｌＧａＮＰ／ＧａＮＰ／ＡｌＧａＮＰ，ＡｌＧａ
ＮＡｓ／ＧａＮＡｓ／ＡｌＧａＮＡｓ，ＡｌＧａＮＰ／
ＩｎＧａＮＰ／ＡｌＧａＮＰ，ＡｌＧａＮＡｓ／ＩｎＧ
ａＮＡｓ／ＡｌＧａＮＡｓのいずれかであることを好適
とする。That is, the low-resistance GaN buffer layer of the present invention has a layer structure in which at least two thin layers made of a nitride III-V compound semiconductor containing Ga as an essential component are heterojuncted. Features. And, as such a layer structure, AlGaN / GaN / AlGa
N, GaN / AlGaN / GaN, GaN / InGaN
/ GaN, InGaN / GaN / InGaN, InAl
GaN / GaN / InAlGaN (however, InAlG
aN has a composition in which the band gap energy is larger than that of GaN), GaN / InAlGaN / Ga
N, AlGaNP / GaNP / AlGaNP, AlGa
NAs / GaNAs / AlGaNAs, AlGaNP /
InGaNP / AlGaNP, AlGaNAs / InG
It is preferable that any one of aNAs / AlGaNAs is used.
【００１１】[0011]
【発明の実施の形態】以下、図面に基づいて本発明の緩
衝層を説明する。図１は、基板１の上に、後述する高純
度な緩衝層２が成膜され、更にその上に、ＳｉドープＧ
ａＮ結晶層のような同じく高純度な緩衝層２が成膜さ
れ、更にその上に、ＳｉドープＧａＮ結晶層のような同
じく高純度なｎ型活性層３が形成された断面構造を示
す。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a buffer layer according to the present invention will be described with reference to the drawings. FIG. 1 shows that a high-purity buffer layer 2 to be described later is formed on a substrate 1 and further a Si-doped G layer is formed thereon.
A cross-sectional structure is shown in which a similarly high-purity buffer layer 2 such as an aN crystal layer is formed, and a high-purity n-type active layer 3 such as a Si-doped GaN crystal layer is further formed thereon.
【００１２】ここで、基板１としては、例えばＳｉ，Ｓ
ｉＣ，ＧａＡｓ，ＧａＰ，ＩｎＰなどの基板のヘテロ接
合から成る層構造のような導電性材料から成る基板を用
いれば、この材料からは、ｎ型活性層３に上部電極を、
基板１の裏面に下部電極をそれぞれ形成することによ
り、縦型のＦＥＴを製造することができる。緩衝層２
は、全体として、第１緩衝層２Ａ、第２緩衝層２Ｂ、お
よび第３緩衝層２Ｃから成る３層構造になっていて、各
部分緩衝層の接合界面はヘテロ接合界面になっている。Here, for example, Si, S
If a substrate made of a conductive material such as a layer structure composed of a heterojunction of a substrate such as iC, GaAs, GaP, or InP is used, an upper electrode is formed on the n-type active layer 3 from this material.
By forming the lower electrodes on the back surface of the substrate 1 respectively, a vertical FET can be manufactured. Buffer layer 2
Has a three-layer structure composed of a first buffer layer 2A, a second buffer layer 2B, and a third buffer layer 2C as a whole, and the junction interface of each partial buffer layer is a hetero junction interface.
【００１３】そして、これら緩衝層２Ａ，２Ｂ，２Ｃ
は、Ｇａを必須成分として含む窒化物系III−Ｖ族化合
物半導体で構成されていて、図１の材料の場合、具体的
には、第１緩衝層２ＡはＡｌＧａＮ（Ａｌ：１５原子
％）結晶層、第２緩衝層２ＢはＧａＮ結晶層、第３緩衝
層２ＣはＡｌＧａＮ（Ａｌ：２０原子％）結晶層になっ
ている。The buffer layers 2A, 2B, 2C
Is made of a nitride III-V compound semiconductor containing Ga as an essential component. In the case of the material shown in FIG. 1, specifically, the first buffer layer 2A is made of AlGaN (Al: 15 atomic%) crystal. The second buffer layer 2B is a GaN crystal layer, and the third buffer layer 2C is an AlGaN (Al: 20 atomic%) crystal layer.
【００１４】この緩衝層２の場合、第１緩衝層２Ａと第
２緩衝層２Ｂの接合界面における第２緩衝層２Ｂ側には
２次元電子ガス層ｇ1が形成され、また、第２緩衝層２
Ｂと第３緩衝層２Ｃの接合界面における第２緩衝層２Ｂ
側にも２次元電子ガス層ｇ2が形成されることになる。
すなわち、２つの接合界面に対応して第２緩衝層２Ｂの
上下には２つの２次元電子ガス層が形成されている。[0014] In this case of the buffer layer 2, a first buffer layer 2A in the second buffer layer 2B side at a joint interface of the second buffer layer 2B 2-dimensional electron gas layer g 1 is formed, and the second buffer layer 2
B and second buffer layer 2B at the bonding interface between third buffer layer 2C
So that the two-dimensional electron gas layer g 2 in the side is formed.
That is, two two-dimensional electron gas layers are formed above and below the second buffer layer 2B corresponding to the two bonding interfaces.
【００１５】したがって、この第２緩衝層２Ｂを薄く成
膜することにより、上記した２次元電子ガス層ｇ1，ｇ2
の作用で、当該第２緩衝層２Ｂの上下方向における抵抗
を低めることが可能になる。具体的には、第２緩衝層２
Ｂの厚みを１０nm以下に設定すれば、上下方向における
導電性を発現せしめることができる。なお、第１緩衝層
２Ａと第３緩衝層２Ｃは、いずれも、第２緩衝層２Ｂと
の接合界面に２次元電子ガス層を形成するためにのみ成
膜されるものである。したがって、その材料としては、
第２緩衝層２Ｂにおける材料のバンドギャップエネルギ
ーよりも大きいバンドギャップエネルギーを有する組成
のものが選定される。そして、これら層２Ａ，２Ｃの厚
みは厚くなくてよく、上記した２次元電子ガス層の形成
に必要な厚みであれば充分である。むしろ、層２Ａ，２
Ｃの厚みを厚くすると、緩衝層全体の上下方向における
抵抗を高めるようになる。したがって、成膜時に層２
Ａ，２Ｃを平坦面にするということも勘案して３０〜５
０nm程度に設定すればよい。Therefore, by forming the second buffer layer 2B thinly, the above-described two-dimensional electron gas layers g 1 and g 2 are formed.
With this operation, the resistance of the second buffer layer 2B in the vertical direction can be reduced. Specifically, the second buffer layer 2
If the thickness of B is set to 10 nm or less, conductivity in the vertical direction can be exhibited. Each of the first buffer layer 2A and the third buffer layer 2C is formed only to form a two-dimensional electron gas layer at the bonding interface with the second buffer layer 2B. Therefore, as the material,
A composition having a band gap energy larger than the band gap energy of the material in the second buffer layer 2B is selected. The thicknesses of these layers 2A and 2C do not need to be large, and are sufficient as long as they are necessary for forming the above-described two-dimensional electron gas layer. Rather, layers 2A, 2
Increasing the thickness of C increases the resistance of the entire buffer layer in the vertical direction. Therefore, at the time of film formation, layer 2
30 to 5 in consideration of making A and 2C flat surfaces
It may be set to about 0 nm.
【００１６】このような作用効果を発揮する緩衝層２の
層構造としては、それを、第１緩衝層２Ａ／第２緩衝層
２Ｂ／第３緩衝層３Ｃで表現した場合、次のような層構
造を好適例としてあげることができる。すなわち、Ａｌ
ＧａＮ／ＧａＮ／ＡｌＧａＮ，ＧａＮ／ＡｌＧａＮ／Ｇ
ａＮ，ＧａＮ／ＩｎＧａＮ／ＧａＮ，ＩｎＧａＮ／Ｇａ
Ｎ／ＩｎＧａＮ，ＩｎＡｌＧａＮ／ＧａＮ／ＩｎＡｌＧ
ａＮ（ただし、ＩｎＡｌＧａＮは、ＧａＮよりもバンド
ギャップエネルギーが大きい組成になっている），Ｇａ
Ｎ／ＩｎＡｌＧａＮ／ＧａＮ，ＡｌＧａＮＰ／ＧａＮＰ
／ＡｌＧａＮＰ，ＡｌＧａＮＡｓ／ＧａＮＡｓ／ＡｌＧ
ａＮＡｓ，ＡｌＧａＮＰ／ＩｎＧａＮＰ／ＡｌＧａＮ
Ｐ，ＡｌＧａＮＡｓ／ＩｎＧａＮＡｓ／ＡｌＧａＮＡｓ
のいずれかである。The layer structure of the buffer layer 2 exhibiting the above-mentioned functions and effects can be expressed as a first buffer layer 2A / second buffer layer 2B / third buffer layer 3C. The structure can be given as a preferred example. That is, Al
GaN / GaN / AlGaN, GaN / AlGaN / G
aN, GaN / InGaN / GaN, InGaN / Ga
N / InGaN, InAlGaN / GaN / InAlG
aN (however, InAlGaN has a composition in which the band gap energy is larger than that of GaN), Ga
N / InAlGaN / GaN, AlGaNP / GaNP
/ AlGaNP, AlGaNAs / GaNAs / AlG
aNAs, AlGaNP / InGaNP / AlGaN
P, AlGaNAs / InGaNAs / AlGaNAs
Is one of
【００１７】[0017]
【実施例】実施例１ 図１で示した材料をＭＢＥ法で次のようにして製造し
た。導電性のＳｉ基板１の上に、成長温度７５０℃で、
まず、１原子層のＡｌを堆積させた。EXAMPLE 1 The material shown in FIG. 1 was produced by the MBE method as follows. At a growth temperature of 750 ° C. on a conductive Si substrate 1,
First, one atomic layer of Al was deposited.
【００１８】ついで、プラズマ化した窒素（３×１０-6
Torr）、金属Ｇａ（５×１０-7Torr）、金属Ａｌ（１×
１０-7Torr）、および金属Ｓｉ（１×１０-9Torr）を用
い、成長温度８００℃で厚み３nmのＳｉ添加ＡｌＧａＮ
（Ａｌ：１５原子％）結晶層を第１緩衝層２Ａとして成
膜した。この層の表面のストリークパターンを高速電子
線回折装置（ＲＨＥＥＤ）で観察したところ平坦である
ことが確認された。Next, the plasma-converted nitrogen (3 × 10 −6)
Torr), metal Ga (5 × 10 −7 Torr), metal Al (1 ×
10 -7 Torr) and metal Si (1 × 10 -9 Torr) at a growth temperature of 800 ° C. and a thickness of 3 nm with Si-added AlGaN.
A (Al: 15 atomic%) crystal layer was formed as the first buffer layer 2A. When the streak pattern on the surface of this layer was observed with a high-speed electron beam diffractometer (RHEED), it was confirmed that the layer was flat.
【００１９】ついで、プラズマ化した窒素（３×１０-6
Torr）、金属Ｇａ（５×１０-7Torr）のみを用いて上記
第１緩衝層２Ａの上に厚み３０nmのＧａＮ結晶層を第２
緩衝層２Ｂとして成膜した。ＲＨＥＥＤ観察によればこ
の層の表面も平坦であった。更に、上記ガス源に金属Ａ
ｌ（２×１０-7Torr）を加えてＭＢＥ法を行い、上記第
２緩衝層２Ｂの上に厚み３nmのＡｌＧａＮ（Ａｌ：２０
原子％）結晶層を第３緩衝層２Ｃとして成膜した。ＲＨ
ＥＥＤ観察によればこの層の表面も平坦であった。Then, the plasma nitrogen (3 × 10 −6)
Torr) and a metal Ga (5 × 10 −7 Torr) alone to form a 30-nm thick GaN crystal layer on the first buffer layer 2A.
A film was formed as the buffer layer 2B. According to RHEED observation, the surface of this layer was also flat. Further, metal A is used as the gas source.
1 (2 × 10 −7 Torr) and the MBE method is performed, and a 3 nm thick AlGaN (Al: 20: 20) is formed on the second buffer layer 2B.
(Atomic%) A crystal layer was formed as the third buffer layer 2C. RH
According to EED observation, the surface of this layer was also flat.
【００２０】ついで、プラズマ化した窒素（５×１０-5
Torr）と金属Ｇａ（８×１０-7Torr）を用い、ｎ型ドー
パントとして金属Ｓｉ（５×１０-8Torr）を用い、成長
温度８５０℃で上記第３緩衝層２Ｃの上に厚み３０nmの
ＳｉドープＧａＮ結晶層をｎ型活性層３として成膜し
た。得られた材料につき、Ｃ−Ｖ測定を行って、緩衝層
のあるヘテロ接合付近のキャリア濃度を調べたところ、
緩衝層２とｎ型活性層３との界面におけるキャリア濃度
は３×１０18cm-3であり、充分に上下方向の導電性を有
することが確認された。このことは、緩衝層に２次元電
子ガス層が形成されていることを根拠づけるものであ
る。Then, the plasma-converted nitrogen (5 × 10 −5)
Torr) and metal Ga (8 × 10 −7 Torr), metal Si (5 × 10 −8 Torr) as an n-type dopant, and a growth temperature of 850 ° C. and a thickness of 30 nm on the third buffer layer 2C. A Si-doped GaN crystal layer was formed as an n-type active layer 3. The obtained material was subjected to CV measurement to examine the carrier concentration near the heterojunction with the buffer layer.
The carrier concentration at the interface between the buffer layer 2 and the n-type active layer 3 is 3 × 10 18 cm -3, it was confirmed that sufficiently has a vertical conductivity. This is based on the fact that the two-dimensional electron gas layer is formed on the buffer layer.
【００２１】実施例２ ＭＢＥ法により、導電性のＳｉ基板１の上に成長温度７
００℃で、まず、１原子層のＧａを堆積させた。つい
で、プラズマ化した窒素（３×１０-6Torr）、金属Ｇａ
（５×１０-7Torr）、および金属Ｓｉ（１×１０-9Tor
r）を用い、成長温度８００℃で厚み３nmのＳｉ添加Ｇ
ａＮ結晶層を第１緩衝層２Ａとして成膜した。この層の
表面のストリークパターンを高速電子線回折装置（ＲＨ
ＥＥＤ）で観察したところ平坦であることが確認され
た。Example 2 A growth temperature of 7 was formed on a conductive Si substrate 1 by MBE.
At 00 ° C., one atomic layer of Ga was first deposited. Next, plasma-converted nitrogen (3 × 10 −6 Torr), metal Ga
(5 × 10 −7 Torr) and metallic Si (1 × 10 −9 Torr)
r), a 3 nm-thick Si-added G at a growth temperature of 800 ° C.
An aN crystal layer was formed as the first buffer layer 2A. The streak pattern on the surface of this layer is converted to a high-speed electron beam diffractometer (RH
Observation by EED) confirmed that the surface was flat.
【００２２】ついで、プラズマ化した窒素（３×１０-6
Torr）、金属Ｇａ（８×１０-7Torr）および金属Ａｌ
（１×１０-7Torr）を用いて上記第１緩衝層２Ａの上に
厚み３０nmのＡｌＧａＮ（Ａｌ：１５原子％）結晶層を
第２緩衝層２Ｂとして成膜した。ＲＨＥＥＤ観察によれ
ばこの層の表面も平坦であった。ついで、金属Ａｌの供
給を絶ってＭＢＥ法を行い、上記第２緩衝層２Ｂの上に
厚み３nmのＧａＮ結晶層を第３緩衝層２Ｃとして成膜し
た。ＲＨＥＥＤ観察によればこの層の表面も平坦であっ
た。Next, the plasma-converted nitrogen (3 × 10 −6)
Torr), metal Ga (8 × 10 −7 Torr) and metal Al
An AlGaN (Al: 15 atomic%) crystal layer having a thickness of 30 nm was formed as a second buffer layer 2B on the first buffer layer 2A using (1 × 10 −7 Torr). According to RHEED observation, the surface of this layer was also flat. Then, the supply of metal Al was cut off to perform the MBE method, and a GaN crystal layer having a thickness of 3 nm was formed as a third buffer layer 2C on the second buffer layer 2B. According to RHEED observation, the surface of this layer was also flat.
【００２３】そして、プラズマ化した窒素（５×１０-5
Torr）と金属Ｇａ（８×１０-7Torr）を用い、ｎ型ドー
パントとして金属Ｓｉ（５×１０-8Torr）を用い、成長
温度８５０℃で上記第３緩衝層２Ｃの上に厚み３０nmの
ＳｉドープＧａＮ結晶層をｎ型活性層３として成膜し
た。得られた材料につき、Ｃ−Ｖ測定を行って、緩衝層
付近のキャリア濃度を調べたところ、緩衝層２とｎ型活
性層３との界面におけるキャリア濃度は５×１０18cm-3
であり、充分に上下方向の導電性を有することが確認さ
れた。Then, plasma-converted nitrogen (5 × 10 −5)
Torr) and metal Ga (8 × 10 −7 Torr), metal Si (5 × 10 −8 Torr) as an n-type dopant, and a growth temperature of 850 ° C. and a thickness of 30 nm on the third buffer layer 2C. A Si-doped GaN crystal layer was formed as an n-type active layer 3. The obtained material was subjected to CV measurement to check the carrier concentration near the buffer layer. As a result, the carrier concentration at the interface between the buffer layer 2 and the n-type active layer 3 was 5 × 10 18 cm −3.
It was confirmed that the film had sufficient vertical conductivity.
【００２４】なお、上記実施例において、ＧａＮ結晶層
の成膜用窒素源としてはラジカル化した窒素やアンモニ
アを用いてもよく、Ｇａ源としてはトリメチルガリウム
（ＴＭＧ）やトリエチルガリウム（ＴＥＧ）などの有機
金属ガスを用い、Ａｌ源としてはトリメチルアルミニウ
ム（ＴＭＡ）やトリエチルアルミニウム（ＴＥＡ）など
の有機金属ガスを用いてもよく、また、不純物としては
Ｓｉに代えてシランガスを用いてもよい。In the above embodiment, radicalized nitrogen or ammonia may be used as a nitrogen source for forming the GaN crystal layer, and a Ga source such as trimethylgallium (TMG) or triethylgallium (TEG) may be used. An organometallic gas may be used, and an organometallic gas such as trimethylaluminum (TMA) or triethylaluminum (TEA) may be used as an Al source, and silane gas may be used instead of Si as an impurity.
【００２５】更に、上記実施例では、エピタキシャル成
長法としてＭＢＥ法を採用したが、上記した有機金属ガ
スを用いたＭＯＣＶＤ法を適用しても同様の結果をえる
ことができる。Further, in the above embodiment, the MBE method is adopted as the epitaxial growth method. However, the same result can be obtained by applying the MOCVD method using the above-mentioned organometallic gas.
【００２６】[0026]
【発明の効果】以上の説明で明らかなように、本発明の
低抵抗ＧａＮ系緩衝層は、高純度の化合物半導体のヘテ
ロ接合界面に形成される２次元電子ガス層を積極的に活
用したものである。したがって、この緩衝層を用いるこ
とにより、縦型のＧａＮ系ＦＥＴやＧａＮ系ＭＥＳＦＥ
Ｔの製造が可能となり、その工業的価値は大である。As is apparent from the above description, the low-resistance GaN-based buffer layer of the present invention utilizes a two-dimensional electron gas layer formed at the heterojunction interface of a high-purity compound semiconductor. It is. Therefore, by using this buffer layer, a vertical GaN-based FET or a GaN-based MESFE
T can be manufactured, and its industrial value is great.
【図１】本発明の緩衝層を用いた層構造を示す断面図で
ある。FIG. 1 is a sectional view showing a layer structure using a buffer layer of the present invention.
１ 結晶成長用の基板（導電性Ｓｉ基板） ２ 緩衝層 ２Ａ 第１緩衝層（ＡｌＧａＮ） ２Ｂ 第２緩衝層（ＧａＮ） ２Ｃ 第３緩衝層（ＡｌＧａＮ） ３ ｎ型活性層（ＳｉドープＧａＮ） Reference Signs List 1 Crystal growth substrate (conductive Si substrate) 2 Buffer layer 2A First buffer layer (AlGaN) 2B Second buffer layer (GaN) 2C Third buffer layer (AlGaN) 3 n-type active layer (Si-doped GaN)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 33/00 Ｈ０１Ｓ 5/32 Ｆターム(参考） 4G077 AA03 BE11 BE15 BE42 BE45 DA05 DB08 ED06 EF03 EF04 HA06 5F041 AA40 CA34 CA40 5F073 CA07 CA17 CB04 CB07 DA05 DA06 5F102 GB01 GC01 GD01 GJ03 GJ04 GJ05 GJ06 GK08 GQ01 HC01 5F103 AA04 DD01 GG01 HH03 HH04 JJ03 KK01 LL08 RR05 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (reference) H01L 33/00 H01S 5/32 F term (reference) 4G077 AA03 BE11 BE15 BE42 BE45 DA05 DB08 ED06 EF03 EF04 HA06 5F041 AA40 CA34 CA40 5F073 CA07 CA17 CB04 CB07 DA05 DA06 5F102 GB01 GC01 GD01 GJ03 GJ04 GJ05 GJ06 GK08 GQ01 HC01 5F103 AA04 DD01 GG01 HH03 HH04 JJ03 KK01 LL08 RR05
Claims (2)
−Ｖ族化合物半導体から成る少なくとも２層の薄層をヘ
テロ接合した層構造になっていることを特徴とする低抵
抗ＧａＮ系緩衝層。1. A nitride III containing Ga as an essential component
-A low-resistance GaN-based buffer layer having a layer structure in which at least two thin layers made of a group V compound semiconductor are hetero-joined.
ｌＧａＮ，ＧａＮ／ＡｌＧａＮ／ＧａＮ，ＧａＮ／Ｉｎ
ＧａＮ／ＧａＮ，ＩｎＧａＮ／ＧａＮ／ＩｎＧａＮ，Ｉ
ｎＡｌＧａＮ／ＧａＮ／ＩｎＡｌＧａＮ（ただし、Ｉｎ
ＡｌＧａＮは、ＧａＮよりもバンドギャップエネルギー
が大きい組成になっている），ＧａＮ／ＩｎＡｌＧａＮ
／ＧａＮ，ＡｌＧａＮＰ／ＧａＮＰ／ＡｌＧａＮＰ，Ａ
ｌＧａＮＡｓ／ＧａＮＡｓ／ＡｌＧａＮＡｓ，ＡｌＧａ
ＮＰ／ＩｎＧａＮＰ／ＡｌＧａＮＰ，ＡｌＧａＮＡｓ／
ＩｎＧａＮＡｓ／ＡｌＧａＮＡｓのいずれかである請求
項１の低抵抗ＧａＮ系緩衝層。2. The method according to claim 1, wherein the layer structure is AlGaN / GaN / A.
lGaN, GaN / AlGaN / GaN, GaN / In
GaN / GaN, InGaN / GaN / InGaN, I
nAlGaN / GaN / InAlGaN (where In
AlGaN has a composition with a larger band gap energy than GaN), GaN / InAlGaN
/ GaN, AlGaNP / GaNP / AlGaNP, A
lGaNAs / GaNAs / AlGaNAs, AlGa
NP / InGaNP / AlGaNP, AlGaNAs /
2. The low-resistance GaN-based buffer layer according to claim 1, which is one of InGaNAs / AlGaNAs.
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| KR100631414B1 (en) | 2005-05-19 | 2006-10-04 | 삼성전기주식회사 | Semiconductor light emitting diode and method of manufacturing the same |
| KR100638818B1 (en) | 2005-05-19 | 2006-10-27 | 삼성전기주식회사 | Nitride semiconductor light emitting device |
| US7569870B2 (en) | 2003-01-17 | 2009-08-04 | Sanken Electric Co., Ltd. | Gallium-nitride-based compound semiconductor device |
| WO2011083940A3 (en) * | 2010-01-05 | 2011-11-24 | 서울옵토디바이스주식회사 | Light-emitting diode and method for manufacturing same |
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