JPH11261053A - High electron mobility transistor - Google Patents
High electron mobility transistorInfo
- Publication number
- JPH11261053A JPH11261053A JP5707098A JP5707098A JPH11261053A JP H11261053 A JPH11261053 A JP H11261053A JP 5707098 A JP5707098 A JP 5707098A JP 5707098 A JP5707098 A JP 5707098A JP H11261053 A JPH11261053 A JP H11261053A
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- Japan
- Prior art keywords
- layer
- type
- gan
- semiconductor layer
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims description 10
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010410 layer Substances 0.000 abstract 11
- 239000002356 single layer Substances 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000005533 two-dimensional electron gas Effects 0.000 description 8
- 229910002704 AlGaN Inorganic materials 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- DIIIISSCIXVANO-UHFFFAOYSA-N 1,2-Dimethylhydrazine Chemical compound CNNC DIIIISSCIXVANO-UHFFFAOYSA-N 0.000 description 1
- MHYQBXJRURFKIN-UHFFFAOYSA-N C1(C=CC=C1)[Mg] Chemical compound C1(C=CC=C1)[Mg] MHYQBXJRURFKIN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001741 metal-organic molecular beam epitaxy Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明のGaN系化合物半導
体から成る高移動度トランジスタ(HEMT)に関し、
更に詳しくは、高電圧印加の下で作動できる新規な構造
のHEMTに関する。The present invention relates to a high mobility transistor (HEMT) comprising a GaN-based compound semiconductor according to the present invention.
More specifically, the present invention relates to a HEMT having a novel structure capable of operating under high voltage application.
【0002】[0002]
【従来の技術】HEMTは、例えば高出力マイクロ波素
子の素材として期待されていて、現在ではGaAs系化
合物半導体を用いて製造されているのが通例である。例
えば、半絶縁性基板の上にi型GaAs層とn型GaA
lxAs1-x層を順次成膜し、そしてそのn型GaAlx
As1-x層の上に、ソース電極とドレイン電極が装荷さ
れ、更に例えばp型GaAs層を介してゲート電極が装
荷された構造のものが知られている。2. Description of the Related Art HEMTs are expected to be used, for example, as materials for high-power microwave devices. At present, HEMTs are usually manufactured using GaAs-based compound semiconductors. For example, an i-type GaAs layer and an n-type GaAs are formed on a semi-insulating substrate.
l x As 1-x layers are sequentially formed, and the n-type GaAl x
There is known a structure in which a source electrode and a drain electrode are loaded on an As1 -x layer, and a gate electrode is further loaded via, for example, a p-type GaAs layer.
【0003】この構造のHEMTの場合、x=0.25
のときのエネルギーバンド図をみると、n型GaAl
0.25As0.75層とi型GaAs層のヘテロ接合界面にお
けるヘテロ障壁(ΔEc)は約0.26eVになってい
て、熱平衡状態においては、当該接合界面に2次元電子
ガス層が形成される状態になっている。そして、ソース
電極とドレイン電極の間に所定値の逆バイアス電圧を印
加し、またソース電極とゲート電極の間に順バイアス電
圧を印加することにより、前記n型GaAlxAs1 -x層
からはその下に位置するi型GaAs層へ電子が供給さ
れ、供給された電子は前記接合界面で2次元電子ガス層
を形成し、そのガス層内に閉じ込められた状態で電子は
ドレイン電極へと高速で流れてHEMT動作を実現す
る。その場合、ゲート電圧の直下における電界強度が強
いほど、2次元電子がガス層への電子の閉じ込め効果は
高まるので、高速動作は実現しやすくなる。In the case of a HEMT having this structure, x = 0.25
Looking at the energy band diagram at the time of, n-type GaAl
The hetero barrier (ΔEc) at the heterojunction interface between the 0.25 As 0.75 layer and the i-type GaAs layer is about 0.26 eV. In a thermal equilibrium state, a two-dimensional electron gas layer is formed at the junction interface. ing. Then, by applying a predetermined reverse bias voltage between the source electrode and the drain electrode and applying a forward bias voltage between the source electrode and the gate electrode, the n-type GaAl x As 1 -x layer Electrons are supplied to an i-type GaAs layer located thereunder, and the supplied electrons form a two-dimensional electron gas layer at the junction interface. The electrons are conveyed at a high speed to the drain electrode while being confined in the gas layer. To realize the HEMT operation. In that case, as the electric field intensity immediately below the gate voltage is higher, the effect of confining the two-dimensional electrons in the gas layer is increased, so that high-speed operation is easily realized.
【0004】しかしながら、GaAs系HEMTの場
合、ヘテロ接合界面における不連続バンドは0.26eV
程度(x=0.25のとき)であり、その絶縁破壊電界
値は3×105V/cm程度であるため、ゲート電極に高電
圧を印加してその直下に高電界を形成することにより高
速動作を実現するという点で難がある。このような問題
に対処することを目的として、最近、GaN系化合物半
導体を用いたHEMTの試作研究が行われている。However, in the case of a GaAs HEMT, the discontinuous band at the heterojunction interface is 0.26 eV.
(When x = 0.25) and the dielectric breakdown electric field value is about 3 × 10 5 V / cm. Therefore, by applying a high voltage to the gate electrode and forming a high electric field immediately below the gate electrode, There is a difficulty in realizing high-speed operation. For the purpose of addressing such a problem, recently, trial manufacture and research of HEMTs using GaN-based compound semiconductors have been conducted.
【0005】これは、GaAlxN1-xとGaNとのヘテ
ロ接合界面におけるヘテロ障壁(ΔEc)は約0.67e
Vであり、GaAs系の場合に比べて約2.6倍と高い不
連続バンドを有し、またその絶縁破壊電界値も2×10
6V/cmであり、GaAs系の場合に比べて1桁大きいの
で2次元電子ガス層内への電子の閉じ込め効果を高める
ことができ、理論的には、GaAs系に比べて電子濃度
を10倍程度大きくすることができるからである。[0005] This is because the hetero barrier (ΔEc) at the heterojunction interface between GaAl x N 1-x and GaN is about 0.67 e.
V, which has a discontinuous band that is about 2.6 times higher than that of the GaAs-based one.
6 V / cm, which is an order of magnitude larger than that of the GaAs system, so that the effect of confining electrons in the two-dimensional electron gas layer can be enhanced. This is because it can be approximately twice as large.
【0006】このGaN系HEMTとしては、例えば次
のようなものがMOCVD法を用いて製造されている。
すなわちまず、半絶縁性のサファイア基板の上に、Al
Nバッファ層が成膜される。ついで、Ga源としてトリ
メチルガリウム,N源としてアンモニアを用いて前記A
lNバッファ層の上にi型GaN層が成膜され、更にト
リメチルアルミニウムをAl源として前記i型GaN層
の上にn型AlGaN層が成膜される。そして、このn
型AlGaN層に対して常法のホトリソグラフィーとエ
ッチングを行ったのち、所定の箇所にゲート電極,ソー
ス電極,およびドレイン電極が装荷される。For example, the following GaN-based HEMTs are manufactured by using the MOCVD method.
That is, first, on a semi-insulating sapphire substrate, Al
An N buffer layer is formed. Next, the above-mentioned A was prepared using trimethylgallium as a Ga source and ammonia as an N source.
An i-type GaN layer is formed on the 1N buffer layer, and an n-type AlGaN layer is formed on the i-type GaN layer using trimethyl aluminum as an Al source. And this n
After performing conventional photolithography and etching on the type AlGaN layer, a gate electrode, a source electrode, and a drain electrode are loaded at predetermined locations.
【0007】このGaN系HEMTの場合、i型GaN
層とn型AlGaN層のヘテロ接合界面、具体的にはi
型GaN層の最上層に2次元電子ガス層が形成され、こ
こを電子が高速移動してHEMT動作を実現する。この
とき、電子の高移動度を実現するためには、このi型G
aN層には不純物や結晶欠陥が極力存在していないこと
が必要である。In the case of this GaN-based HEMT, i-type GaN
Interface between the layer and the n-type AlGaN layer, specifically, i
A two-dimensional electron gas layer is formed on the uppermost layer of the type GaN layer, and electrons move at a high speed to realize a HEMT operation. At this time, in order to realize high electron mobility, the i-type G
It is necessary that impurities and crystal defects do not exist as much as possible in the aN layer.
【0008】[0008]
【発明が解決しようとする課題】しかしながら、上記し
たGaN系HEMTの場合、GaAs系HEMTに比べ
れば高い電圧の印加は可能であるが、更なる高速動作が
要求されている昨今の状況に対しては必ずしも充分な電
子移動度を発揮するものとはいいがたい。本発明は従来
のGaN系HEMTにおける上記した問題を解決し、高
耐圧性を備えている新規構造のGaN系HEMTの提供
を目的とする。However, in the case of the GaN-based HEMT described above, a higher voltage can be applied than in the case of the GaAs-based HEMT. Does not necessarily exhibit sufficient electron mobility. An object of the present invention is to solve the above-described problems in the conventional GaN-based HEMT and to provide a GaN-based HEMT having a novel structure and high withstand voltage.
【0009】[0009]
【課題を解決するための手段】上記した目的を達成する
ために、本発明においては、半絶縁性基板の上に、i型
半導体層,n型半導体層をこの順序で積層して成る積層
構造が形成され、前記各半導体層はいずれもGaN系化
合物半導体から成り、前記n型半導体層の上にはGaN
系化合物半導体から成るp型半導体層を介してゲート電
極が装荷され、また前記n型半導体層の上には直接ソー
ス電極とドレイン電極がそれぞれ装荷されていることを
特徴とする高移動度トランジスタ、とくに、前記p型半
導体層が、p型GaN層もしくはp型InGaN層の1
層構造、またはp型GaN層にp型InGaN層を積層
して成る2層構造である高移動度トランジスタが提供さ
れる。In order to achieve the above object, according to the present invention, there is provided a laminated structure in which an i-type semiconductor layer and an n-type semiconductor layer are laminated in this order on a semi-insulating substrate. Is formed, each of the semiconductor layers is made of a GaN-based compound semiconductor, and GaN is formed on the n-type semiconductor layer.
A high mobility transistor, wherein a gate electrode is loaded via a p-type semiconductor layer made of a compound semiconductor, and a source electrode and a drain electrode are directly loaded on the n-type semiconductor layer, respectively. In particular, the p-type semiconductor layer is one of a p-type GaN layer and a p-type InGaN layer.
A high mobility transistor having a layer structure or a two-layer structure in which a p-type InGaN layer is stacked on a p-type GaN layer is provided.
【0010】[0010]
【発明の実施の形態】以下、本発明のHEMTにつき、
その基本構造を示す図1に基づいて詳細に説明する。本
発明のHEMTは、半絶縁性基板1の上に、バッファ層
2,i型半導体層3,n型半導体層4から成る積層構造
Aが形成され、n型半導体層4の上には、p型半導体層
6を介してゲート電極Gが装荷され、また、ソース電極
S,ドレイン電極Dがそれぞれ装荷された構造になって
いる。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a HEMT of the present invention will be described.
This will be described in detail with reference to FIG. In the HEMT of the present invention, a laminated structure A including a buffer layer 2, an i-type semiconductor layer 3, and an n-type semiconductor layer 4 is formed on a semi-insulating substrate 1, and a p-type The gate electrode G is loaded via the mold semiconductor layer 6, and the source electrode S and the drain electrode D are loaded respectively.
【0011】このHEMTは、GaN系化合物半導体に
対してMOCVD法やMOMBE法など公知のエピタキ
シャル成長法を適用することにより、半絶縁性基板1の
上に所定組成の半導体層を成膜していくことによって製
造される。ここで、半絶縁性基板1としては、この上に
成膜していく各半導体層との間で格子整合している材料
から成ることが本来は好ましいが、GaN系に関しては
そのような材料は存在しないので、従来から使用されて
いる材料、例えばサファイア,Si単結晶などの半絶縁
性材料の基板であればよい。また、バッファ層2として
は、GaN層が選択される。In this HEMT, a semiconductor layer having a predetermined composition is formed on a semi-insulating substrate 1 by applying a known epitaxial growth method such as a MOCVD method or a MOMBE method to a GaN-based compound semiconductor. Manufactured by Here, it is originally preferable that the semi-insulating substrate 1 be made of a material which is lattice-matched with each semiconductor layer to be formed thereon. Since it does not exist, a substrate of a conventionally used material, for example, a semi-insulating material such as sapphire or Si single crystal may be used. Further, a GaN layer is selected as the buffer layer 2.
【0012】i型半導体層3を構成するGaN系化合物
半導体としては、例えば、i型GaN,i型InGaN
などをあげることができる。とくに、i型GaNは好適
である。また、バンドギャップエネルギーが上記した高
純度なi型GaNのそれよりも小さいかまたは同等であ
れば、i型InxGa1-x-yAlyN(ただし、0<x<
1,0<y<0.2)をi型半導体層3として用いること
もできる。As the GaN compound semiconductor constituting the i-type semiconductor layer 3, for example, i-type GaN, i-type InGaN
And so on. In particular, i-type GaN is suitable. If the band gap energy is smaller than or equal to that of the above-mentioned high-purity i-type GaN, i-type In x Ga 1 -xy Al y N (where 0 <x <
1,0 <y <0.2) can be used as the i-type semiconductor layer 3.
【0013】n型半導体層4を構成するGaN系化合物
半導体としては、例えば、n型AlGaN,n型GaN
などをあげることができる。これらのうち、n型AlG
aNは好適である。また、バンドギャップエネルギーが
上記n型AlGaNのそれよりも小さいかまたは同等で
あれば、n型InuGa1-u-vAlvN(ただし、0<u
<1,0<v<0.5)をn型半導体層として用いること
もできる。As the GaN-based compound semiconductor constituting the n-type semiconductor layer 4, for example, n-type AlGaN, n-type GaN
And so on. Of these, n-type AlG
aN is preferred. If the band gap energy is smaller than or equal to that of the n-type AlGaN, n-type In u Ga 1-uv Al v N (where 0 <u)
<1,0 <v <0.5) can also be used as the n-type semiconductor layer.
【0014】このn型半導体層4の成膜に用いるn型ド
ーパントとしては、例えば金属Si(MBE法で成膜す
る場合)やジシラン(MOCVD法で成膜する場合)を
あげることができる。このn型半導体層4の上には直接
ソース電極Sとドレイン電極Dを装荷することを考える
と、両者間でオーミック接触を実現させるため、できる
だけ低抵抗となるようにドーパント濃度を設定すること
が好ましい。例えばn型ドーパントがSiである場合に
は、5×1017〜5×1018cm-3程度の濃度にする。The n-type dopant used for forming the n-type semiconductor layer 4 includes, for example, metal Si (in the case of forming by MBE) and disilane (in the case of forming by MOCVD). Considering that the source electrode S and the drain electrode D are directly loaded on the n-type semiconductor layer 4, it is necessary to set the dopant concentration so that the resistance is as low as possible in order to realize ohmic contact between the two. preferable. For example, when the n-type dopant is Si, the concentration is set to about 5 × 10 17 to 5 × 10 18 cm −3 .
【0015】次に、p型半導体層5を構成するGaN系
化合物半導体としては、p型GaN,p型InGaNを
あげることができる。このp型半導体層5は、p型Ga
N層,p型InGaN層のそれぞれ1層から成っていて
もよいが、p型GaN層の上に更にp型InGaN層を
積層して成る2層構造にすることが好適である。このp
型半導体層5を成膜するときのp型ドーパントとして
は、例えば金属Mg(MBE法で成膜する場合)やシク
ロペンタジエニルマグネシウム(MOCVD法で成膜す
る場合)などをあげることができる。このときのp型ド
ーパントの濃度は5×1017〜5×1018cm-3程度にす
る。Next, as the GaN-based compound semiconductor constituting the p-type semiconductor layer 5, p-type GaN and p-type InGaN can be mentioned. This p-type semiconductor layer 5 is made of p-type Ga
It may be composed of one layer each of an N layer and a p-type InGaN layer, but it is preferable to form a two-layer structure in which a p-type InGaN layer is further laminated on the p-type GaN layer. This p
Examples of the p-type dopant when forming the type semiconductor layer 5 include metal Mg (when forming by the MBE method) and cyclopentadienyl magnesium (when forming by the MOCVD method). At this time, the concentration of the p-type dopant is set to about 5 × 10 17 to 5 × 10 18 cm −3 .
【0016】最後に、ゲート電極Gを構成する材料とし
ては例えばAu/Pt,Alなどをあげることができ、
またゲート電極Gを構成する材料としては例えばAu,
Ti/Alなどをあげることができる。この構造のHE
MTは、ゲート電極Gの下がpn接合構造になってい
る。そして、ゲート電極Gから電圧印加を行うと、n型
半導体層4とi型半導体層3のヘテロ接合界面、具体的
には、i型半導体層3の最上層部に2次元電子ガス層3
aが形成され、そこにn型半導体層4から供給された電
子が閉じ込められ、高速でドレイン電極Dへ流れてHE
MT動作を実現する。Finally, examples of the material constituting the gate electrode G include Au / Pt, Al and the like.
Examples of the material forming the gate electrode G include Au,
Ti / Al and the like can be mentioned. HE of this structure
The MT has a pn junction structure below the gate electrode G. When a voltage is applied from the gate electrode G, the two-dimensional electron gas layer 3 is formed at the heterojunction interface between the n-type semiconductor layer 4 and the i-type semiconductor layer 3, specifically, at the uppermost layer of the i-type semiconductor layer 3.
a is formed, and the electrons supplied from the n-type semiconductor layer 4 are confined therein, flow to the drain electrode D at high speed, and HE
Implement MT operation.
【0017】その場合、ゲート電極G直下のpn接合の
働きにより少量のキャリア注入で電圧が制御され、かつ
制御された電圧によってチャネル間を流れる電流を制御
することが可能になるので、前記2次元電子ガス層3a
を高電圧で制御することが可能になり、2次元電子ガス
層3aへの電子の閉じ込め効果も高くなって電子の高速
移動が可能になる。In this case, the voltage is controlled by a small amount of carrier injection by the function of the pn junction immediately below the gate electrode G, and the current flowing between the channels can be controlled by the controlled voltage. Electron gas layer 3a
Can be controlled at a high voltage, the effect of confining the electrons in the two-dimensional electron gas layer 3a is enhanced, and the electrons can move at high speed.
【0018】とくに、p型半導体層5が前記したp型G
aNとp型InGaNの2層構造になっている場合に
は、この積層構造が1種の量子井戸構造として機能し、
その結果、量子効果によるトンネル電流が流れるように
なり、ゲート電流は流れやすくなるので好適である。In particular, the p-type semiconductor layer 5 is
In the case of a two-layer structure of aN and p-type InGaN, this stacked structure functions as one kind of quantum well structure,
As a result, a tunnel current due to the quantum effect flows and a gate current easily flows, which is preferable.
【0019】[0019]
【実施例】図1で示した積層構造のHEMTをMOMB
E法により次のようにして製造した。まず、半絶縁性の
Si単結晶基板1の上に、Ga源として金属Ga(5×
10 -7Torr),N源としてジメチルヒドラジン(5×1
0-5Torr)を用い、成長温度640℃でエピタキシャル
成長を行い、厚み50ÅのGaNバッファ層2を成膜し
た。DESCRIPTION OF THE PREFERRED EMBODIMENTS The HEMT having the laminated structure shown in FIG.
It was produced as follows by Method E. First, semi-insulating
On a Si single crystal substrate 1, metal Ga (5 ×
10 -7Torr), dimethylhydrazine (5 × 1) as N source
0-FiveTorr) and epitaxial growth at 640 ° C
After growing, a GaN buffer layer 2 having a thickness of 50 ° is formed.
Was.
【0020】ついで、N源をアンモニア(5×10-5To
rr)に切り換え、成長温度を850℃に上昇してエピタ
キシャル成長を行い、厚み5000Åのi型GaN層3
を成膜した。なお、このときのキャリア濃度は5×10
16cm-3以下となるように成膜条件を設定した。Then, the N source was changed to ammonia (5 × 10 −5 To
rr), the growth temperature is raised to 850 ° C. and epitaxial growth is performed, and the 5000-mm thick i-type GaN layer 3 is formed.
Was formed. The carrier concentration at this time is 5 × 10
The film forming conditions were set so as to be 16 cm −3 or less.
【0021】ついで、金属Al(2×10-7Torr)を供
給し、またn型ドーパントとして金属Si(2×10-9
Torr)を供給し、成長温度850℃でエピタキシャル成
長を継続して、厚みが500Åのn型AlGaN層4を
成膜した。このとき、キャリア濃度は1×1018cm-3と
なるように成膜条件を設定した。ついで、金属Siの供
給を絶ち、p型ドーパントとして金属Mg(5×10-9
Torr)を供給して成膜操作を続け、前記n型AlGaN
層4の上に厚み500Åのp型GaN層6を成膜した。
このとき、キャリア濃度は1×1018cm-3となるように
成膜条件を設定した。Next, metal Al (2 × 10 −7 Torr) is supplied, and metal Si (2 × 10 −9 Torr) is used as an n-type dopant.
(Torr), epitaxial growth was continued at a growth temperature of 850 ° C., and an n-type AlGaN layer 4 having a thickness of 500 ° was formed. At this time, the film forming conditions were set so that the carrier concentration was 1 × 10 18 cm −3 . Then, the supply of metal Si was stopped, and metal Mg (5 × 10 −9) was used as a p-type dopant.
Torr) to continue the film forming operation, and the n-type AlGaN
A p-type GaN layer 6 having a thickness of 500 ° was formed on the layer 4.
At this time, the film forming conditions were set so that the carrier concentration was 1 × 10 18 cm −3 .
【0022】ついで、水素とアルゴンとメタンの混合ガ
スをプラズマ化したものをエッチャントにしてドライエ
ッチングを行い、ゲート電極を装荷すべき箇所以外のp
型GaN層をエッチング除去してn型InGaN層4を
表出させた。その後、全体の表面を被覆してSiO2膜
をプラズマCVD法で成膜し、ホトレジストでパターニ
ングしたのちゲート電極を装荷すべき箇所を含む部分を
マスキングし、ソース電極とドレイン電極を装荷すべき
箇所は開口し、そこに表出したn型InGaN層4の上
に、金属Alを蒸着することにより、ソース電極Sとド
レイン電極Dを装荷した。Then, dry etching is performed by using a mixture of hydrogen, argon, and methane, which has been turned into plasma, as an etchant to perform p etching on portions other than those where the gate electrode is to be loaded.
The n-type InGaN layer 4 was exposed by removing the n-type GaN layer by etching. After that, the entire surface is covered, a SiO 2 film is formed by a plasma CVD method, and after patterning with a photoresist, a portion including a portion where a gate electrode is to be loaded is masked, and a portion where a source electrode and a drain electrode are to be loaded. Was opened, and the source electrode S and the drain electrode D were loaded on the exposed n-type InGaN layer 4 by depositing metal Al.
【0023】最後、前記マスキングをエッチング除去
し、その下のSiO2膜を開口し、ソース電極Sとドレ
イン電極Gの箇所をSiO2膜でマスキングしたのち、
上記開口部にAuを蒸着してp型GaN層5の上にはゲ
ート電極Gを装荷して図1で示したHEMTを製造し
た。このHEMTは、ゲート電圧からの印加電圧を3V
でドレイン電流(Ids)が60mA,ドレイン電圧2V以
上で飽和するHEMT特性が得られた。すなわち、この
飽和特性はVdsを100Vまであげても一定値を保ち、
HEMTとしての機能を喪失することはなかった。Finally, the masking is removed by etching, the underlying SiO 2 film is opened, and the portions of the source electrode S and the drain electrode G are masked with the SiO 2 film.
Au was vapor-deposited on the opening and a gate electrode G was loaded on the p-type GaN layer 5 to manufacture the HEMT shown in FIG. In this HEMT, the applied voltage from the gate voltage is 3 V
As a result, HEMT characteristics were obtained in which the drain current (Ids) was saturated at 60 mA and the drain voltage was 2 V or more. That is, this saturation characteristic maintains a constant value even when Vds is increased up to 100 V,
The function as HEMT was not lost.
【0024】室温下でのこのHEMT構造の移動度は、
600cm2/V・secであり、77Kでの移動度は7500c
m2/V・secと良好な値を示した。The mobility of this HEMT structure at room temperature is:
600 cm 2 / V · sec, mobility at 77K is 7500 c
It showed a good value of m 2 / V · sec.
【0025】[0025]
【発明の効果】以上の説明で明らかなように、本発明の
GaN系HEMTは、ゲート電極をVまで高めても故障
を起こすことがなく、従来のGaN系HEMTに比べて
高速動作をすることができる。これは、ゲート電極とチ
ャネル層との間をpn接合構造とし、i型半導体層とn
型半導体層との接合界面に電子の閉じ込め効果が優れて
いる2次元電子ガス層が形成されるようにしたことがも
たらす効果である。As is apparent from the above description, the GaN-based HEMT of the present invention does not fail even if the gate electrode is raised to V, and operates at a higher speed than the conventional GaN-based HEMT. Can be. This is because a pn junction structure is formed between the gate electrode and the channel layer, and the i-type semiconductor layer
This is an effect brought about by forming a two-dimensional electron gas layer having an excellent electron confinement effect at the junction interface with the mold semiconductor layer.
【図1】本発明のHEMTの層構造を示す断面図であ
る。FIG. 1 is a sectional view showing a layer structure of a HEMT of the present invention.
1 半絶縁性基板 2 バップ層(GaN層) 3 i型半導体層(i型GaN層) 3a 2次元電子ガス層 4 n型半導体層(n型InGaN層) 5 p型半導体層(p型GaN層) S ソース電極 G ゲート電極 D ドレイン電極 DESCRIPTION OF SYMBOLS 1 Semi-insulating substrate 2 Vap layer (GaN layer) 3 i-type semiconductor layer (i-type GaN layer) 3a Two-dimensional electron gas layer 4 n-type semiconductor layer (n-type InGaN layer) 5 p-type semiconductor layer (p-type GaN layer) ) S source electrode G gate electrode D drain electrode
Claims (2)
型半導体層をこの順序で積層して成る積層構造が形成さ
れ、前記各半導体層はいずれもGaN系化合物半導体か
ら成り、前記n型半導体層の上にはGaN系化合物半導
体から成るp型半導体層を介してゲート電極が装荷さ
れ、また前記n型半導体層の上には直接ソース電極とド
レイン電極がそれぞれ装荷されていることを特徴とする
高移動度トランジスタ。An i-type semiconductor layer is formed on a semi-insulating substrate.
A stacked structure is formed by stacking type semiconductor layers in this order. Each of the semiconductor layers is made of a GaN-based compound semiconductor, and a p-type semiconductor layer made of a GaN-based compound semiconductor is formed on the n-type semiconductor layer. A high-mobility transistor, wherein a gate electrode is loaded via the gate electrode, and a source electrode and a drain electrode are respectively loaded directly on the n-type semiconductor layer.
くはp型InGaN層の1層構造、またはp型GaN層
にp型InGaN層を積層して成る2層構造である請求
項1の高移動度トランジスタ。2. The p-type semiconductor layer according to claim 1, wherein the p-type semiconductor layer has a one-layer structure of a p-type GaN layer or a p-type InGaN layer, or a two-layer structure in which a p-type GaN layer is laminated on a p-type GaN layer. High mobility transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5707098A JPH11261053A (en) | 1998-03-09 | 1998-03-09 | High electron mobility transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5707098A JPH11261053A (en) | 1998-03-09 | 1998-03-09 | High electron mobility transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11261053A true JPH11261053A (en) | 1999-09-24 |
Family
ID=13045200
Family Applications (1)
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---|---|---|---|
JP5707098A Pending JPH11261053A (en) | 1998-03-09 | 1998-03-09 | High electron mobility transistor |
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