JP2001155999A - Method and device for forming semiconductor layers in layer - Google Patents
Method and device for forming semiconductor layers in layerInfo
- Publication number
- JP2001155999A JP2001155999A JP33372299A JP33372299A JP2001155999A JP 2001155999 A JP2001155999 A JP 2001155999A JP 33372299 A JP33372299 A JP 33372299A JP 33372299 A JP33372299 A JP 33372299A JP 2001155999 A JP2001155999 A JP 2001155999A
- Authority
- JP
- Japan
- Prior art keywords
- film forming
- chamber
- forming chamber
- substrate
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体層の積層方
法及び積層装置に関し、より詳しくは、太陽電池の半導
体層の積層方法及び積層装置に関する。The present invention relates to a method and apparatus for laminating semiconductor layers, and more particularly to a method and apparatus for laminating semiconductor layers of a solar cell.
【０００２】[0002]
【従来の技術】アモルファスシリコン太陽電池及びハイ
ブリッド太陽電池の半導体層の積層装置（製膜装置）
は、複数の製膜室が直列的に接続され、且つ、各製膜室
で同時に製膜進行するインライン方式の積層装置が使用
されている。この製膜装置は量産性に富むだけでなく、
不純物相の混入が防止可能である。しかも、製膜途中の
基板が大気接触するのを防止することにより高品質膜が
製膜でき、且つ、半導体層を積層するための基板の搬送
の自動化が可能である。その概念図を図８に示す。先
ず、アモルファスシリコン半導体層の積層方法について
説明する。図８（ａ）に示す製膜装置１２０は複数の製
膜室をそれぞれ仕切扉（図示していない）等を介して直
列に接続し、各室で個々の製膜を行なうことを基本とし
ている。図８（ａ）で入口室１３０に入った基板３６
は、ここで急速に減圧される。その後、イオン洗浄法等
でクリーニングされてもよい。そして、必要に応じて基
板３６を予備加熱して所定温度にまで昇温することも可
能である。次に、入口室１３０と第１製膜室１２２の圧
力を測定して、仕切扉を開いても良い状態であることを
確認後、仕切扉を開き、基板３６は第１製膜室１２２に
入れられる。そして、仕切扉を閉じ第１製膜室１２２で
プラズマＣＶＤ法によって基板３６上にｐｉｎ型アモル
ファスシリコン半導体層のｐ層が製膜される。この間
に、次の基板は入口室１３０に入り、同様のことが行な
われる。基板３６は次々に第２製膜室１２４以降の製膜
室で連続的にｉ層とｎ層が製膜され（第２製膜室１２４
から第７製膜室１２６はｉ層の製膜、第８製膜室１２８
ではｎ層の製膜）、出口室１３２を出て大気圧空間に取
り出される。なお、製膜室数は任意に変更が可能であ
る。2. Description of the Related Art Laminating apparatus for semiconductor layers of amorphous silicon solar cells and hybrid solar cells (film forming apparatus)
A plurality of film forming chambers are connected in series, and an in-line type laminating apparatus in which film formation proceeds simultaneously in each film forming chamber is used. This film forming device is not only mass-producible, but also
It is possible to prevent entry of an impurity phase. In addition, a high quality film can be formed by preventing the substrate in the course of film formation from coming into contact with the atmosphere, and the transfer of the substrate for laminating the semiconductor layers can be automated. FIG. 8 shows a conceptual diagram thereof. First, a method of laminating an amorphous silicon semiconductor layer will be described. The film forming apparatus 120 shown in FIG. 8A is based on connecting a plurality of film forming chambers in series via a partition door (not shown) or the like, and performing individual film forming in each chamber. . The substrate 36 that has entered the entrance chamber 130 in FIG.
Is rapidly depressurized here. Thereafter, cleaning may be performed by an ion cleaning method or the like. If necessary, the substrate 36 can be preheated and heated to a predetermined temperature. Next, the pressure in the inlet chamber 130 and the first film forming chamber 122 is measured, and after confirming that the partition door is in a state where the partition door may be opened, the partition door is opened, and the substrate 36 is moved to the first film forming chamber 122. Can be put in. Then, the partition door is closed, and the p-layer of the pin type amorphous silicon semiconductor layer is formed on the substrate 36 by the plasma CVD method in the first film forming chamber 122. During this time, the next substrate enters the inlet chamber 130 and the same is done. In the substrate 36, the i-layer and the n-layer are successively formed in the film forming chambers subsequent to the second film forming chamber 124 (the second film forming chamber 124).
From the seventh film forming chamber 126, an i-layer film is formed, and the eighth film forming chamber 128 is formed.
In this case, an n-layer film is formed), and exits the outlet chamber 132 and is taken out into the atmospheric pressure space. The number of film forming chambers can be arbitrarily changed.
【０００３】この方式にあっては、各室での工程はほぼ
同時間に行なわれることが必須条件である。なぜなら、
ｐ層及びｎ層と比較して充分な厚さを必要とするｉ層の
積層を１つの製膜室で行なうと、ｐ層又はｎ層を製膜し
ている製膜室はｐ層又はｎ層の製膜後、ｉ層の製膜完了
まで製膜室の機能を停止させなくてはならないからであ
る。よって、ｉ層の厚みを厚くするには、製膜時間をｐ
層，ｎ層と合わせるためにｉ層を製膜する製膜室を図８
に示すように複数室にする方法がとられる。In this system, it is an essential condition that the processes in each chamber are performed almost simultaneously. Because
When lamination of the i-layer, which requires a sufficient thickness compared to the p-layer and the n-layer, is performed in one deposition chamber, the p-layer or the n-layer deposition chamber is p-layer or n-layer. This is because, after the formation of the layer, the function of the film forming chamber must be stopped until the formation of the i-layer is completed. Therefore, in order to increase the thickness of the i-layer, the film formation time must be p
FIG. 8 shows a film forming chamber for forming an i-layer to be combined with the n-layer and the n-layer.
As shown in FIG.
【０００４】次に、アモルファスシリコン半導体層を積
層してからポリシリコン半導体層を積層するハイブリッ
ド太陽電池の半導体層を製造する場合を検討してみる。
アモルファスシリコン半導体層を積層する工程とポリシ
リコン半導体層を積層する工程との２工程が必要なの
で、図８（ａ）に示す製膜室以外に、ポリシリコン半導
体層を積層するための製膜室を追加することが考えられ
る。即ち、図８（ｂ）に示すように、図８（ａ）のアモ
ルファスシリコン半導体層のｎ層を積層する第８製膜室
１２８の次にポリシリコン半導体層のｐ層を積層する第
９製膜室１３４を設置する。そして、ポリシリコン半導
体層のｉ層、ｎ層の順で積層できるように製膜室を設置
すれば（第１０製膜室１３６から第１５製膜室１３８は
ｉ層、第１６製膜室１４０はｎ層の製膜）、ハイブリッ
ド太陽電池の半導体層を製造することが可能である。Next, consider the case of manufacturing a semiconductor layer of a hybrid solar cell in which an amorphous silicon semiconductor layer is stacked and then a polysilicon semiconductor layer is stacked.
Since two steps of a step of laminating an amorphous silicon semiconductor layer and a step of laminating a polysilicon semiconductor layer are required, a film forming chamber for laminating a polysilicon semiconductor layer other than the film forming chamber shown in FIG. May be added. That is, as shown in FIG. 8B, a ninth film-forming chamber 128 in which a polysilicon semiconductor layer p-layer is laminated next to an eighth film-forming chamber 128 in which an amorphous silicon semiconductor layer n-layer is laminated in FIG. 8A. A membrane chamber 134 is provided. If a film forming chamber is installed so that the i-layer and the n-layer of the polysilicon semiconductor layer can be stacked in this order (the tenth film-forming chamber 136 to the fifteenth film-forming chamber 138 are the i-layer, the sixteenth film-forming chamber 140). Is an n-layer film formation), and a semiconductor layer of a hybrid solar cell can be manufactured.
【０００５】アモルファスシリコン半導体層及び、更に
ポリシリコン半導体層を積層するハイブリッド太陽電池
の半導体層の両方を製造するのならば、各製膜装置を用
意することになる。例えば、アモルファスシリコン半導
体層及びハイブリッド太陽電池の半導体層の製膜装置を
それぞれＸとＹ（Ｘ，Ｙは任意の数）だけ用意したとす
る。アモルファスシリコン半導体層及びハイブリッド太
陽電池の半導体層の製膜装置がそれぞれ最大限に稼働し
ている時は製膜装置の無駄はなく、且つ、半導体層の生
産性は良い。又、アモルファスシリコン半導体層を（Ｘ
＋Ｙ）の数の製膜装置を使用して製造したい場合で、且
つ、ハイブリッド太陽電池の半導体層を製造しない場合
は、ハイブリッド太陽電池の半導体層のアモルファスシ
リコン半導体層を製膜する製膜室を使用することによっ
て、（Ｘ＋Ｙ）の数の製膜装置を使用することができ
る。これは、ハイブリッド太陽電池の半導体層がアモル
ファスシリコン半導体層とポリシリコン半導体層から構
成されていて、例えば、図８（ｂ）に示す第１製膜室１
２２から第８製膜室１２８でアモルファスシリコン半導
体層の積層を行なった後、第９製膜室１３４以降では製
膜を行なわない事によって、アモルファスシリコン半導
体層が製膜可能であるからである。If both an amorphous silicon semiconductor layer and a semiconductor layer of a hybrid solar cell in which a polysilicon semiconductor layer is further laminated are manufactured, each film forming apparatus must be prepared. For example, it is assumed that X and Y (X and Y are arbitrary numbers) are prepared for the film forming apparatus of the amorphous silicon semiconductor layer and the semiconductor layer of the hybrid solar cell, respectively. When the film forming apparatuses for the amorphous silicon semiconductor layer and the semiconductor layer of the hybrid solar cell are operating at their maximum, there is no waste of the film forming apparatus, and the productivity of the semiconductor layer is good. In addition, the amorphous silicon semiconductor layer (X
+ Y), and when the semiconductor layer of the hybrid solar cell is not to be manufactured, the film forming chamber for forming the amorphous silicon semiconductor layer of the semiconductor layer of the hybrid solar cell is provided. By using this, (X + Y) number of film forming apparatuses can be used. This is because the semiconductor layer of the hybrid solar cell is composed of an amorphous silicon semiconductor layer and a polysilicon semiconductor layer. For example, the first film forming chamber 1 shown in FIG.
This is because the amorphous silicon semiconductor layer can be formed by stacking the amorphous silicon semiconductor layers in the film forming chambers 22 to 128 and not performing the film forming in the ninth film forming chamber 134 and thereafter.
【０００６】[0006]
【発明が解決しようとする課題】しかし、ハイブリッド
太陽電池の半導体層を（Ｘ＋Ｙ）の数の製膜装置を使用
して製造したい場合で、且つ、アモルファスシリコン半
導体層を全く製造しない場合は、アモルファスシリコン
半導体層の製膜装置は使用できないので完全に休んでし
まい、又、ハイブリッド太陽電池の半導体層は製膜装置
が不足する分（この例ではＸだけ不足する）だけ、全て
のハイブリッド太陽電池の半導体層の製造に時間が掛か
ってしまう。よって、上記の場合は製膜装置の無駄が生
じた上に、生産性が悪くなっている。However, when it is desired to manufacture a semiconductor layer of a hybrid solar cell using (X + Y) film-forming apparatuses and when no amorphous silicon semiconductor layer is manufactured, an amorphous silicon semiconductor layer is required. The silicon semiconductor layer film forming apparatus cannot be used, so it is completely rested. Also, the semiconductor layers of the hybrid solar cells have the shortage of the film forming apparatuses (in this example, X is insufficient), and all the hybrid solar cells It takes time to manufacture the semiconductor layer. Therefore, in the above case, the film forming apparatus is wasted and productivity is deteriorated.
【０００７】そこで、本発明者は複数の製膜室が直列的
に接続された製膜装置における太陽電池等の製作におけ
る半導体層の積層において、上述した種々の課題を解決
するために鋭意研究を重ねた結果、本発明をするに至っ
たのである。Therefore, the present inventor has made intensive studies to solve the various problems described above in laminating semiconductor layers in the manufacture of solar cells and the like in a film forming apparatus in which a plurality of film forming chambers are connected in series. As a result, the present invention has been accomplished.
【０００８】[0008]
【課題を解決するための手段】本発明に係る半導体層の
積層方法の要旨とするところは、基板を複数の製膜室を
順に移動させながら基板上に所定構造の半導体層を積層
する半導体層の積層方法において、少なくともいずれか
一つの前記製膜室から該基板が次に進む製膜室を複数設
けて、該基板が次に入る製膜室を決定する工程を含むこ
とにある。なお、前記基板が次に入る製膜室を決定する
工程後に、該基板を決定された製膜室に移送する。The gist of the method for laminating semiconductor layers according to the present invention is to provide a method of laminating a semiconductor layer having a predetermined structure on a substrate while sequentially moving the substrate through a plurality of film forming chambers. The laminating method according to the above aspect further comprises a step of providing a plurality of film-forming chambers in which the substrate proceeds from at least one of the film-forming chambers, and determining a film-forming chamber into which the substrate enters next. After the step of determining a film forming chamber into which the substrate is to be next, the substrate is transferred to the determined film forming chamber.
【０００９】又、本発明に係る半導体層の積層方法の他
の要旨とするところは、基板を複数の製膜室を順に移動
させながら基板上に所定構造の半導体層を積層する半導
体層の積層方法において、複数の製膜室から順次移動し
てくる基板を順番に取り込む工程を含むことにある。な
お、順番に取り込む工程後に、次の製膜室に基板を移送
する。また、基板が移送される製膜室の室数は１つに限
られることは無く、複数の製膜室から基板を移送する製
膜室を決定してから移送してもよい。Another aspect of the method of laminating semiconductor layers according to the present invention is that a semiconductor layer having a predetermined structure is laminated on a substrate while sequentially moving the substrate through a plurality of film forming chambers. The method is to include a step of sequentially taking the substrates sequentially moving from the plurality of film forming chambers. After the steps of sequentially taking in the substrates, the substrates are transferred to the next film forming chamber. Further, the number of the film forming chambers to which the substrates are transferred is not limited to one, and the transfer may be performed after determining the film forming chambers to transfer the substrates from the plurality of film forming chambers.
【００１０】なお、上記の基板が次に入る製膜室を決定
する工程及び／又は基板を順番に取り込む工程によっ
て、複数種の半導体層を積層することが可能である。即
ち、通常のアモルファスシリコン太陽電池、薄型の太陽
電池、ハイブリッド太陽電池の半導体層を混合して製膜
することができる。又、複数種の半導体層の製膜ではな
く、１種類の半導体層を積層することも当然可能であ
る。[0010] A plurality of types of semiconductor layers can be stacked by the step of determining a film formation chamber into which the substrate enters next and / or the step of sequentially loading the substrates. That is, the semiconductor layers of ordinary amorphous silicon solar cells, thin solar cells, and hybrid solar cells can be mixed to form a film. In addition, it is naturally possible to stack one type of semiconductor layer instead of forming a plurality of types of semiconductor layers.
【００１１】次に、本発明に係る半導体層の積層装置の
要旨とするところは、基板を複数の製膜室を順に移動さ
せながら該基板上に所定構造の半導体層を順次積層する
半導体層の積層装置において、該基板が少なくともいず
れか一つの前記製膜室から次に進む製膜室を複数設け
て、該基板が次に入る製膜室を決定する分岐室を含むこ
とを特徴とする半導体層の積層装置を提供することにあ
る。なお、分岐室及び／又は集合室において製膜を行な
うことも可能である。つまり、製膜室が分岐室又は集合
室の機能を備えることである。Next, the gist of the semiconductor layer laminating apparatus according to the present invention is that a semiconductor layer having a predetermined structure is sequentially laminated on a substrate while sequentially moving the substrate through a plurality of film forming chambers. In the stacking apparatus, the substrate is provided with a plurality of film forming chambers that proceed from at least one of the film forming chambers to the next, and includes a branch chamber that determines a film forming chamber into which the substrate enters next. An object of the present invention is to provide a layer stacking apparatus. In addition, it is also possible to perform film formation in a branch room and / or a collective room. That is, the film forming chamber has a function of a branching chamber or a collecting chamber.
【００１２】更に、本発明に係る半導体層の積層装置の
要旨とするところは、基板を複数の製膜室を順に移動さ
せながら基板上に所定構造の半導体層を順次積層する半
導体層の積層装置において、複数の製膜室から順次移動
してくる基板を、順番に取り込む集合室を含むことを特
徴とする半導体層の積層装置を提供することにある。
又、基板が集合室に送られたあと、次に送られる製膜室
は、単数又は複数のどちらでもよい。Further, the gist of the semiconductor layer laminating apparatus according to the present invention is that a semiconductor layer laminating apparatus for sequentially laminating a semiconductor layer having a predetermined structure on a substrate while sequentially moving the substrate through a plurality of film forming chambers. In the present invention, there is provided an apparatus for stacking semiconductor layers, characterized by including a collective chamber for sequentially taking in substrates sequentially moving from a plurality of film forming chambers.
After the substrate is sent to the collecting chamber, the film forming chamber to be sent next may be either a single film forming chamber or a plurality of film forming chambers.
【００１３】[0013]
【発明の実施の形態】本発明に係る半導体層の積層方法
及び積層装置の実施の形態について、図面に基づいて詳
しく説明する。なお、本明細書に添付する図面における
製膜室等の装置の詳細な図は省略している。又、各図面
における製膜室数は任意に変更することが可能である。
更に、各製膜室の製膜条件を任意に変更して、製膜でき
る半導体の種類を変更することができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method and apparatus for laminating semiconductor layers according to the present invention will be described in detail with reference to the drawings. Detailed drawings of the apparatus such as a film forming chamber in the drawings attached to this specification are omitted. Further, the number of film forming chambers in each drawing can be arbitrarily changed.
Furthermore, the type of semiconductor that can be formed can be changed by arbitrarily changing the film forming conditions in each film forming chamber.
【００１４】図１に本発明の半導体層の積層装置１０を
示す。なお、図示していないが、各製膜室は開閉可能な
扉（仕切扉）で接続されていて、基板３６が各製膜室を
移動する時に開閉するようになっている。又、各製膜室
には、高周波プラズマ放電を行なう装置、シラン（Ｓｉ
Ｈ4 ）ガス、ジボラン（Ｂ2 Ｈ6 ）ガス、フォスフィン
（ＰＨ3 ）ガス、水素（Ｈ2 ）ガス、メタン（ＣＨ4 ）
ガス、あるいはそれ以外のガスを供給する装置、製膜室
内を真空又は減圧する装置が必要に応じて設置されてい
る。そして、基板３６は台車に載置されるなどして、自
動的に各室に移送される。基板３６は台車に１枚又は複
数枚セットされて、同時に製膜が行なわれる。FIG. 1 shows a semiconductor layer laminating apparatus 10 according to the present invention. Although not shown, each of the film forming chambers is connected by an openable / closable door (partition door), and is opened and closed when the substrate 36 moves through each of the film forming chambers. In each film forming chamber, a device for performing high-frequency plasma discharge, silane (Si)
H 4 ) gas, diborane (B 2 H 6 ) gas, phosphine (PH 3 ) gas, hydrogen (H 2 ) gas, methane (CH 4 )
A device for supplying gas or another gas, and a device for vacuum or decompression of the film forming chamber are provided as necessary. Then, the substrate 36 is automatically transferred to each room by being placed on a cart or the like. One or a plurality of substrates 36 are set on a cart, and film formation is performed simultaneously.
【００１５】先ず、入口室１４に入った基板３６は、こ
こで急速に減圧される。そして、必要に応じて基板３６
を予備加熱して所定温度にまで昇温することが可能であ
る。次に、入口室１４と第１製膜室１６の圧力を測定し
て、仕切扉を開いてもよい状態であることを確認の後、
仕切扉を開き、基板３６は第１製膜室１６に入る。基板
３６が第１製膜室１６に搬入後に、仕切扉を閉じて第１
製膜室１６でプラズマＣＶＤ法を用いてアモルファスシ
リコン半導体層のｐ層が製膜される。この間に、次の基
板３６は入口室１４に入り、同様のことが行なわれる。
第１製膜室１６での製膜が完了すると、基板３６は第２
製膜室１８に送られる。このようにして、第２製膜室１
８以降、次々と製膜が行なわれ、各出口室で半導体層が
積層された基板３６が取り出される。First, the substrate 36 entering the inlet chamber 14 is rapidly decompressed here. Then, if necessary, the substrate 36
Can be preheated and heated to a predetermined temperature. Next, the pressure in the inlet chamber 14 and the first film forming chamber 16 is measured, and after confirming that the partition door is in a state where the partition door may be opened,
The partition door is opened, and the substrate 36 enters the first film forming chamber 16. After the substrate 36 is carried into the first film forming chamber 16, the partition door is closed and the first
In the film forming chamber 16, the p-layer of the amorphous silicon semiconductor layer is formed using the plasma CVD method. During this time, the next substrate 36 enters the inlet chamber 14 and the same is done.
When the film formation in the first film forming chamber 16 is completed, the substrate 36 becomes the second
It is sent to the film forming chamber 18. Thus, the second film forming chamber 1
8 and thereafter, film formation is performed one after another, and the substrate 36 on which the semiconductor layer is laminated is taken out from each exit chamber.
【００１６】本発明においては、第４製膜室２２の次
に、製膜する半導体層の種類によって次に移動する製膜
室を振り分けるための分岐室１２が設けられている。よ
って、アモルファスシリコン半導体層を製造するのなら
ば第５ａ製膜室２４ａに送り、又、ハイブリッド太陽電
池の半導体層を製造するのならば第５ｂ製膜室２４ｂに
送られる。そして、第５ａ製膜室２４ａ及び第６ａ製膜
室２６ａにおいてそれぞれアモルファスシリコン半導体
層のｉ層とｎ層とを積層することによって第１出口室３
４ａでアモルファスシリコン半導体層が積層した基板３
６が取り出される。又、第５ｂ製膜室２４ｂ以降の製膜
室においては、アモルファスシリコン半導体層のｎ層及
びｐｉｎ型ポリシリコン半導体層が積層されて（第５ｂ
製膜室２４ｂではアモルファスシリコン半導体層のｎ層
の積層、第６ｂ製膜室２６ｂではポリシリコン半導体層
のｐ層の積層、第７ｂ製膜室２８ｂから第１２ｂ製膜室
３０ｂではポリシリコン半導体層のｉ層の積層、第１３
ｂ製膜室３２ｂではポリシリコン半導体層のｎ層の積
層）、第２出口室３４ｂでハイブリッド太陽電池の半導
体層が積層された基板３６が取り出される。よって、１
つの製膜装置において２種類の半導体層の積層が可能に
なった。このことは、複数種の半導体層を積層するのに
柔軟に製膜装置を使用することができる。In the present invention, next to the fourth film forming chamber 22, there is provided a branch chamber 12 for sorting a film forming chamber to be moved next according to the type of semiconductor layer to be formed. Therefore, if an amorphous silicon semiconductor layer is to be manufactured, it is sent to the 5a-th film forming chamber 24a, and if it is to manufacture a hybrid solar cell semiconductor layer, it is sent to the 5b-th film forming chamber 24b. Then, the first outlet chamber 3 is formed by laminating the i-layer and the n-layer of the amorphous silicon semiconductor layer in the 5a film-forming chamber 24a and the 6a film-forming chamber 26a, respectively.
Substrate 3 on which amorphous silicon semiconductor layer is laminated at 4a
6 is taken out. Further, in the film forming chambers after the 5b film forming chamber 24b, the n-layer of the amorphous silicon semiconductor layer and the pin-type polysilicon semiconductor layer are laminated (5b
The n-layer of the amorphous silicon semiconductor layer is stacked in the film forming chamber 24b, the p-layer of the polysilicon semiconductor layer is stacked in the sixth film forming chamber 26b, and the polysilicon semiconductor layer is stacked in the seventh to the 12th film forming chamber 30b. Of the i-layer of the thirteenth
The substrate 36 on which the semiconductor layer of the hybrid solar cell is laminated is taken out from the second outlet chamber 34b. Therefore, 1
Two types of semiconductor layers can be stacked in one film forming apparatus. This makes it possible to flexibly use the film forming apparatus to stack a plurality of types of semiconductor layers.
【００１７】詳しく述べると、例えば第１製膜室１６か
ら第４製膜室２２の各室での製膜時間が２分であり、第
５ａ製膜室２４ａ、第６ａ製膜室２６ａ及び第５ｂ製膜
室２４ｂから第１３ｂ製膜室３２ｂでの各室製膜時間が
４分だったとする。第５ｂ製膜室２４ｂで製膜が行なわ
れている時に分岐室１２に入ってきた基板３６は第５ａ
製膜室２４ａに送られる。又、第５ｂ製膜室２４ｂで製
膜を行なわれていた基板３６が第６ｂ製膜室２６ｂに送
られて、第５ｂ製膜室２４ｂが空になったときは、分岐
室１２に入ってきた基板３６は第５ｂ製膜室２４ｂに送
られる。例えば、第４製膜室２２にあった基板３６が第
５ｂ製膜室２４ｂに送られたのならば、第１製膜室１６
及び第３製膜室２０にある基板３６は第５ａ製膜室２４
ａに送られることになり、第２製膜室１８にある基板３
６は第５ｂ製膜室２４ｂに送られることになる。つま
り、分岐室１２に２分毎に送られてくる基板３６は、第
５ａ製膜室２４ａと第５ｂ製膜室２４ｂに交互に基板３
６を送ることによって、第５ａ製膜室２４ａと第５ｂ製
膜室２４ｂ以降の製膜室での製膜時間は４分になる。こ
のことによって、第１出口室３４ａ及び第２出口室３４
ｂより４分毎にそれぞれアモルファスシリコン半導体層
又はハイブリッド太陽電池の半導体層が積層された基板
３６が取り出される。More specifically, for example, the film forming time in each of the first film forming chamber 16 to the fourth film forming chamber 22 is 2 minutes, and the 5a film forming chamber 24a, the 6a film forming chamber 26a, and the It is assumed that the film forming time from the 5b film forming chamber 24b to the 13th film forming chamber 32b is 4 minutes. The substrate 36 that has entered the branching chamber 12 when the film is being formed in the 5b film forming chamber 24b is the 5a
It is sent to the film forming chamber 24a. Further, the substrate 36 which has been formed in the 5b film forming chamber 24b is sent to the 6b film forming chamber 26b, and when the 5b film forming chamber 24b becomes empty, it enters the branching chamber 12. The substrate 36 is sent to the 5b-th film forming chamber 24b. For example, if the substrate 36 in the fourth film forming chamber 22 is sent to the 5b film forming chamber 24b, the first film forming chamber 16
And the substrate 36 in the third film forming chamber 20 is the 5a film forming chamber 24.
a in the second film-forming chamber 18
6 is sent to the 5b film-forming chamber 24b. In other words, the substrate 36 sent to the branch chamber 12 every two minutes is alternately placed in the 5a film forming chamber 24a and the 5b film forming chamber 24b.
By sending 6, the film forming time in the film forming chambers after the 5a film forming chamber 24a and the 5b film forming chamber 24b becomes 4 minutes. As a result, the first outlet chamber 34a and the second outlet chamber 34
The substrate 36 on which the amorphous silicon semiconductor layer or the semiconductor layer of the hybrid solar cell is laminated is taken out every 4 minutes from b.
【００１８】なお、分岐室１２に入った台車は次に進む
製膜室に合わせて方向転換を行なった上で次の製膜室に
移動する。方向転換の方法は、分岐室１２の床面にター
ンテーブルを設置して、回動させる等して行なったり、
台車を上方移動レールよりつり下げられている機構で
は、上方移動レールを回動する等して行なう。又、第４
製膜室２２が分岐室１２の機能を兼ねることも可能で、
第４製膜室２２での製膜後に、次に基板３６が送られる
製膜室との仕切扉が開くことになる。この場合は、分岐
室１２がなくなる分だけ、製膜装置１０が小型化される
ことになる。The truck that has entered the branching chamber 12 changes its direction in accordance with the film forming chamber to be advanced to the next, and moves to the next film forming chamber. The direction can be changed by installing a turntable on the floor of the branch room 12 and rotating it.
In a mechanism in which the carriage is suspended from the upper moving rail, the operation is performed by rotating the upper moving rail or the like. Also, the fourth
The film forming chamber 22 can also serve as the function of the branch chamber 12,
After the film formation in the fourth film formation chamber 22, the partition door for the next film formation chamber to which the substrate 36 is fed is opened. In this case, the film forming apparatus 10 is reduced in size by the amount of the branch chamber 12 being eliminated.
【００１９】又、上記の実施例では各製膜室での製膜時
間を２分及び４分としたが、所望する半導体層の層厚、
各製膜室での半導体層の製膜速度、及び製膜室数によっ
て、任意に変更することもできる。ただ、各出口室で所
定時間毎に基板を取り出すのならば、第５ａ製膜室２４
ａ、第６ａ製膜室２６ａ及び第５ｂ製膜室２４ｂから第
１３ｂ製膜室３２ｂの各製膜室での製膜時間は、第１製
膜室１６から第４製膜室２２の各製膜室での製膜時間の
整数倍の製膜時間になる。In the above embodiment, the film forming time in each film forming chamber is set to 2 minutes and 4 minutes.
It can be arbitrarily changed depending on the film forming speed of the semiconductor layer in each film forming chamber and the number of film forming chambers. However, if the substrate is taken out from each outlet chamber at a predetermined time interval, the 5a film forming chamber 24a
a, The film forming time in each of the film forming chambers from the 6a film forming chamber 26a and the 5b film forming chamber 24b to the 13th film forming chamber 32b is set in each of the film forming chambers from the first film forming chamber 16 to the fourth film forming chamber 22. The film forming time is an integral multiple of the film forming time in the film forming chamber.
【００２０】上記した実施例によりアモルファスシリコ
ン半導体層とハイブリッド太陽電池の半導体層を１つの
製膜装置で製作が可能になったが、当然、どちらか一方
の半導体層のみを製膜することも可能である。例えば、
アモルファスシリコン半導体層を製膜している時は、第
５ｂ製膜室２４ｂから第１３ｂ製膜室３２ｂが稼働しな
いので、第５ｂ製膜室２４ｂから第１３ｂ製膜室３２ｂ
のメンテナンスを行なうことができる。又、ハイブリッ
ド太陽電池の半導体層のみを製膜している時も同様であ
る。According to the above embodiment, the amorphous silicon semiconductor layer and the semiconductor layer of the hybrid solar cell can be manufactured by one film forming apparatus. However, it is also possible to form only one of the semiconductor layers. It is. For example,
When the amorphous silicon semiconductor layer is being formed, since the 5b-th film forming chamber 24b to the 13th-th film forming chamber 32b do not operate, the 5b-th film forming chamber 24b to the 13th-th film forming chamber 32b are not operated.
Maintenance can be performed. The same applies when only the semiconductor layer of the hybrid solar cell is formed.
【００２１】又、上記した製膜装置１０は、分岐室１２
によってアモルファスシリコン半導体層とハイブリッド
太陽電池の半導体層の製膜室を分けることができたが、
図２のように、アモルファスシリコン半導体層の製膜を
第１製膜室１６から第５製膜室２３で行なった後、ポリ
シリコン半導体層を製膜する製膜室と第１出口室３４ａ
に分岐することによっても可能である。これは、第５製
膜室２３までにアモルファスシリコン半導体層が製膜さ
れた基板３６が分岐室１２に入ったとき、アモルファス
シリコン半導体層が積層された基板３６を取り出す場合
は、第１出口室３４ａへ基板３６が送られる。又、ハイ
ブリッド太陽電池の半導体層を製膜する場合は、第６製
膜室２５に基板３６が送られて、第６製膜室２５以降の
製膜室でポリシリコン半導体層が製膜（第６製膜室では
ポリシリコン半導体層のｐ層、第７製膜室２７から第１
０製膜室２９ではポリシリコン半導体層のｉ層、第１１
製膜室３１ではポリシリコン半導体層のｎ層の製膜）さ
れる。そして、第２出口室３４ｂでハイブリッド太陽電
池が積層された基板３６が取り出される。Further, the above-described film forming apparatus 10 includes a branch chamber 12
This allowed the separation chambers for the amorphous silicon semiconductor layer and the semiconductor layer of the hybrid solar cell to be separated,
As shown in FIG. 2, after the amorphous silicon semiconductor layer is formed from the first film forming chamber 16 to the fifth film forming chamber 23, the film forming chamber for forming the polysilicon semiconductor layer and the first outlet chamber 34a are formed.
It is also possible by branching to. This is because when the substrate 36 on which the amorphous silicon semiconductor layer is formed by the fifth film forming chamber 23 enters the branching chamber 12 and the substrate 36 on which the amorphous silicon semiconductor layer is stacked is taken out, the first outlet chamber is used. The substrate 36 is sent to 34a. When the semiconductor layer of the hybrid solar cell is formed, the substrate 36 is sent to the sixth film forming chamber 25, and the polysilicon semiconductor layer is formed in the film forming chambers after the sixth film forming chamber 25 (the second film forming chamber 25). In the sixth film forming chamber, the p-layer of the polysilicon semiconductor layer is used.
In the film forming chamber 29, the i-layer of the polysilicon semiconductor layer, the eleventh layer
In the film forming chamber 31, an n-layer polysilicon semiconductor layer is formed. Then, the substrate 36 on which the hybrid solar cells are stacked is taken out from the second outlet chamber 34b.
【００２２】このようにすると、図８（ｂ）の装置でア
モルファスシリコン半導体層を製膜しようとした場合
に、第９製膜室１３４から第１６製膜室１４０は、基板
３６が通過するだけの部屋になっていたが、分岐室１２
と第１出口室３４ａによって、ポリシリコン半導体層を
製膜する製膜室を通過せずとも、アモルファスシリコン
半導体層が積層された基板３６を取り出すことができる
ようになった。又、第６製膜室２５以降の製膜室をメン
テナンスしている間に、アモルファスシリコン半導体層
を製膜する事が可能である。In this way, when the amorphous silicon semiconductor layer is to be formed by the apparatus shown in FIG. 8B, the ninth film forming chamber 134 to the sixteenth film forming chamber 140 are only required to pass the substrate 36. Room, but it was a branch room 12
With the first outlet chamber 34a, the substrate 36 on which the amorphous silicon semiconductor layer is laminated can be taken out without passing through the film forming chamber for forming the polysilicon semiconductor layer. Further, the amorphous silicon semiconductor layer can be formed while the film forming chambers after the sixth film forming chamber 25 are being maintained.
【００２３】以上、１つの分岐室によって基板が次に移
動する製膜室又は出口室を振り分けたが、分岐室を複数
にして更に多種の半導体層を積層することも可能であ
る。図３にその１例を示す。図３に示す製膜装置４０
は、２つの分岐室が設置されている。先ず、第１製膜室
１６でアモルファスシリコン半導体層のｐ層、及び、第
２製膜室１８から第３製膜室２０でアモルファスシリコ
ン半導体層のｉ層の製膜が行なわれる。そして、第３製
膜室２０での製膜後に、基板３６は第１分岐室６０ａで
第４ａ製膜室４２ａか第４ｂ製膜室４２ｂに振り分けら
れる。第４ｂ製膜室４２ｂに入った基板３６は、その
後、基板３６上にアモルファスシリコン半導体層のｎ層
とｐｉｎ型ポリシリコン半導体層が積層されて（第４ｂ
製膜室４２ｂではアモルファスシリコン半導体層のｎ
層、第５ｂ製膜室４４ｂではポリシリコン半導体層のｐ
層、第６ｂ製膜室４６ｂから第９ｂ製膜室５２ｂではポ
リシリコン半導体層のｉ層、第１０ｂ製膜室５４ｂでは
ポリシリコン半導体層のｎ層の積層）、第２出口室５８
ｂで取り出される。第４ａ製膜室４２ａに送られた基板
３６は、第４ａ製膜室４２ａでアモルファスシリコン半
導体層のｉ層の積層が終えたあと、第２分岐室６０ｂで
第５ａ製膜室４４ａか第５ｃ製膜室４４ｃに送られる。
第５ａ製膜室４４ａに送られた基板３６は第５ａ製膜室
４４ａ以降、第５ａ製膜室４４ａから第７ａ製膜室４８
ａでアモルファスシリコン半導体層のｉ層、及び、第８
ａ製膜室５０ａでｎ層の製膜をして第１出口室５８ａで
取り出される。又、第５ｃ製膜室４４ｃに送られた基板
３６は第５ｃ製膜室４４ｃ以降、アモルファスシリコン
半導体層のｎ層とｐｉｎ型ポリシリコン半導体層を積層
して（第５ｃ製膜室４４ｃではアモルファスシリコン半
導体層のｎ層、第６ｃ製膜室４６ｃではポリシリコン半
導体層のｐ層、第７ｃ製膜室４８ｃから第１０ｃ製膜室
５４ｃではポリシリコン半導体層のｉ層、第８ｃ製膜室
５６ｃではポリシリコン半導体層のｎ層の製膜）、第３
出口室５８ｃで取り出される。このようにすると、アモ
ルファスシリコン半導体層と２種類のハイブリッド太陽
電池の半導体層が１つの製膜装置で製作することができ
る。As described above, the film-forming chamber or the outlet chamber in which the substrate moves next is divided by one branch chamber. However, it is also possible to use a plurality of branch chambers and further laminate various kinds of semiconductor layers. FIG. 3 shows one example. The film forming apparatus 40 shown in FIG.
Has two branch rooms. First, the p-layer of the amorphous silicon semiconductor layer is formed in the first film forming chamber 16 and the i-layer of the amorphous silicon semiconductor layer is formed in the second film forming chamber 18 to the third film forming chamber 20. After the film formation in the third film forming chamber 20, the substrate 36 is sorted in the first branch chamber 60a into the fourth film forming chamber 42a or the fourth film forming chamber 42b. The substrate 36 that has entered the 4b film-forming chamber 42b is then formed by stacking an n-layer of an amorphous silicon semiconductor layer and a pin-type polysilicon semiconductor layer on the substrate 36 (4b
In the film forming chamber 42b, the n of the amorphous silicon semiconductor layer
In the fifth and fifth film-forming chambers 44b, the p of the polysilicon semiconductor layer
The i-layer of the polysilicon semiconductor layer in the 6b film-forming chamber 46b to the ninth film-forming chamber 52b, the n-layer of the polysilicon semiconductor layer in the 10b film-forming chamber 54b), the second outlet chamber 58
It is taken out at b. The substrate 36 sent to the 4a film-forming chamber 42a, after the lamination of the i-layer of the amorphous silicon semiconductor layer is completed in the 4a film-forming chamber 42a, and then the 5a film-forming chamber 44a or 5c in the second branch chamber 60b. It is sent to the film forming chamber 44c.
The substrate 36 sent to the 5a film forming chamber 44a is moved from the 5a film forming chamber 44a to the 7a film forming chamber 48 after the 5a film forming chamber 44a.
a, the i-layer of the amorphous silicon semiconductor layer;
An n-layer film is formed in the a film forming chamber 50a, and is taken out in the first outlet chamber 58a. Further, the substrate 36 sent to the 5c film forming chamber 44c is formed by stacking an n-layer of an amorphous silicon semiconductor layer and a pin-type polysilicon semiconductor layer after the 5c film forming chamber 44c (in the 5c film forming chamber 44c, The n layer of the silicon semiconductor layer, the p layer of the polysilicon semiconductor layer in the 6c film forming chamber 46c, the i layer of the polysilicon semiconductor layer in the 7c film forming chamber 48c to the 10c film forming chamber 54c, and the 8c film forming chamber 56c. In this case, an n-layer polysilicon semiconductor layer is formed.)
It is taken out in the outlet chamber 58c. In this way, the amorphous silicon semiconductor layer and the semiconductor layers of the two types of hybrid solar cells can be manufactured by one film forming apparatus.
【００２４】なお、この時の各製膜室での製膜時間の１
例として、第１製膜室１６から第３製膜室２０までの各
室製膜時間を１分、第４ａ製膜室４２ａ及び第４ｂ製膜
室４２ｂから第１０ｂ製膜室５４ｂまでの各室製膜時間
を２分、及び、第５ａ製膜室４４ａから第８ａ製膜室５
０ａ、及び、第５ｃ製膜室４４ｃから第１１ｃ製膜室５
６ｃの製膜時間を４分にすれば、第２出口室５８ｂでは
２分ごと、第１出口室５８ａ及び第３出口室５８ｃでは
４分ごとに基板３６が取り出されることになる。なお、
各製膜室での製膜時間は、製作する半導体層の層厚、製
膜速度、及び製膜室数によって任意に変更することがで
きる。又、いずれかの製膜室をメンテナンスしている間
に他の製膜室を利用して、半導体層の積層を行なうこと
も可能である。In this case, one time of the film forming time in each film forming chamber is set.
As an example, the film forming time from the first film forming chamber 16 to the third film forming chamber 20 is 1 minute, and each of the 4a film forming chamber 42a and the 4b film forming chamber 42b to the 10th film forming chamber 54b. The chamber deposition time was 2 minutes, and the 5a deposition chamber 44a to the 8a deposition chamber 5
0a and the 5c film-forming chamber 44c to the 11c film-forming chamber 5
If the film forming time of 6c is set to 4 minutes, the substrate 36 is taken out every two minutes in the second outlet chamber 58b and every four minutes in the first outlet chamber 58a and the third outlet chamber 58c. In addition,
The deposition time in each deposition chamber can be arbitrarily changed depending on the thickness of the semiconductor layer to be produced, the deposition rate, and the number of deposition chambers. It is also possible to stack semiconductor layers by using another film forming chamber while maintaining one of the film forming chambers.
【００２５】更に、分岐室を用いた製膜装置のみを上記
に説明したが、複数の製膜室から来た基板を集合させる
集合室を用いて製膜を行なうことも可能である。その例
を図４に示す。第１製膜室１６と第２製膜室１８でそれ
ぞれアモルファスシリコンのｐ層とｉ層を製膜した後、
基板３６は分岐室１２で第３ａ製膜室７２ａか第３ｂ製
膜室７２ｂに振り分けられて送られる。第３ａ製膜室７
２ａに送られた基板３６は第３ａ製膜室７２ａから第５
ａ製膜室７６ａまで、アモルファスシリコン半導体層の
ｉ層を製膜される。又、第３ｂ製膜室７２ｂに送られた
基板３６は第３ｂ製膜室７２ｂで、アモルファスシリコ
ン半導体層のｎ層を製膜したあと、更に第４ｂ製膜室７
４ｂ及び第５ｂ製膜室７６ｂでそれぞれアモルファスシ
リコン半導体層のｐ層とｉ層が製膜される。そして、第
５ａ製膜室７６ａ及び第５ｂ製膜室７６ｂで製膜が終了
した基板３６は集合室８２に送られた後、第６製膜室７
８に送られてアモルファスシリコン半導体層のｎ層が積
層される。Further, only the film forming apparatus using the branch chamber has been described above, but it is also possible to form a film using a collecting chamber for collecting substrates coming from a plurality of film forming chambers. An example is shown in FIG. After forming a p-layer and an i-layer of amorphous silicon in the first film forming chamber 16 and the second film forming chamber 18 respectively,
The substrate 36 is divided and sent to the 3a film forming chamber 72a or the 3b film forming chamber 72b in the branch chamber 12. 3a film forming chamber 7
The substrate 36 sent to 2a is moved from the 3a film forming chamber 72a to the 5th
The i-layer of the amorphous silicon semiconductor layer is formed up to the film forming chamber 76a. The substrate 36 sent to the third-b film-forming chamber 72b is used to form the n-layer of the amorphous silicon semiconductor layer in the third-b film-forming chamber 72b, and then further to the fourth-b film-forming chamber 7b.
The p layer and the i layer of the amorphous silicon semiconductor layer are formed in the 4b and 5b film forming chambers 76b, respectively. Then, the substrate 36 whose film formation has been completed in the 5a film formation chamber 76a and the 5b film formation chamber 76b is sent to the collecting chamber 82, and then the sixth film formation chamber 7 is formed.
8, the n layers of the amorphous silicon semiconductor layers are stacked.
【００２６】なお、集合室８２に入った台車の方向転換
は、集合室の床面にターンテーブル等を設置して、回動
させることによって行なったり、台車を上方移動レール
よりつり下げている機構では、上方移動レールを回動す
る等して行なう。又、各製膜室での製膜時間は、第１製
膜室１６、第２製膜室１８及び第６製膜室７８での各室
製膜時間を２分にすると、第３ａ製膜室７２ａから第５
ａ製膜室７６ａ及び第３ｂ製膜室７２ｂから第５ｂ製膜
室７６ｂでの各室製膜時間は４分になる。このようにす
ることによって、出口室８０からはｐｉｎ型アモルファ
スシリコン半導体層が製膜された基板３６とｐｉｎ型ア
モルファスシリコン半導体層が２層になった基板３６が
交互に取り出される。又、第３ａ製膜室７２ａから第５
ａ製膜室７６ａまでをメンテナンスしている間は、第３
ｂ製膜室７２ｂから第５ｂ製膜室７６ｂを利用して半導
体層を積層することが可能であり、その逆も可能であ
る。The direction of the truck entering the collective room 82 can be changed by installing a turntable or the like on the floor of the collective room and rotating it, or by suspending the truck from the upper moving rail. Then, the upward movement rail is rotated or the like. When the film forming time in each of the first film forming chamber 16, the second film forming chamber 18, and the sixth film forming chamber 78 is set to 2 minutes, the film forming time in each film forming chamber is 3a. From room 72a to the fifth
The film forming time in each of the film forming chambers 76a and 76b from the third film forming chamber 72b to the fifth film forming chamber 76b is 4 minutes. By doing so, the substrate 36 on which the pin-type amorphous silicon semiconductor layer is formed and the substrate 36 on which the pin-type amorphous silicon semiconductor layer has two layers are alternately taken out from the outlet chamber 80. In addition, the third film-forming chamber 72a to the fifth
a During maintenance to the film forming chamber 76a, the third
The semiconductor layers can be stacked using the fifth film forming chamber 76b from the b film forming chamber 72b, and vice versa.
【００２７】以上、本発明に係る半導体層の積層装置及
び積層方法は、インライン方式の製膜装置において、製
膜室が途中で分岐することによって多種の半導体層の積
層が１つの製膜装置で行なうことができる。又、ある製
膜室をメンテナンス中に他の製膜室を利用して製膜を行
なうことができる。よって、柔軟性の高い製膜装置の利
用ができる。更に、複数の製膜室から送られてくる基板
を集める集合室を設けることも可能であり、分岐室と集
合室を組み合わせることによって、かなり融通のきく製
膜装置を構成することができる。As described above, according to the semiconductor layer laminating apparatus and the laminating method according to the present invention, in the in-line type film forming apparatus, the lamination of various kinds of semiconductor layers can be performed in one film forming apparatus by branching the film forming chamber in the middle. Can do it. Further, a film can be formed by using another film forming chamber while maintaining a certain film forming chamber. Therefore, a highly flexible film forming apparatus can be used. Furthermore, it is also possible to provide a collecting chamber for collecting substrates sent from a plurality of film forming chambers, and by combining the branching chamber and the collecting chamber, it is possible to configure a film forming apparatus which is quite flexible.
【００２８】更に、上記の半導体層の積層装置は、他種
の半導体層を１つの製膜装置で製作できたが、１種類の
半導体層を積層することも可能である。その１実施例を
図５に示す。第１製膜室１６でアモルファスシリコン半
導体層のｐ層を積層した後に、ｉ層を積層する製膜室を
分岐している。そして、第７ａ製膜室１７４ａ及び第７
ｂ製膜室１７４ｂでｉ層の積層後に、集合室８２に送ら
れて、第８製膜室１７６に入ってｎ層の製膜が行なわれ
る。例えば、第１製膜室１６での各室製膜時間を２分と
すると、第２ａ製膜室１７２ａから第７ａ製膜室１７４
ａ及び第２ｂ製膜室１７２ｂから第７ｂ製膜室１７４ｂ
での各室製膜時間は４分で、且つ、第８製膜室１７６で
の各室製膜時間は２分になる。そして、出口室１７８で
は２分ごとに基板が取り出される。Further, in the above-described semiconductor layer laminating apparatus, another kind of semiconductor layer can be manufactured by one film forming apparatus, but one kind of semiconductor layer can also be stacked. One embodiment is shown in FIG. After the p-layer of the amorphous silicon semiconductor layer is stacked in the first film-forming chamber 16, the film-forming chamber in which the i-layer is stacked is branched. Then, the 7a film forming chamber 174a and the seventh
After the i-layer is stacked in the b-film forming chamber 174b, the i-layer is sent to the collecting chamber 82, and enters the eighth film-forming chamber 176, where the n-layer is formed. For example, assuming that the film forming time of each chamber in the first film forming chamber 16 is 2 minutes, the second film forming chamber 172a to the 7a film forming chamber 174 are used.
a and the second b film forming chamber 172b to the seventh b film forming chamber 174b
Is 4 minutes, and the film forming time in the eighth film forming chamber 176 is 2 minutes. Then, the substrate is taken out of the outlet chamber 178 every two minutes.
【００２９】又、本発明に係る半導体層の積層装置及び
積層方法は、上記に記した積層装置に限られることはな
い。例えば、図６に示すような製膜装置９０にしてもよ
い。図５に示す製膜装置９０は、第１入口室１１２ａ及
び第２入口室１１２ｂのそれぞれより基板を搬入するこ
とができ、第１ａ製膜室９２ａから第３ａ製膜室９６ｂ
及び第１ｂ製膜室９２ｂから第４ｂ製膜室９８ｂでは、
それぞれｉ層の層厚が異なるｐｉｎ型アモルファスシリ
コン半導体層が積層される。そして、第３ａ製膜室９６
ａ及び第４ｂ製膜室９８ｂでの製膜が完了した後、集合
室１１０に基板は送られる。集合室１１０に送られた基
板は第５ａ製膜室１００ａ、第５ｂ製膜室１００ｂ又は
第３出口室１０８ｃに送られる。第３出口室１０８ｃに
送られた基板は、第１ａ製膜室９２ａから第３ａ製膜室
９６ａ及び第１ｂ製膜室９２ｂから第４ｂ製膜室９８ｂ
で製膜されたｉ層の層厚が異なるアモルファスシリコン
半導体層が取り出される。又、第５ａ製膜室１００ａに
送られた基板は第５ａ製膜室１００ａから第８ａ製膜室
１０６ａでｐｉｎ型アモルファスシリコン半導体層が製
膜される。よって、第１出口室１０８ａより、ｐｉｎ型
アモルファスシリコン半導体層が２層になった基板が取
り出される。更に、第５ｂ製膜室１００ｂに送られた基
板は第５ｂ製膜室１００ｂから第８ｂ製膜室１０６ｂで
ポリシリコン半導体層が積層される。よって、第２出口
室１０８ｂからはハイブリッド太陽電池の半導体層が積
層された基板が取り出される。以上の積層装置を用いる
と、６種類の半導体層の製膜が可能になり、ある製膜室
でメンテナンスを行なっている間も、他の製膜室を利用
して半導体層の積層を行なうことができる。The apparatus and method for stacking semiconductor layers according to the present invention are not limited to the above-described apparatus. For example, a film forming apparatus 90 as shown in FIG. 6 may be used. In the film forming apparatus 90 shown in FIG. 5, a substrate can be loaded from each of the first inlet chamber 112a and the second inlet chamber 112b, and the first film forming chamber 92a can be moved from the first film forming chamber 92a to the third film forming chamber 96b.
And in the 1b film forming chamber 92b to the 4b film forming chamber 98b,
Pin-type amorphous silicon semiconductor layers having different i-layer thicknesses are stacked. Then, the 3a film forming chamber 96
After the film formation in the film forming chambers 98a and 98b is completed, the substrate is sent to the collecting chamber 110. The substrate sent to the collecting chamber 110 is sent to the 5a-th film forming chamber 100a, the 5b-th film forming chamber 100b, or the third outlet chamber 108c. The substrates sent to the third outlet chamber 108c are converted from the first film forming chamber 92a to the third film forming chamber 96a and the first film forming chamber 92b to the fourth film forming chamber 98b.
An amorphous silicon semiconductor layer having a different layer thickness of the i-layer formed by the above is taken out. On the substrate sent to the 5a-th film forming chamber 100a, a pin type amorphous silicon semiconductor layer is formed from the 5a-th film forming chamber 100a to the 8a-th film forming chamber 106a. Therefore, a substrate having two pin-type amorphous silicon semiconductor layers is taken out from the first outlet chamber 108a. Further, a polysilicon semiconductor layer is stacked on the substrate sent to the 5b film forming chamber 100b from the 5b film forming chamber 100b to the 8b film forming chamber 106b. Therefore, the substrate on which the semiconductor layers of the hybrid solar cell are stacked is taken out from the second outlet chamber 108b. With the use of the above-described laminating apparatus, it is possible to form six types of semiconductor layers, and to perform lamination of semiconductor layers using another film forming chamber while performing maintenance in one film forming chamber. Can be.
【００３０】又、図６の積層装置は、入口室及び出口室
がそれぞれ２室と３室になっていたが、図７のように、
分岐室を１室及び集合室を２室設ければ入口室及び出口
室をそれぞれ１室にすることが可能である。この方式に
あっては、第１ａ製膜室９２ａから第３ａ製膜室９６ａ
又は、第１ｂ製膜室９２ｂから第４ｂ製膜室９８ｂでの
製膜で、製膜を終了する場合は、集合室１５４の次に移
送室１６２に送られて、移送室１６２では製膜を行なわ
ずに集合室１５６に送られる。又、集合室１５４に入っ
た基板に更に製膜を行なうならば、ｐｉｎ型アモルファ
スシリコン半導体層を積層するのならば第５ａ製膜室１
００ａに送られ、ｐｉｎ型ポリシリコン半導体層を積層
するのならば第５ｂ製膜室１００ｂに送られる。よっ
て、図６の積層装置と同じように、６種類の半導体層の
製膜が可能になり、ある製膜室でメンテナンスを行なっ
ている間も、他の製膜室を利用して半導体層の積層を行
なうことができる。In the laminating apparatus shown in FIG. 6, the inlet chamber and the outlet chamber are respectively two chambers and three chambers.
If one branch room and two gathering rooms are provided, it is possible to make the inlet room and the outlet room one each. In this method, the first film forming chamber 92a is moved from the first film forming chamber 92a to the third film forming chamber 96a.
Alternatively, when the film formation is completed in the film formation in the 1b film formation chamber 92b to the 4b film formation chamber 98b, the film is sent to the transfer chamber 162 next to the collecting chamber 154, and the film formation is performed in the transfer chamber 162. It is sent to the collecting room 156 without performing. Further, if a film is to be further formed on the substrate in the collecting chamber 154, if a pin type amorphous silicon semiconductor layer is to be laminated, the 5a-th film forming chamber 1
00a, and if a pin-type polysilicon semiconductor layer is to be laminated, it is sent to the 5b film-forming chamber 100b. Therefore, as in the case of the laminating apparatus shown in FIG. 6, it is possible to form six types of semiconductor layers, and while performing maintenance in a certain film forming chamber, use another film forming chamber to form a semiconductor layer. Lamination can be performed.
【００３１】以上の説明ではｐｉｎ型アモルファスシリ
コン半導体層及びｐｉｎ型ポリシリコン半導体層を積層
していたが、ｎｉｐ型アモルファスシリコン半導体層及
びｎｉｐ型ポリシリコン半導体層の積層においても、同
様のことができる。又、上記以外の半導体層の積層にお
いても同じである。In the above description, the pin-type amorphous silicon semiconductor layer and the pin-type polysilicon semiconductor layer are stacked, but the same can be applied to the stack of the nip-type amorphous silicon semiconductor layer and the nip-type polysilicon semiconductor layer. . The same applies to the stacking of semiconductor layers other than those described above.
【００３２】以上の説明で得られた半導体層の積層方法
及び該積層装置は、これに限定されるものではない。そ
の他、本発明はその趣旨を逸脱しない範囲内で、当業者
の知識に基づき種々なる改良、修正、変形を加えた態様
で実施し得るものである。The method and apparatus for laminating semiconductor layers obtained in the above description are not limited to the above. In addition, the present invention can be carried out in various modified, modified, and modified embodiments based on the knowledge of those skilled in the art without departing from the spirit of the present invention.
【００３３】[0033]
【発明の効果】本発明に係る半導体層の積層方法及び積
層装置は、複数の製膜室が直列的に接続されたインライ
ン方式の製膜装置において、製膜室の途中に分岐室を備
えることによって、基板が次に送られる製膜室を振り分
けることができた。このことは、複数種の半導体層が１
つの製膜装置で混合して製膜すること可能にした。よっ
て、複数種の半導体層をそれぞれの基板に積層するのに
全ての半導体層のための積層装置を取りそろえる必要は
ない。更に、ある製膜室のメンテナンスを行なっている
時は、他の製膜室を使って製膜を行なうことが可能で、
製膜装置の使用にあってはかなりの柔軟性を持ってい
る。又、複数の製膜室から送られてくる基板を集める集
合室を備えることによって、更に、柔軟性を持った製膜
装置及び製膜方法を提供することが可能である。又、前
記分岐室及び集合室において製膜を行なうことも可能で
ある。According to the method and apparatus for laminating semiconductor layers according to the present invention, in a film forming apparatus of an in-line type in which a plurality of film forming chambers are connected in series, a branch chamber is provided in the middle of the film forming chamber. With this, the film forming chamber to which the substrate was sent next could be sorted. This means that a plurality of types of semiconductor layers
It was made possible to form a film by mixing with two film forming devices. Therefore, it is not necessary to provide a stacking device for all the semiconductor layers in order to stack a plurality of types of semiconductor layers on each substrate. Furthermore, when maintenance is being performed on a certain deposition chamber, it is possible to perform deposition using another deposition chamber.
There is considerable flexibility in the use of film forming equipment. Further, by providing a collecting chamber for collecting substrates sent from a plurality of film forming chambers, it is possible to provide a film forming apparatus and a film forming method having more flexibility. It is also possible to form a film in the branching chamber and the collecting chamber.
【図１】本発明に係る半導体層の積層装置の１実施形態
を示す図。FIG. 1 is a diagram showing one embodiment of a semiconductor layer laminating apparatus according to the present invention.
【図２】本発明に係る半導体層の積層装置の他の実施形
態を示す図。FIG. 2 is a view showing another embodiment of a semiconductor layer laminating apparatus according to the present invention.
【図３】本発明に係る半導体層の積層装置で、分岐室を
２つ設置した場合の実施形態を示す図。FIG. 3 is a view showing an embodiment in which two branch chambers are installed in the semiconductor layer laminating apparatus according to the present invention.
【図４】本発明に係る半導体層の積層装置で、分岐室及
び集合室を設けた場合の実施形態を示す図。FIG. 4 is a diagram showing an embodiment in which a branch chamber and a collective chamber are provided in the semiconductor layer laminating apparatus according to the present invention.
【図５】本発明に係る半導体層の積層装置で、分岐室及
び集合室を設けた場合の実施形態を示す図。FIG. 5 is a diagram showing an embodiment in which a branch chamber and a collective chamber are provided in the semiconductor layer laminating apparatus according to the present invention.
【図６】本発明に係る半導体層の積層装置で、入口室を
２つ設けた場合の実施形態を示す図。FIG. 6 is a view showing an embodiment in which two entrance chambers are provided in the semiconductor layer laminating apparatus according to the present invention.
【図７】本発明に係る半導体層の積層装置で、分岐室及
び集合室を設けた場合の実施形態を示す図。FIG. 7 is a diagram showing an embodiment in which a branch chamber and a collective chamber are provided in the semiconductor layer laminating apparatus according to the present invention.
【図８】従来技術であるアモルファスシリコン半導体層
の積層装置（ａ）及びハイブリッド太陽電池の半導体層
の積層装置（ｂ）の図。FIGS. 8A and 8B are diagrams of a conventional apparatus for stacking an amorphous silicon semiconductor layer (a) and a semiconductor layer for a hybrid solar cell (b).
１０，２１，４０，７０，９０，１２０，１２１，１４
２，１５０，１７０：半導体層の積層装置 １２，８２，１５２：分岐室 １４，１３０，１５８：入口室 １６，１２２：第１製膜室 １８，１２４：第２製膜室 ２０：第３製膜室 ２２：第４製膜室 ２３：第５製膜室 ２４ａ，４４ａ，７６ａ，１００ａ：第５ａ製膜室 ２４ｂ，４４ｂ，７６ｂ，１００ｂ：第５ｂ製膜室 ２５，７８：第６製膜室 ２６ａ，１０２ａ：第６ａ製膜室 ２６ｂ，４６ｂ，１０２ｂ：第６ｂ製膜室 ２７，１２６：第７製膜室 ２８ｂ，１０４ｂ，１７４ｂ：第７ｂ製膜室 ２９，１３６：第１０製膜室 ３０ｂ：第１２ｂ製膜室 ３１：第１１製膜室 ３２ｂ：第１３ｂ製膜室 ３４ａ，５８ａ，１０８ａ：第１出口室 ３４ｂ，５８ｂ，１０８ｂ：第２出口室 ３６，３６ａ，３６ｂ：基板 ４２ａ：第４ａ製膜室 ４２ｂ，７４ｂ，９８ｂ：第４ｂ製膜室 ４４ｃ：第５ｃ製膜室 ４６ｃ：第６ｃ製膜室 ４８ａ，１０４ａ，１７４ａ：第７ａ製膜室 ４８ｃ：第７ｃ製膜室 ５０ａ，１０６ａ：第８ａ製膜室 ５２ｂ：第９ｂ製膜室 ５４ｂ：第１０ｂ製膜室 ５４ｃ：第１０ｃ製膜室 ５６ｃ：第１１ｃ製膜室 ５８ｃ，１０８ｃ：第３出口室 ６０ａ：第１分岐室 ６０ｂ：第２分岐室 ７２ａ，９６ａ：第３ａ製膜室 ７２ｂ，９６ｂ：第３ｂ製膜室 ８０，１３２，１７８：出口室 ８２，１１０：集合室 ９２ａ：第１ａ製膜室 ９２ｂ：第１ｂ製膜室 ９４ａ，１７２ａ：第２ａ製膜室 ９４ｂ，１７２ｂ：第２ｂ製膜室 １０６ｂ：第８ｂ製膜室 １１２ａ：第１入口室 １１２ｂ：第２入口室 １２８，１７６：第８製膜室 １３４：第９製膜室 １３８：第１５製膜室 １４０：第１６製膜室 １５４：第１集合室 １５６：第１集合室 １６２：移送室10, 21, 40, 70, 90, 120, 121, 14
2, 150, 170: semiconductor layer laminating apparatus 12, 82, 152: branch chamber 14, 130, 158: inlet chamber 16, 122: first film forming chamber 18, 124: second film forming chamber 20: third product Film forming room 22: Fourth film forming room 23: Fifth film forming room 24a, 44a, 76a, 100a: 5a film forming room 24b, 44b, 76b, 100b: 5th film forming room 25, 78: Sixth film forming room Chambers 26a, 102a: 6a film forming chamber 26b, 46b, 102b: 6b film forming chamber 27, 126: 7th film forming chamber 28b, 104b, 174b: 7b film forming chamber 29, 136: 10th film forming chamber 30b: 12th film forming chamber 31: 11th film forming chamber 32b: 13th film forming chamber 34a, 58a, 108a: first outlet chamber 34b, 58b, 108b: second outlet chamber 36, 36a, 36b: substrate 42a: 4a film forming chamber 42b, 7 b, 98b: 4b film forming chamber 44c: 5c film forming chamber 46c: 6c film forming chamber 48a, 104a, 174a: 7a film forming chamber 48c: 7c film forming chamber 50a, 106a: 8a film forming chamber 52b: 9b film-forming chamber 54b: 10th film-forming chamber 54c: 10c film-forming chamber 56c: 11c film-forming chamber 58c, 108c: third outlet chamber 60a: first branch chamber 60b: second branch chamber 72a, 96a: 3a film forming chamber 72b, 96b: 3b film forming chamber 80, 132, 178: outlet chamber 82, 110: collecting chamber 92a: 1a film forming chamber 92b: 1b film forming chamber 94a, 172a: 2a Film forming chambers 94b, 172b: 2b film forming chamber 106b: 8th film forming chamber 112a: first inlet chamber 112b: second inlet chamber 128, 176: eighth film forming chamber 134: ninth film forming chamber 138: eighth 15 film forming room 140: 16th Film forming chamber 154: First collecting chamber 156: First collecting chamber 162: Transfer chamber
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4K030 BA29 BA30 BB03 BB12 GA12 HA01 KA08 LA16 5F045 AA08 AB03 AB04 AC01 BB08 BB10 CA13 DA52 DP21 DQ15 EB08 EB09 EN04 5F051 AA03 AA05 BA11 BA14 CB12 CB29 CB30 DA02 DA04 DA16 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4K030 BA29 BA30 BB03 BB12 GA12 HA01 KA08 LA16 5F045 AA08 AB03 AB04 AC01 BB08 BB10 CA13 DA52 DP21 DQ15 EB08 EB09 EN04 5F051 AA03 AA05 BA11 BA14 CB12 CB29 CB30 DA04
Claims (6)
ら該基板上に所定構造の半導体層を順次積層する半導体
層の積層方法において、 該基板が少なくともいずれか一つの製膜室から次に進む
製膜室を複数設けて、該基板が次に入る製膜室を決定す
る工程を含むことを特徴とする半導体層の積層方法。1. A method for laminating a semiconductor layer having a predetermined structure on a substrate while sequentially moving the substrate through a plurality of film forming chambers, wherein the substrate is moved from at least one of the film forming chambers to the next. Providing a plurality of film-forming chambers proceeding to the step (a), and determining a film-forming chamber into which the substrate enters next.
程後に、該基板を決定された製膜室に移送する工程を含
む請求項１記載の半導体層の積層方法。2. The method according to claim 1, further comprising a step of transferring the substrate to the determined film forming chamber after the step of determining a film forming chamber into which the substrate enters next.
ら基板上に所定構造の半導体層を順次積層する半導体層
の積層方法において、 複数の該製膜室から順次移動してくる基板を、１つの製
膜室に順番に取り込む工程を含むことを特徴とする半導
体層の積層方法。3. A method for laminating semiconductor layers having a predetermined structure on a substrate while sequentially moving the substrate through a plurality of film forming chambers, wherein the substrate sequentially moving from the plurality of film forming chambers is provided. A method of laminating semiconductor layers, comprising a step of sequentially taking in semiconductor films into one film forming chamber.
室に基板を移送する工程を含む請求項３記載の半導体層
の積層方法。4. The method according to claim 3, further comprising a step of transferring the substrate to a next film forming chamber after the step of taking in the order.
ら該基板上に所定構造の半導体層を順次積層する半導体
層の積層装置において、 該基板が少なくともいずれか一つの前記製膜室から次に
進む製膜室を複数設けて、該基板が次に入る製膜室を決
定する分岐室を含むことを特徴とする半導体層の積層装
置。5. A semiconductor layer laminating apparatus for sequentially laminating a semiconductor layer having a predetermined structure on a substrate while sequentially moving a substrate through a plurality of film forming chambers, wherein the substrate is removed from at least one of the film forming chambers. An apparatus for laminating semiconductor layers, comprising a plurality of film forming chambers to proceed to the next, and a branch chamber for determining a film forming chamber into which the substrate enters next.
ら基板上に所定構造の半導体層を順次積層する半導体層
の積層装置において、 複数の製膜室から順次移動してくる基板を、順番に取り
込む集合室を含むことを特徴とする半導体層の積層装
置。6. A semiconductor layer stacking apparatus for sequentially stacking semiconductor layers having a predetermined structure on a substrate while sequentially moving the substrate through a plurality of film forming chambers, wherein the substrate sequentially moving from the plurality of film forming chambers is An apparatus for laminating semiconductor layers, comprising a collective chamber for taking in sequentially.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33372299A JP2001155999A (en) | 1999-11-25 | 1999-11-25 | Method and device for forming semiconductor layers in layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33372299A JP2001155999A (en) | 1999-11-25 | 1999-11-25 | Method and device for forming semiconductor layers in layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001155999A true JP2001155999A (en) | 2001-06-08 |
Family
ID=18269237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33372299A Pending JP2001155999A (en) | 1999-11-25 | 1999-11-25 | Method and device for forming semiconductor layers in layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001155999A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010520369A (en) * | 2007-03-02 | 2010-06-10 | エリコン・トレーディング・アクチェンゲゼルシャフト，トリュープバッハ | Vacuum coating equipment |
| JP2017101271A (en) * | 2015-11-30 | 2017-06-08 | 株式会社フィルテック | Film deposition apparatus |
| US10036101B2 (en) | 2010-05-11 | 2018-07-31 | Qunano Ab | Gas-phase synthesis of epitaxial semiconductor wires from seed crystals |
-
1999
- 1999-11-25 JP JP33372299A patent/JP2001155999A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010520369A (en) * | 2007-03-02 | 2010-06-10 | エリコン・トレーディング・アクチェンゲゼルシャフト，トリュープバッハ | Vacuum coating equipment |
| US10036101B2 (en) | 2010-05-11 | 2018-07-31 | Qunano Ab | Gas-phase synthesis of epitaxial semiconductor wires from seed crystals |
| JP2017101271A (en) * | 2015-11-30 | 2017-06-08 | 株式会社フィルテック | Film deposition apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5016562A (en) | Modular continuous vapor deposition system | |
| CN1986872B (en) | Machine for treating substrates and method | |
| CN101268213B (en) | Device and method for continuous chemical vapour deposition under atmospheric pressure and use thereof | |
| WO2003038145A2 (en) | Chemical vapor deposition system | |
| KR20080108595A (en) | System architecture and method for solar panel formation | |
| JP2008520837A (en) | Wafer fab | |
| CN101994102A (en) | Film deposition device | |
| CN102686769A (en) | Method for depositing multi-layered layers and/or gradient layers | |
| WO1987005539A1 (en) | Deposition of materials | |
| US20020011203A1 (en) | Multi wafer introduction/single wafer conveyor mode processing system and method of processing wafers using the same | |
| CN102725439A (en) | Inline coating installation | |
| CN112236544A (en) | Continuous apparatus and method for coating substrates | |
| TW200843552A (en) | Processing device and method for processing a substrate | |
| JP2001049440A (en) | Method and device for forming plasma cvd film | |
| CN102057076A (en) | Coating system and method for coating a substrate | |
| JP2001155999A (en) | Method and device for forming semiconductor layers in layer | |
| US20130136862A1 (en) | Multi-cell mocvd apparatus | |
| CN211112215U (en) | Coating device and coating equipment | |
| JP2002083774A (en) | Film forming apparatus | |
| JP2001035798A (en) | Film-forming apparatus | |
| CN112813418B (en) | Wafer atomic layer deposition control system based on ALD technology and efficient wafer production method | |
| JP2001135583A (en) | Method and apparatus for laminating semiconductor layers | |
| CN1180926A (en) | Method of depositing films on semiconductor wafers using partial deposition and reloading techniques | |
| WO2004036634A1 (en) | Thin film forming apparatus and thin film forming method and thin film forming system | |
| CN113174589A (en) | Modular rotary space atomic layer deposition system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060926 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081107 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081119 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090319 |