JP2001068486A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法Info
- Publication number
- JP2001068486A JP2001068486A JP23696599A JP23696599A JP2001068486A JP 2001068486 A JP2001068486 A JP 2001068486A JP 23696599 A JP23696599 A JP 23696599A JP 23696599 A JP23696599 A JP 23696599A JP 2001068486 A JP2001068486 A JP 2001068486A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor chip
- copper
- polyimide
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Abstract
い、鉄合金リードフレーム品以上の信頼性を有し、しか
も低コストで半導体装置を得ること。 【解決手段】 銅合金に銅メッキを行ったリードフレー
ム1上に、ポリイミド系の接着剤3を用いて半導体チッ
プ4を接合し、金又は銅を主成分としたワイヤー5を用
いて半導体チップ4の電極とリードフレーム2の各端子
を接続した後、半導体チップとワイヤー、リードフレー
ムのワイヤーとの接合部を樹脂封止して半導体装置を得
る。
Description
に半導体チップを銅合金からなるリードフレーム上に接
合するのにポリイミド系の接着剤(ペースト)を用いた
ことを特徴とする半導体装置及びその製造方法に関する
ものである。
にリードフレームのダイパット1上にAgペースト等の
接着剤3で半導体チップ4を接合し、半導体チップ4の
電極パット6とリードフレームの各端子のインナーリー
ド部2を金線等5で接続し、それを封止樹脂で封止した
構造を有している。又、リードフレームのインナーリー
ド部2の一部分(図のハッチングの部分)には大気中で
金線5とインナーリード部が接続できるように、一般に
Agメッキが施されている。ところで、パッケージが非
常に小さい場合や、パッケージに比べダイパットが非常
に大きい場合、インナーリードが非常に短くなる設計し
か出来ず、この様な状態でインナーリード部にAgメッ
キを施すと、Agメッキがインナーリードでけで納まら
ず、パッケージの外まで漏れてしまう不具合が発生す
る。図4は、図3のインナーリード2の一部を拡大して
示した図であって、図中Pはパッケージラインを示して
いる。図示のようにメッキエリアの小さなリードフレー
ムにメッキを行った場合は、メッキがメッキエリアのM
AX値を越え、パッケージ外部に漏れることは避けられ
ない。Agメッキがパッケージ外部まで漏れてしまう
と、図5に示すようにAgのマイグレーションや耐湿信
頼性の劣化という信頼性上の重大な不具合を発生させ
る。以上の理由から、パッケージが非常に小さい場合や
パッケージに比べダイパットが非常に大きい場合は、リ
ードフレームのインナーリード部2の一部にAgメッキ
を施すには非常に困難であり、Agメッキの代わりにC
uメッキを施すのが一般的である。
ムについてみると、それが例えば42Ni等の鉄系合金
にCuメッキを施したリードフレームである場合は、半
導体チップの裏面に金を15000〜30000Å程度
蒸着し還元雰囲気中で450〜550°C程度の温度を
かけ、半導体チップをこの金によって直接リードフレー
ムのダイパット上に接合するか、ダイパット上にAuー
Siを用いて半導体チップを接合する。続いて半導体チ
ップの電極パットとリードフレームのインナーリード部
をこれも還元雰囲気下で300°C程度の温度で金又は
銅を主成分としたワイヤーで接続し半導体チップ、ワイ
ヤー、リードフレームのインナーリード部を樹脂封止し
て半導体装置を形成している。
たリードフレームが鉄合金系のリードフレームの場合に
は、チップ裏面に金を15000〜30000Å程度蒸
着し、その金で直接接合するダイレクトボンディング
か、あるいはAuーSiプリフォームを用いてボンディ
ングするかのいずれかで、半導体チップとリードフレー
ムとの接合が可能である。しかしながら、銅メッキした
リードフレームが銅合金の場合には、ダイレクトボンデ
ィングやAuーSiダイボンディングを行おうとして
も、半導体チップとリードフレームの熱膨張係数が大き
く異なるため、半導体チップとリードフレームとの接合
時の温度変化に伴う熱膨張・収縮により、半導体チップ
にクラックが発生してしまうため、この方法では製造で
きない。また、銅フレームと半導体チップを接合すると
きに、通常使用されるエポキシ樹脂系のAgペーストで
は、150°C〜200°C程度でAgペーストを硬化
させ、その後200〜250°C程度でワイヤボンディ
ングを行うが、本半導体装置は、リードフレームのイン
ナーリード部にAgメッキを施していないため、リード
フレーム表面の酸化膜を除去するために還元を行う必要
がある。短時間で還元するためには、300°C以上の
温度を与える必要がある。ところが、エポシキ樹脂系の
Agペーストは300°C以上の温度をかけると、樹脂
が熱分解し半導体チップとリードフレームとの接合信頼
性が著しく低下する。また、これを防ぐためにリードフ
レームに与える温度を300°未満に抑えると、今度
は、リードフレームのインナーリード部と金線の接合信
頼性が大きく低下し、いずれにしろ、銅合金系のリード
フレームを用いた半導体装置については十分に信頼性が
確保された製造方法は確立されていなかった。そこで、
本発明の目的は、銅合金リードフレームを用い、鉄合金
リードフレーム品よりも高い信頼性を確保できる半導体
装置を低コストな方法で得ることである。
ッキを行ったリードフレームとチップとの接合にポリイ
ミド系の接着剤を採用したことを特徴とするものであっ
て、請求項1の発明は、銅合金に銅メッキを行ったリー
ドフレーム上に、ポリイミド系の接着剤を用いて半導体
チップを接合し、金又は銅を主成分としたワイヤーを用
いて半導体チップの電極とリードフレームの各端子を接
続し、半導体チップとワイヤー、リードフレームのワイ
ヤーとの接合部を樹脂封止したことを特徴とする半導体
装置である。
を銅合金に銅メッキを行ったリードフレーム上に塗布し
て半導体チップを登載し、排気により真空雰囲気を維持
しつつ加熱して前記ポリイミド系ペーストを硬化し、次
に、還元しつつ半導体チップの電極とリードフレームの
各端子のワイヤーボンディングを行うことを特徴とする
半導体装置の製造方法である。
を銅合金に銅メッキを行ったリードフレーム上に塗布し
て半導体チップを登載し、排気により10−1〜10
−2Torr程度の真空雰囲気を維持しつつ約300°C、
約60分間 加熱して前記ポリイミド系ペーストを硬化
し、次に、約300〜450°Cのフォーミングガス中
で還元しつつ半導体チップの電極とリードフレームの各
端子のワイヤーボンディングを行うことを特徴とする半
導体装置の製造方法である。
半導体装置の製造方法において、前記フォーミングガス
はH2がおおむね5〜10%、残りがN2から成るもの
であることを特徴とする半導体装置の製造方法である。
と比べ、弾性率が約1/20であること及び、450°
Cの高温下でも数分程度なら耐えることが出来るため、
本発明は、ポリイミド系接着剤のこの特性に着目して、
これを銅合金からなるリードフレームと半導体チップと
の接着剤として用いたものである。即ち、本発明に係る
銅合金からなるリードブレームは、そのボンディングエ
リアには、既に述べたように銀メッキができないため銅
メッキが施されており、銅に直接金または銅ワイヤーを
付けて合金化しなければならない。ところがそのままワ
イヤーボンディングを行うと、銅は熱によって酸化が促
進される結果、そのままではワイヤーボンディングを行
うことはできない。そこで、フォーミングガス中で銅フ
レームの酸化を還元しながらワイヤーボンディングを行
うものであって、本発明は、銅合金系のリードフレーム
と半導体チップをポリイミド系の接着剤を用いて接合さ
せ、その後、フォーミングガス中で、銅の酸化を還元
し、かつフォーミングガス中でワイヤーボンディングを
行うようにしたのである。
工程について図1を参考にして説明する。まず、ポリイ
ミド系ペースト3を、ポッティングにより銅メッキを施
した銅合金からなるリードフレーム1のダイパット部1
aに塗布し(図1A)、その上に半導体チップ4を登載
する(図1B)。次に、ポリイミド系ペースト3で接合
されたリードフレーム1と半導体チップ4を、約10
−1〜10−2Torrの真空オーブン中において、約12
0°Cで60分間程度の加熱し、ポリイミド系ペースト
中の溶剤(例えばNーメチルピロリドン)を飛ばす。溶
剤を飛ばし終えたところで、次にポリイミド系ペースト
を完全に硬化させるため、約300°Cで約60分間加
熱する。以上の加熱工程中、銅フレームの酸化を抑制
し、かつ、硬化中のペーストから発生するアウトガスが
銅フレームやチップに付着させなようにするため、真空
オーブンは常に吸引排気を行う。
ころで、図2Aの斜視図及び図2Bの側面図に示すよう
にメッキした銅の表面に直接金線5を付け合金化させて
ワイヤーボンディングを行う。既に述べたように、ポリ
イミド系接着剤は、450°Cの高温下でも数分なら十
分耐えることができるので、この工程は、300〜45
0°H2、5〜10%、残りがN2のフォーミングガス
中において銅の酸化を防止しながらを行う。因に、銀ペ
ーストは300°C程度で熱分解してしまうため、この
ワイヤーボンディング工程の実施は不可能であり、使用
することはできない。このように、ポリイミド系接着剤
はAuーSiと比べ、弾性率が約1/20であることか
ら、リードフレームと半導体チップとの熱膨張係数差が
大きく異なっていてもチップクラックは発生することは
なく、また、ポリイミド系接着剤3は450°Cの高温
下での還元にも耐えることができるため、それを用いる
ことにより銅メッキした銅合金からなるリードフレーム
に対しワイヤー(金線)5を取り付けることができる。
このようにして作製された半導体装置のリードフレーム
1、半導体チップ4、金線5、インナーリード2の一部
を例えば図3に示す従来のものと同様にパッケージライ
ンに沿って樹脂封止してパッケージを作製することが出
来る。
系接着剤を用いたため、銀メッキを施していない、つま
り銅メッキを施した銅合金のリードフレームを用い、鉄
合金リードフレーム品以上の信頼性を有した半導体装置
を容易に得ることができる。 請求項2乃至5に対応する効果: 銅の酸化を防止する
ことができるため、銀メッキを施していないリードフレ
ーム、つまり銅合金リードフレームに銅メッキを施した
リードフレームを用いて半導体チップのパッケージング
を行うことによって半導体装置を製造することができ
る。
めの図である。
その斜視図でありかつ、図2Bはその側面図である。
る。
説明するための図である。
ーリード部、3…ペースト(ポリイミド系接着剤)、4
…半導体チップ、5…ワイヤー(金線)、6…電極パッ
ト
Claims (4)
- 【請求項1】 銅合金に銅メッキを行ったリードフレ
ーム上に、ポリイミド系の接着剤を用いて半導体チップ
を接合し、 金又は銅を主成分としたワイヤーを用いて半導体チップ
の電極とリードフレームの各端子を接続し、半導体チッ
プとワイヤー、リードフレームのワイヤーとの接合部を
樹脂封止したことを特徴とする半導体装置。 - 【請求項2】 ポリイミド系ペーストを銅合金に銅メッ
キを行ったリードフレーム上に塗布して半導体チップを
登載し、排気により真空雰囲気を維持しつつ加熱して前
記ポリイミド系ペーストを硬化し、次に、還元雰囲気中
で半導体チップの電極とリードフレームの各端子のワイ
ヤーボンディングを行うことを特徴とする半導体装置の
製造方法。 - 【請求項3】 ポリイミド系ペーストを銅合金に銅メッ
キを行ったリードフレーム上に塗布して半導体チップを
登載し、排気により10−1〜10−2Torr程度の真空
雰囲気を維持しつつ約300°C、約60分間 加熱し
て前記ポリイミド系ペーストを硬化し、次に、約300
〜450°Cのフォーミングガス中で還元しつつ半導体
チップの電極とリードフレームの各端子のワイヤーボン
ディングを行うことを特徴とする半導体装置の製造方
法。 - 【請求項4】 請求項3に記載された半導体装置の製造
方法において、前記フォーミングガスは、H2がおおむ
ね5〜10%、残りがN2から成るものであることを特
徴とする半導体装置の製造方法。
Priority Applications (2)
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---|---|---|---|
JP23696599A JP3804747B2 (ja) | 1999-08-24 | 1999-08-24 | 半導体装置の製造方法 |
US09/644,572 US6404066B1 (en) | 1999-08-24 | 2000-08-24 | Semiconductor device and process for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23696599A JP3804747B2 (ja) | 1999-08-24 | 1999-08-24 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001068486A true JP2001068486A (ja) | 2001-03-16 |
JP3804747B2 JP3804747B2 (ja) | 2006-08-02 |
Family
ID=17008400
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Application Number | Title | Priority Date | Filing Date |
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JP23696599A Expired - Fee Related JP3804747B2 (ja) | 1999-08-24 | 1999-08-24 | 半導体装置の製造方法 |
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Country | Link |
---|---|
US (1) | US6404066B1 (ja) |
JP (1) | JP3804747B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008277653A (ja) * | 2007-05-02 | 2008-11-13 | Morioka Seiko Instruments Inc | 半導体製造方法 |
JP2009043940A (ja) * | 2007-08-09 | 2009-02-26 | Morioka Seiko Instruments Inc | 半導体製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7023313B2 (en) * | 2003-07-16 | 2006-04-04 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US7307502B2 (en) * | 2003-07-16 | 2007-12-11 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US7489219B2 (en) * | 2003-07-16 | 2009-02-10 | Marvell World Trade Ltd. | Power inductor with reduced DC current saturation |
US8324872B2 (en) * | 2004-03-26 | 2012-12-04 | Marvell World Trade, Ltd. | Voltage regulator with coupled inductors having high coefficient of coupling |
US7741703B2 (en) * | 2006-10-06 | 2010-06-22 | Vishay General Semiconductor Llc | Electronic device and lead frame |
US9070392B1 (en) | 2014-12-16 | 2015-06-30 | Hutchinson Technology Incorporated | Piezoelectric disk drive suspension motors having plated stiffeners |
JP6689294B2 (ja) | 2015-06-30 | 2020-04-28 | ハッチンソン テクノロジー インコーポレイテッドHutchinson Technology Incorporated | 金誘電体接合部の信頼性を向上させたディスクドライブヘッドサスペンション構造 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4942454A (en) * | 1987-08-05 | 1990-07-17 | Mitsubishi Denki Kabushiki Kaisha | Resin sealed semiconductor device |
JPH0286157A (ja) * | 1988-09-22 | 1990-03-27 | Hitachi Ltd | 半導体装置 |
JPH04162556A (ja) * | 1990-10-25 | 1992-06-08 | Mitsubishi Electric Corp | リードフレーム及びその製造方法 |
US5859471A (en) * | 1992-11-17 | 1999-01-12 | Shinko Electric Industries Co., Ltd. | Semiconductor device having tab tape lead frame with reinforced outer leads |
JP2989406B2 (ja) * | 1993-01-29 | 1999-12-13 | シャープ株式会社 | 半導体装置用プリプレーテッドフレーム及びその製造方法 |
KR100266726B1 (ko) * | 1995-09-29 | 2000-09-15 | 기타지마 요시토시 | 리드프레임과 이 리드프레임을 갖춘 반도체장치 |
JP3937265B2 (ja) * | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | 半導体装置 |
US6310390B1 (en) * | 1999-04-08 | 2001-10-30 | Micron Technology, Inc. | BGA package and method of fabrication |
US6303981B1 (en) * | 1999-09-01 | 2001-10-16 | Micron Technology, Inc. | Semiconductor package having stacked dice and leadframes and method of fabrication |
-
1999
- 1999-08-24 JP JP23696599A patent/JP3804747B2/ja not_active Expired - Fee Related
-
2000
- 2000-08-24 US US09/644,572 patent/US6404066B1/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008277653A (ja) * | 2007-05-02 | 2008-11-13 | Morioka Seiko Instruments Inc | 半導体製造方法 |
JP2009043940A (ja) * | 2007-08-09 | 2009-02-26 | Morioka Seiko Instruments Inc | 半導体製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US6404066B1 (en) | 2002-06-11 |
JP3804747B2 (ja) | 2006-08-02 |
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