JP2001060654A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2001060654A JP2001060654A JP11234577A JP23457799A JP2001060654A JP 2001060654 A JP2001060654 A JP 2001060654A JP 11234577 A JP11234577 A JP 11234577A JP 23457799 A JP23457799 A JP 23457799A JP 2001060654 A JP2001060654 A JP 2001060654A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor chip
- hole
- electrode portion
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の半導体チッ
プを有するいわゆるマルチチップパッケージ（ＭＣＰ）
に係り、特に複数の半導体チップを積層したスタックド
ＭＣＰ半導体装置およびその製造方法に関する。The present invention relates to a so-called multi-chip package (MCP) having a plurality of semiconductor chips.
More particularly, the present invention relates to a stacked MCP semiconductor device in which a plurality of semiconductor chips are stacked and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、電子機器の高性能化、小型化に伴
って１つのパッケージ内に複数の半導体チップを配置し
てマルチチップパッケージとすることにより、半導体装
置の高機能化と小型化とが図られている。そして、マル
チチップパッケージには、複数の半導体チップを平面的
に並べたものと、複数の半導体チップを厚み方向に積層
したものとがある。半導体チップを平面的に並べたマル
チチップパッケージは、広い実装面積を必要とするた
め、電子機器の小型化への寄与が小さい。このため、半
導体チップを積層したスタックドＭＣＰの開発が盛んに
行われている。2. Description of the Related Art In recent years, with the increase in performance and miniaturization of electronic devices, a plurality of semiconductor chips are arranged in a single package to form a multi-chip package. Is planned. The multi-chip package includes a package in which a plurality of semiconductor chips are arranged in a plane and a package in which a plurality of semiconductor chips are stacked in a thickness direction. A multi-chip package in which semiconductor chips are arranged in a plane requires a large mounting area, so that the contribution to miniaturization of electronic devices is small. For this reason, a stacked MCP in which semiconductor chips are stacked has been actively developed.
【０００３】[0003]
【発明が解決しようとする課題】従来のスタックドＭＣ
Ｐは、例えば特開平６−３７２５０号公報に記載されて
いるように、積層した半導体チップを相互に電気的に接
続する場合、各半導体チップの周縁部に端子部を形成
し、各チップの端子間をワイヤによって接続している。
このため、半導体チップ相互の電気的接続が煩雑となる
ばかりでなく、積層する半導体チップは、上にいくほど
サイズを小さくしなければならず、集積効率、実装効率
が低下する。また、半導体チップの集積度が向上する
と、ワイヤ間の間隔が小さくなってワイヤ間で短絡を生
ずるおそれがある。さらに、従来のスタックドＭＣＰに
おいては、積層した半導体チップを接着剤によって相互
に接合するようにしており、接着剤の塗布などを必要と
して工程が煩雑となる。SUMMARY OF THE INVENTION Conventional stacked MC
P is, for example, as described in JP-A-6-37250, when the stacked semiconductor chips are electrically connected to each other, a terminal portion is formed on a peripheral portion of each semiconductor chip, and a terminal of each chip is formed. They are connected by wires.
For this reason, the electrical connection between the semiconductor chips is not only complicated, but also the semiconductor chips to be stacked must be reduced in size as they go up, and the integration efficiency and the mounting efficiency decrease. Further, when the degree of integration of the semiconductor chip is improved, the distance between the wires is reduced, and there is a possibility that a short circuit occurs between the wires. Further, in the conventional stacked MCP, the stacked semiconductor chips are bonded to each other by an adhesive, and the application of the adhesive or the like is required, so that the process becomes complicated.
【０００４】本発明は、前記従来技術の欠点を解消する
ためになされたもので、ワイヤを用いずに積層した半導
体チップを相互に電気的に接続することを目的としてい
る。The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to electrically connect stacked semiconductor chips without using wires.
【０００５】また、本発明は、接着剤を用いずに積層し
た半導体チップを相互に接合することを目的としてい
る。It is another object of the present invention to bond semiconductor chips stacked together without using an adhesive.
【０００６】[0006]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明に係る第１の半導体装置は、素子が形成さ
れた半導体チップを複数積層してある半導体装置におい
て、前記各半導体チップの電極部と対応した部分の半導
体基板を貫通して形成した穴に充填した導電材により、
前記各半導体チップを相互に接合したことを特徴として
いる。In order to achieve the above object, a first semiconductor device according to the present invention is a semiconductor device comprising a plurality of stacked semiconductor chips on which elements are formed. The conductive material filled in the hole formed through the semiconductor substrate in the part corresponding to the electrode part of
The semiconductor chips are joined to each other.
【０００７】このように構成した本発明の第１に係る半
導体装置は、電極部を残して半導体基板に貫通穴を形成
し、この貫通穴に充填した導電材によって各半導体チッ
プの電極部を接合することにより、ワイヤを用いずに各
半導体チップを電気的に接続することができ、また各半
導体チップを相互に接合することができる。In the semiconductor device according to the first aspect of the present invention configured as described above, a through hole is formed in the semiconductor substrate except for the electrode portion, and the electrode portion of each semiconductor chip is joined by the conductive material filled in the through hole. By doing so, the respective semiconductor chips can be electrically connected without using wires, and the respective semiconductor chips can be joined to each other.
【０００８】導電材として半田または低融点金属を用い
ると、接合による電気抵抗を小さくすることができると
ともに、大きな接合力が得られる。また、導電材として
導電性接着剤を用いると、加熱を必要としないために工
程の簡略化が図れ、素子などの熱によるダメージなどを
避けることができる。[0008] When solder or low melting point metal is used as the conductive material, the electrical resistance due to bonding can be reduced and a large bonding force can be obtained. In addition, when a conductive adhesive is used as the conductive material, heating is not required, so that the process can be simplified and damage to the element and the like due to heat can be avoided.
【０００９】そして、本発明の第２に係る半導体装置
は、素子が形成された半導体チップを複数積層した半導
体装置において、前記各半導体チップは電極部を対応さ
せて積層してあり、これらの電極部が電極部と半導体基
板とを貫通して設けた貫通穴内に配置した導電材によ
り、電気的に相互に接続してあることを特徴としてい
る。A semiconductor device according to a second aspect of the present invention is a semiconductor device in which a plurality of semiconductor chips on which elements are formed are stacked, wherein each of the semiconductor chips is stacked so as to correspond to an electrode portion. The portions are electrically connected to each other by a conductive material disposed in a through hole provided through the electrode portion and the semiconductor substrate.
【００１０】このように構成した本発明の第２に係る半
導体装置においても、ワイヤを用いずに各半導体チップ
を電気的に接続することができる。また、電極部と半導
体基板とを貫通した貫通穴を形成しているため、各半導
体チップを積層した状態で一括して貫通穴を形成するこ
とが可能で、工程の簡素化を図ることができる。[0010] In the semiconductor device according to the second aspect of the present invention thus configured, each semiconductor chip can be electrically connected without using wires. In addition, since the through-hole penetrating the electrode portion and the semiconductor substrate is formed, the through-hole can be formed collectively in a state where the semiconductor chips are stacked, and the process can be simplified. .
【００１１】導電材は、貫通穴の壁面に形成した導電性
膜であってよい。この導電性膜は、銅やアルミニウムな
どの導電性金属の膜を蒸着やメッキによって堆積するこ
とにより形成することができる。さらに、導電材として
導電性接着剤を用い、この導電性接着剤を貫通穴に充填
して硬化させることにより、各半導体チップを相互に接
合することができる。そして、導電性接着剤を、下方に
位置する半導体チップの電極部上の保護膜が除去されて
形成された空隙に充填することにより、各半導体チップ
の電極部と導電性接着剤との接触面積が増大して電気的
接続をより確実にすることができるとともに、各半導体
チップ間の接合力を大きくすることができる。[0011] The conductive material may be a conductive film formed on the wall surface of the through hole. This conductive film can be formed by depositing a film of a conductive metal such as copper or aluminum by vapor deposition or plating. Further, by using a conductive adhesive as a conductive material and filling the through-hole with the conductive adhesive and curing the same, the respective semiconductor chips can be joined to each other. Then, by filling the gap formed by removing the protective film on the electrode portion of the semiconductor chip located below, the conductive adhesive is applied to the contact area between the electrode portion of each semiconductor chip and the conductive adhesive. And the electrical connection can be further ensured, and the joining force between the semiconductor chips can be increased.
【００１２】また、本発明の第３に係る半導体装置は、
素子が形成された半導体チップの複数を積層した半導体
装置において、前記各半導体チップは、電極部を対応さ
せて積層してあり、上方に位置する前記半導体チップ
は、前記電極部に対応した部分の半導体基板に形成した
貫通穴と、前記電極部を貫通して形成したバンプとを有
し、下方に位置する前記半導体チップは、前記電極部が
前記バンプを介して上方に位置する前記半導体チップの
前記電極部に電気的に接続してある、ことを特徴として
いる。Further, a semiconductor device according to a third aspect of the present invention includes:
In a semiconductor device in which a plurality of semiconductor chips on which elements are formed are stacked, each of the semiconductor chips is stacked so as to correspond to an electrode portion, and the semiconductor chip positioned above is a portion corresponding to the electrode portion. A semiconductor chip having a through-hole formed in a semiconductor substrate and a bump formed through the electrode portion, wherein the semiconductor chip located below the semiconductor chip has the electrode portion located upward via the bump; It is characterized by being electrically connected to the electrode part.
【００１３】このように構成した本発明においてもワイ
ヤを用いることなく各半導体チップを電気的に接続する
ことができる。そして、下方に位置する半導体チップの
電極部と上方に位置する半導体チップのバンプとを、導
電性接着剤により接合すると、電気的な接続がより確実
に行えるとともに、各半導体チップを相互に接合するこ
とができる。In the present invention thus configured, each semiconductor chip can be electrically connected without using wires. Then, when the electrode portion of the semiconductor chip located below and the bump of the semiconductor chip located above are joined with a conductive adhesive, electrical connection can be performed more reliably and the respective semiconductor chips are joined to each other. be able to.
【００１４】上記の半導体装置を製造する方法の第１
は、素子を形成した半導体チップの電極部と対応した部
分の半導体基板に貫通穴を形成する工程と、前記貫通穴
を覆って導電材の盛上げ部を形成する工程と、前記導電
材を配置した前記半導体チップの複数を積層して前記電
極部を相互に電気的に接続するとともに、前記各半導体
チップを相互に接合する工程と、を有することを特徴と
している。これにより、本発明の第１に係る半導体装置
が得られ、半導体チップ間をワイヤボンディングするこ
となく相互に電気的に接続することができるとともに、
積層した半導体チップ同士を接合することができる。The first of the methods for manufacturing the above semiconductor device
Forming a through hole in a portion of the semiconductor substrate corresponding to an electrode portion of a semiconductor chip on which an element is formed, forming a raised portion of a conductive material over the through hole, and disposing the conductive material. And laminating a plurality of the semiconductor chips to electrically connect the electrode portions to each other and bonding the semiconductor chips to each other. Thereby, the semiconductor device according to the first aspect of the present invention is obtained, and the semiconductor chips can be electrically connected to each other without wire bonding.
The stacked semiconductor chips can be joined together.
【００１５】導電材は、半田ペーストであってよい。こ
の場合、盛上げ部は、貫通穴を覆って穴の容積より多く
の半田ペーストを配置する工程と、半田ペーストを配置
した半導体チップを加熱して半田ペーストを溶融し、半
田ペースト中のフラックスを除去する工程とにより形成
し、接合は、積層した複数の半導体チップを加熱して貫
通穴に配置された半田を溶融して行うことができる。す
なわち、半田ペーストを用いれば、半導体チップを積層
して半田を加熱、リフローすることにより、半導体チッ
プの自重によって半田が融けたときに自動的に各半導体
チップの接合が行える。また、導電材として低融点金属
を用いた場合、接合は、積層した複数の半導体チップの
低融点金属を加熱、加圧して行うと、電極部間の接合、
半導体チップ間の接合を確実に行える。そして、錫や銀
などの低融点金属を用いることにより鉛フリーを実現す
ることが可能となる。[0015] The conductive material may be a solder paste. In this case, the raised portion covers the through hole and arranges more solder paste than the volume of the hole, and the semiconductor chip on which the solder paste is arranged is heated to melt the solder paste and remove the flux in the solder paste. The bonding can be performed by heating the stacked semiconductor chips and melting the solder arranged in the through holes. That is, when the solder paste is used, the semiconductor chips are stacked, and the solder is heated and reflowed, so that when the solder is melted by its own weight, the semiconductor chips can be automatically joined. When a low-melting-point metal is used as the conductive material, bonding is performed by heating and pressing the low-melting-point metal of a plurality of stacked semiconductor chips.
Bonding between semiconductor chips can be reliably performed. And, by using a low melting point metal such as tin or silver, it becomes possible to realize lead-free.
【００１６】本発明に係る第２の半導体装置の製造方法
は、素子を形成した半導体ウエハまたは半導体チップの
複数を、予め定めた電極部を対応させて積層する工程
と、積層した前記半導体ウエハまたは半導体チップの前
記電極部と半導体基板とを貫通した貫通穴を形成する工
程と、前記貫通穴内に導電材を設けて前記電極部を相互
に電気的に接続する工程と、を有することを特徴として
いる。これにより、本発明の第２に係る半導体装置を得
ることができる。A second method of manufacturing a semiconductor device according to the present invention comprises the steps of: laminating a plurality of semiconductor wafers or semiconductor chips having elements formed thereon in correspondence with predetermined electrode portions; Forming a through-hole penetrating the electrode portion and the semiconductor substrate of the semiconductor chip; and providing a conductive material in the through-hole to electrically connect the electrode portions to each other. I have. Thereby, the semiconductor device according to the second aspect of the present invention can be obtained.
【００１７】電極部の電気的接続は、貫通穴の壁面に蒸
着またはメッキにより金属膜を形成して行うことができ
る。また、各半導体ウエハまたは半導体チップは、電極
部の上に形成してある保護膜の一部が除去され、電極部
の少なくとも一部が露出させてある場合、各電極部の電
気的接続は貫通穴と保護膜を除去して形成された空隙と
に導電性接着剤を注入して行う。これにより、電極部と
導電性接着剤との接触面積が大きくなって電気的接続を
確実にでき、各半導体チップ間の接合強度を増大するこ
とができる。The electrical connection of the electrode portion can be made by forming a metal film on the wall surface of the through hole by vapor deposition or plating. Further, in each semiconductor wafer or semiconductor chip, when a part of the protective film formed on the electrode part is removed and at least a part of the electrode part is exposed, the electrical connection of each electrode part is made through. This is performed by injecting a conductive adhesive into the hole and the gap formed by removing the protective film. Thereby, the contact area between the electrode portion and the conductive adhesive is increased, electrical connection can be ensured, and the bonding strength between the semiconductor chips can be increased.
【００１８】本発明の第３に係る半導体装置の製造方法
は、第１の半導体チップの電極部と、この電極部に対応
した半導体基板とを貫通した貫通穴を形成する工程と、
前記電極部に形成した貫通穴を介して電極部を貫通した
バンプを形成する工程と、前記第１の半導体チップの非
能動面側に第２の半導体チップを重ねて配置し、前記バ
ンプを介して前記第２の半導体チップの電極部を前記第
１の半導体チップの前記電極部に電気的に接続する工程
と、を有することを特徴としている。これにより、本発
明の第３に係る半導体装置を得ることができる。In a third aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: forming a through hole penetrating an electrode portion of a first semiconductor chip and a semiconductor substrate corresponding to the electrode portion;
Forming a bump penetrating the electrode portion through a through hole formed in the electrode portion, and arranging a second semiconductor chip on the non-active surface side of the first semiconductor chip so as to overlap the second semiconductor chip; Electrically connecting the electrode portion of the second semiconductor chip to the electrode portion of the first semiconductor chip. Thereby, the semiconductor device according to the third aspect of the present invention can be obtained.
【００１９】そして、第１の半導体チップと第２の半導
体チップとの電極部を電気的に接続する工程を、第１の
半導体チップの半導体基板に形成した貫通穴内、または
第２の半導体チップの電極部上に導電性接着剤を配置す
る工程と、第１の半導体チップの非能動面側に第２の半
導体装置を配置して重ね、第２の半導体チップの電極部
とバンプとを導電性接着剤によって接合する工程と、に
よって行うことにより、電気的接続の確実性を向上する
ことができ、また半導体チップ同士の接合が可能とな
る。The step of electrically connecting the electrode portions of the first semiconductor chip and the second semiconductor chip is performed in a through-hole formed in the semiconductor substrate of the first semiconductor chip or in the second semiconductor chip. Arranging a conductive adhesive on the electrode portion, and arranging and overlaying a second semiconductor device on the non-active surface side of the first semiconductor chip, and electrically connecting the electrode portion and the bump of the second semiconductor chip to each other; By performing the bonding with the adhesive, the reliability of the electrical connection can be improved, and the bonding between the semiconductor chips can be performed.
【００２０】[0020]
【発明の実施の形態】本発明に係る半導体装置およびそ
の製造方法の好ましい実施の形態を、添付図面にしたが
って詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
【００２１】図１は、本発明の第１実施の形態に係る半
導体装置の一部断面図である。図１において、スタック
ド型ＭＣＰを構成する半導体装置１０は、複数（実施形
態の場合４つ）の半導体チップ１２（１２ａ〜１２ｄ）
が積層してある。そして、各半導体チップ１２は、シリ
コンからなる半導体基板１４を有し、半導体基板１４の
上部に図示しないトランジスタや抵抗、コンデンサなど
の素子が形成してあるとともに、電極部１６が設けてあ
る。これらの電極部１６は、例えばアルミニウムやアル
ミニウム合金などの導電材によって形成してあって、半
導体基板１４に形成した配線（図示せず）を介してトラ
ンジスタなどの素子に電気的に接続してある。FIG. 1 is a partial sectional view of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, a plurality of (four in the case of the embodiments) semiconductor chips 12 (12a to 12d) of a semiconductor device 10 forming a stacked type MCP are provided.
Are laminated. Each semiconductor chip 12 has a semiconductor substrate 14 made of silicon. On the semiconductor substrate 14, elements such as transistors, resistors, and capacitors (not shown) are formed, and an electrode portion 16 is provided. These electrode portions 16 are formed of, for example, a conductive material such as aluminum or an aluminum alloy, and are electrically connected to elements such as transistors via wiring (not shown) formed on the semiconductor substrate 14. .
【００２２】各半導体チップ１２は、予め定めた電極部
１６ａ、１６ｂを対応させて積層してあって、隣接した
半導体チップ１２の対応させた電極部１６ａ、１６ｂが
導電材である半田１８によって電気的に相互に接続して
ある。Each of the semiconductor chips 12 has a predetermined electrode section 16a, 16b correspondingly laminated thereon, and the corresponding electrode sections 16a, 16b of the adjacent semiconductor chip 12 are electrically connected by solder 18 which is a conductive material. Are interconnected.
【００２３】すなわち、最下段の半導体チップ１２ｄを
除いた他の半導体チップ１２ａ〜１２ｃには、半導体基
板１４の電極部１６ａ、１６ｂと対応した部分に、半導
体基板１４を貫通して形成した接続穴（貫通穴）２０が
設けてある。これらの接続穴２０は、半導体チップ１２
の能動面側である電極部１６を設けた側から非能動面側
（図１の下面側）に向けて漸次拡開している。そして、
半導体基板１４の非能動面と接続穴２０の壁面とには、
例えば二酸化シリコン（ＳｉＯ2 ）からなる絶縁膜２２
が設けてあって、接続穴２０内に配置した半田１８と半
導体基板１４とが直接電気的に導通しないようにしてあ
る。さらに、図の上側に位置する半導体チップ１２の接
続穴２０内に配置した半田１８は、電極部１６の下面と
接合しているとともに、半導体基板１４の非能動面から
突出し、非能動面側に隣接している下側半導体チップ１
２の電極部１６の上面と接合している。That is, in the other semiconductor chips 12a to 12c except for the lowermost semiconductor chip 12d, connection holes formed through the semiconductor substrate 14 at portions corresponding to the electrode portions 16a and 16b of the semiconductor substrate 14. (Through hole) 20 is provided. These connection holes 20 are provided in the semiconductor chip 12.
Are gradually expanded from the side on which the electrode portion 16 is provided, which is the active surface side, to the non-active surface side (the lower surface side in FIG. 1). And
The non-active surface of the semiconductor substrate 14 and the wall surface of the connection hole 20 have
For example, an insulating film 22 made of silicon dioxide (SiO 2 )
Is provided to prevent direct electrical conduction between the solder 18 disposed in the connection hole 20 and the semiconductor substrate 14. Further, the solder 18 disposed in the connection hole 20 of the semiconductor chip 12 located on the upper side of the figure is joined to the lower surface of the electrode portion 16 and protrudes from the non-active surface of the semiconductor substrate 14, and is Adjacent lower semiconductor chip 1
It is joined to the upper surface of the second electrode section 16.
【００２４】このように形成した第１実施形態に係る半
導体装置１０は、各半導体チップ１２ａ〜１２ｄの対応
させた電極部１６ａ、１６ｂが半導体基板１４に形成し
た接続孔２０に設けた半田１８によって直接電気的に接
続されているため、各半導体チップ１２を電気的に接続
するためのワイヤを必要とせず、半導体チップ１２相互
の電気的接続を容易に行うことができる。しかも、変形
しやすいワイヤを用いないために電極部１６間の間隔を
小さくしても短絡などの発生をなくすことができ、各半
導体チップ１２の素子の集積度を向上することが可能と
なる。また、積層した各半導体チップ１２の周縁部に端
子部を形成する必要がないため、半導体チップ１２の積
層数を多くしても上方に位置する半導体チップのサイズ
を小さくする必要がなく、実装効率を高めることができ
る。In the semiconductor device 10 according to the first embodiment thus formed, the corresponding electrode portions 16a and 16b of the semiconductor chips 12a to 12d are formed by the solder 18 provided in the connection holes 20 formed in the semiconductor substrate 14. Since the semiconductor chips 12 are directly electrically connected, wires for electrically connecting the semiconductor chips 12 are not required, and electrical connection between the semiconductor chips 12 can be easily performed. In addition, since a wire that is easily deformed is not used, even if the interval between the electrode portions 16 is reduced, occurrence of a short circuit or the like can be eliminated, and the degree of integration of elements of each semiconductor chip 12 can be improved. Further, since it is not necessary to form a terminal portion on the peripheral portion of each stacked semiconductor chip 12, even if the number of stacked semiconductor chips 12 is increased, it is not necessary to reduce the size of the semiconductor chip located above, and the mounting efficiency is reduced. Can be increased.
【００２５】さらに、半導体装置１０は、半田１８を介
して隣接する半導体チップ１２の電極部１６を接合した
ことにより、接着剤によって半導体チップを相互に接合
する工程を省略することができる。そして、実施の形態
においては、半導体チップ１２に形成した接続穴２０が
他の半導体チップを接合する非能動面側に向けて漸次拡
開してあるため、半田１８と他の半導体チップの電極部
１６（例えば、半導体チップ１２ａの半田１８と半導体
チップ１２ｂの電極部１６）との接合力を大きくするこ
とができる。Further, in the semiconductor device 10, since the electrode portions 16 of the adjacent semiconductor chips 12 are joined via the solder 18, the step of joining the semiconductor chips to each other by the adhesive can be omitted. In the embodiment, since the connection hole 20 formed in the semiconductor chip 12 is gradually expanded toward the non-active surface side for joining another semiconductor chip, the solder 18 and the electrode portion of the other semiconductor chip are connected. 16 (for example, the solder 18 of the semiconductor chip 12a and the electrode portion 16 of the semiconductor chip 12b) can be increased.
【００２６】なお、半導体装置１０をパッケージの基板
に電気的に接続する場合、図１の最上段に位置する半導
体チップ１２ａの電極部１６をワイヤボンディングやフ
ェースダウンボンディングして行う。When the semiconductor device 10 is electrically connected to the package substrate, the electrode section 16 of the semiconductor chip 12a located at the top of FIG. 1 is bonded by wire bonding or face down bonding.
【００２７】前記実施の形態においては、導電材が半田
１８である場合について説明したが、導電材は錫や銀な
どのいわゆる低融点金属であってもよく、また導電性接
着剤であってもよい。In the above embodiment, the case where the conductive material is the solder 18 has been described. However, the conductive material may be a so-called low melting point metal such as tin or silver, or may be a conductive adhesive. Good.
【００２８】図２は、第１実施の形態に係る半導体装置
１０の製造方法を説明する工程図の要部を示したもので
あるまず、図２（ａ）に示したように、公知の方法によ
り半導体基板１４に図示しない素子を形成したのち、配
線を形成するとともに電極部１６を設けて半導体チップ
１２を作製する。その後、半導体チップ１２の裏面（非
能動面）側から半導体基板１４を例えばウエットエッチ
ングし、半導体基板１４を貫通して電極部１６の裏面に
達する接続穴２０を形成する。FIG. 2 shows a main part of a process chart for explaining a method of manufacturing the semiconductor device 10 according to the first embodiment. First, as shown in FIG. After forming an element (not shown) on the semiconductor substrate 14, the wiring is formed and the electrode portion 16 is provided to manufacture the semiconductor chip 12. Thereafter, the semiconductor substrate 14 is, for example, wet-etched from the back surface (non-active surface) side of the semiconductor chip 12 to form a connection hole 20 that penetrates the semiconductor substrate 14 and reaches the back surface of the electrode portion 16.
【００２９】次に、図２（ｂ）に示したように、テトラ
エトキシシラン（ＴＥＯＳ）などを用いたＣＶＤ法など
によって、半導体基板１４の非能動面と接続穴２０とを
覆って二酸化シリコン（ＳｉＯ2 ）からなる絶縁膜２２
を形成する。さらに、絶縁膜２２を覆ってフォトレジス
ト膜３０を形成し、これをフォトリソグラフィー法によ
って露光、現像してパターニングし、電極１６と対応し
た位置に穴３２を設け、電極部１６の面に形成されてい
る絶縁膜２２を露出させる。Next, as shown in FIG. 2B, the non-active surface of the semiconductor substrate 14 and the connection holes 20 are covered by silicon dioxide (CVD) using tetraethoxysilane (TEOS) or the like. Insulating film 22 made of SiO 2 )
To form Further, a photoresist film 30 is formed to cover the insulating film 22, which is exposed and developed by photolithography to be patterned, and a hole 32 is provided at a position corresponding to the electrode 16, and formed on the surface of the electrode portion 16. The exposed insulating film 22 is exposed.
【００３０】その後、フォトレジスト膜３０をマスクと
してエッチングを行い、露出させた絶縁膜２２を除去す
る（図２（ｃ）参照）。次に、スクリーン印刷法を用い
て接続穴２０内に導電材となる半田ペースト３４を設け
る。この半田ペースト３４は、後述するように、他の半
導体チップの電極部と接合するために、接続穴２０から
適宜量食み出すように設ける。その後、半田ペースト３
４を配置した半導体チップ１２をリフロー炉に入れ、半
田ペースト３４を加熱してフラックスを除去し、図２
（ｄ）に示したように半田プラグ３６にする。Thereafter, etching is performed using the photoresist film 30 as a mask to remove the exposed insulating film 22 (see FIG. 2C). Next, a solder paste 34 serving as a conductive material is provided in the connection hole 20 using a screen printing method. As will be described later, the solder paste 34 is provided so as to protrude from the connection hole 20 in an appropriate amount in order to join with the electrode portion of another semiconductor chip. Then, solder paste 3
2 is placed in a reflow furnace, and the solder paste 34 is heated to remove the flux.
The solder plug 36 is formed as shown in FIG.
【００３１】次に、図２（ｅ）に示したように、半田接
続プラグ３６を形成した所望数の半導体チップ１２を所
定の電極部１６を対応させて非能動面が上になるように
して積み重ねる。そして、複数の半導体チップ１２を積
み重ねた状態でリフロー炉に配置し、半田プラグ３６を
溶融温度まで加熱する。これにより、半田プラグ３６は
溶融し、半導体チップ１２の重みによって押しつぶされ
る。そこで、半導体チップ１２を冷却すると、隣接した
上下の半導体チップ１２の電極部１６が半田１８によっ
て相互に電気的に接続され、接合されて図１に示した半
導体装置１０を得ることができる。Next, as shown in FIG. 2E, a desired number of semiconductor chips 12 on which the solder connection plugs 36 have been formed are placed so that the non-active surface faces up with the predetermined electrode portions 16 corresponding thereto. Stack up. Then, the plurality of semiconductor chips 12 are placed in a reflow furnace in a stacked state, and the solder plug 36 is heated to a melting temperature. As a result, the solder plug 36 is melted and crushed by the weight of the semiconductor chip 12. Then, when the semiconductor chip 12 is cooled, the electrode portions 16 of the adjacent upper and lower semiconductor chips 12 are electrically connected to each other by the solder 18 and joined to obtain the semiconductor device 10 shown in FIG.
【００３２】なお、接続穴２０に配置した導電材が銀な
どの低融点金属である場合、図２（ｄ）のリフロー工程
を省略できる。そして、重ねた複数の各半導体チップを
銀などの低融点金属によって相互に接合する場合、最上
段または最下段の半導体チップ１２、もしくは両者を加
熱するとともに、積層した半導体チップの全体を上下方
向に加圧する。これにより、半導体基板１４を介して熱
を低融点金属に容易に伝達することができるとともに、
各半導体チップの電極部を確実に低融点金属と接合する
ことができる。さらに、導電材として導電性接着剤を用
いた場合には、加熱工程を省略することができる。When the conductive material disposed in the connection hole 20 is a low melting point metal such as silver, the reflow step shown in FIG. 2D can be omitted. When the plurality of stacked semiconductor chips are joined to each other by a low melting point metal such as silver, the uppermost or lowermost semiconductor chip 12 or both are heated, and the whole of the stacked semiconductor chips is vertically moved. Apply pressure. Thereby, heat can be easily transmitted to the low melting point metal through the semiconductor substrate 14, and
The electrode portion of each semiconductor chip can be reliably joined to the low melting point metal. Furthermore, when a conductive adhesive is used as the conductive material, the heating step can be omitted.
【００３３】図３は、第２実施の形態に係る半導体装置
の一部断面図である。図３（ａ）に示した半導体装置４
０は、複数（この実施形態においては３つ）の半導体チ
ップ１２（１２ａ〜１２ｃ）が積層してある。各半導体
チップ１２は、能動面側が図３の上側となるように揃え
てあって、予め定めた電極部４２を対応させて積層して
ある。そして、半導体装置４０は、各半導体チップ１２
の電極部４２と半導体基板１４とを貫通した貫通穴４４
が形成してあって、この貫通穴４４の壁面に蒸着やメッ
キなどによって形成した導電材である金属膜４６が設け
てあって、各半導体チップ１２の電極部４２が金属膜４
６を介して相互に電気的に接続してある。ただし、各半
導体チップ１２は、半導体基板１４の貫通穴４４の壁面
となる部分にシリコン酸化膜などの絶縁膜４５が形成し
てあって、金属膜４６と半導体基板１４と間が電気的に
遮断してある。FIG. 3 is a partial cross-sectional view of the semiconductor device according to the second embodiment. The semiconductor device 4 shown in FIG.
0 indicates that a plurality (three in this embodiment) of semiconductor chips 12 (12a to 12c) are stacked. Each semiconductor chip 12 is aligned so that the active surface side is on the upper side in FIG. 3, and is laminated so that predetermined electrode portions 42 correspond to each other. The semiconductor device 40 includes the respective semiconductor chips 12
Through hole 44 penetrating through electrode portion 42 of semiconductor substrate 14
A metal film 46, which is a conductive material formed by vapor deposition or plating, is provided on the wall surface of the through hole 44, and the electrode portion 42 of each semiconductor chip 12 is
6 are electrically connected to each other. However, in each semiconductor chip 12, an insulating film 45 such as a silicon oxide film is formed on a portion to be a wall surface of the through hole 44 of the semiconductor substrate 14, so that the metal film 46 and the semiconductor substrate 14 are electrically disconnected. I have.
【００３４】このように形成した半導体装置４０は、図
４のようにして製造することができる。まず、図４のス
テップ６０に示したように、半導体ウエハに通常の方法
により素子や電極部などを形成する。その後、素子など
を形成した半導体ウエハを所望枚数（この実施形態にお
いては３枚）、能動面を上にするとともに貫通穴４４を
形成する電極部４２を対応させて積層する（ステップ６
２）。次に、半導体ウエハを積層した状態で電極部４２
の部分にレーザ光などを用いて貫通穴４４を形成する
（ステップ６４）。この貫通穴４４は、エッチングによ
って形成してもよい。また、レーザ光を用いて貫通穴４
４を形成する場合、穴の壁面が荒れるので、レーザ光に
よって穴をあけたのち、エッチングして整形するとよ
い。The semiconductor device 40 formed as described above can be manufactured as shown in FIG. First, as shown in step 60 of FIG. 4, elements, electrode portions, and the like are formed on a semiconductor wafer by an ordinary method. Thereafter, a desired number (three in this embodiment) of semiconductor wafers on which elements and the like are formed are stacked with the active surface facing up and the electrode portions 42 forming the through holes 44 corresponding thereto (step 6).
2). Next, in a state where the semiconductor wafers are stacked, the electrode portions 42 are formed.
A through hole 44 is formed in a portion of the above by using a laser beam or the like (step 64). This through hole 44 may be formed by etching. In addition, the through hole 4 is formed by using a laser beam.
In the case of forming 4, since the wall surface of the hole becomes rough, it is preferable to form the hole by etching after etching the hole with a laser beam.
【００３５】その後、ステップ６６に示したように、半
導体基板１４の貫通穴４４の壁面となっている部分に絶
縁膜４５を形成する。この絶縁膜４５の形成は、例えば
貫通穴４４を形成した半導体ウエハを濃硝酸液中に浸
漬、酸化雰囲気中で加熱し、半導体基板１４の貫通穴壁
面部を酸化してＳｉＯ2 にする。その後、電極部４２に
形成されている金属酸化膜（不動態）をアルカリ等によ
って除去する。Thereafter, as shown in step 66, an insulating film 45 is formed on the portion of the semiconductor substrate 14 which is the wall surface of the through hole 44. The insulating film 45 is formed, for example, by immersing the semiconductor wafer having the through hole 44 formed therein in a concentrated nitric acid solution, heating the semiconductor wafer in an oxidizing atmosphere, and oxidizing the through hole wall surface of the semiconductor substrate 14 to SiO 2 . After that, the metal oxide film (passive) formed on the electrode portion 42 is removed with an alkali or the like.
【００３６】次に、ステップ６８に示したように、蒸着
や無電解メッキなどにより絶縁膜を形成した貫通穴４４
の壁面に金属膜４６を形成する。なお、メッキによって
金属膜４６を形成する場合、Ｔｉ（チタン）などの下地
金属を真空蒸着やＣＶＤ法によって形成し、その後に無
電解メッキによって銅などの金属膜を形成するとよい。Next, as shown in step 68, the through-hole 44 having an insulating film formed thereon by vapor deposition, electroless plating, or the like.
A metal film 46 is formed on the wall surface of. When the metal film 46 is formed by plating, it is preferable to form a base metal such as Ti (titanium) by vacuum evaporation or CVD, and then form a metal film such as copper by electroless plating.
【００３７】貫通穴４４内に金属膜４６を形成したなら
ば、ステップ７０に示したように、半導体ウエハを積層
したままレーザ光やダイヤモンドブレードなどを用いて
チップの大きさに分割する。さらに、チップの大きさに
切断した積層品をパッケージの基板に実装し、樹脂封止
などを行ってスタックド型のＭＣＰ半導体装置にする
（ステップ７２）。After the formation of the metal film 46 in the through-hole 44, as shown in step 70, the semiconductor wafer is divided into chips by using a laser beam or a diamond blade while the semiconductor wafers are stacked. Further, the laminated product cut into the size of the chip is mounted on a substrate of a package, and sealed with a resin or the like to obtain a stacked MCP semiconductor device (step 72).
【００３８】なお、前記実施形態においては、半導体ウ
エハを積層して貫通穴４４を形成した場合について説明
したが、素子と電極部４２などを形成した半導体ウエハ
を切断して半導体チップ１２を形成したのち、所望数の
半導体チップを積層して貫通穴４４を形成するようにし
てもよい。In the above-described embodiment, the case where the through holes 44 are formed by laminating the semiconductor wafers has been described. However, the semiconductor chips 12 are formed by cutting the semiconductor wafer on which the elements and the electrode portions 42 are formed. Thereafter, a desired number of semiconductor chips may be stacked to form the through-hole 44.
【００３９】図３（ｂ）は、第２実施形態の変形例の一
部断面図である。この半導体装置５０は、２つの半導体
チップ１２ａ、１２ｂが非能動面側を合せて積層してあ
る。そして、各半導体チップ１２の対応させた電極部４
２と半導体基板１４とを貫通した貫通穴４４が設けら
れ、この貫通穴４４の壁面に金属膜４６が形成してあ
り、各半導体チップ１２の電極部４２が金属膜４６によ
って電気的に接続してある。FIG. 3B is a partial sectional view of a modification of the second embodiment. In this semiconductor device 50, two semiconductor chips 12a and 12b are stacked with the non-active surface side together. Then, the corresponding electrode portion 4 of each semiconductor chip 12
2 and the semiconductor substrate 14 are provided, and a metal film 46 is formed on the wall surface of the through hole 44, and the electrode portions 42 of each semiconductor chip 12 are electrically connected by the metal film 46. It is.
【００４０】なお、半導体基板１４の貫通穴４４の壁面
が絶縁膜４５によって絶縁してあることは前記と同様で
ある。また、この半導体装置５０は、半導体装置４０の
場合とほぼ同様にして製造することができる。また、図
３（ｂ）に示した半導体装置５０は、半導体チップ１２
を２つ重ねた場合について説明したが、半導体チップ１
２ａ、１２ｂの間に任意の数の半導体チップを積層する
ことができる。It is to be noted that the wall surface of the through hole 44 of the semiconductor substrate 14 is insulated by the insulating film 45 in the same manner as described above. The semiconductor device 50 can be manufactured in substantially the same manner as the semiconductor device 40. The semiconductor device 50 shown in FIG.
Has been described, but the semiconductor chip 1
Any number of semiconductor chips can be stacked between 2a and 12b.
【００４１】図５は、第３実施の形態に係る半導体装置
の一部断面図である。図５（ａ）に示した半導体装置７
４は、複数（実施形態の場合３つ）の半導体チップ７６
（７６ａ〜７６ｃ）が積層してある。そして、各半導体
チップ７６に形成した電極部７８と半導体基板８０とを
貫通して貫通穴８２が形成してあり、この貫通穴８２に
導電材である導電性接着剤８４が充填してあって、各半
導体チップ７６が導電性接着剤８４により接合されてい
一体化してある。また、導電性接着剤８４は、図の下方
に位置する半導体チップ７６ｂ、７６ｃの、シリコン酸
化膜などからなる保護膜としてのパッシベーション膜８
６を剥離して形成された空隙８８にも充填されている。FIG. 5 is a partial sectional view of a semiconductor device according to the third embodiment. Semiconductor device 7 shown in FIG.
4 denotes a plurality (three in the case of the embodiment) of semiconductor chips 76
(76a to 76c) are stacked. A through hole 82 is formed through the electrode portion 78 formed on each semiconductor chip 76 and the semiconductor substrate 80, and the through hole 82 is filled with a conductive adhesive 84 as a conductive material. The semiconductor chips 76 are joined by a conductive adhesive 84 to be integrated. In addition, the conductive adhesive 84 is used to passivate the passivation film 8 as a protective film made of a silicon oxide film or the like on the semiconductor chips 76b and 76c located below the figure.
The gaps 88 formed by peeling 6 are also filled.
【００４２】すなわち、半導体チップは、一般に配線や
電極部を形成したのち、その上にパッシベーション膜８
６を形成して配線などを保護している。そして、電極部
７８の上に位置するパッシベーション膜８６は、他の半
導体チップやパッケージ基板の電極部などと電気的に接
続するために除去される。このため、半導体チップを複
数積層すると、パッシベーション膜８６を除去したとこ
ろが空隙８８となるので、その空隙８６に導電性接着剤
８４を充填して各電極部７８の電気的接続を行うことに
より、導電性接着剤８４と電極部７８との接触面積を増
大させてより確実な電気的接続を行い、また各半導体チ
ップ間の接合力を大きくする。That is, a semiconductor chip is generally formed with wirings and electrodes, and then a passivation film 8 is formed thereon.
6 is formed to protect the wiring and the like. Then, the passivation film 86 located on the electrode portion 78 is removed so as to be electrically connected to another semiconductor chip or an electrode portion of a package substrate. Therefore, when a plurality of semiconductor chips are stacked, the space 88 is formed by removing the passivation film 86, and the space 86 is filled with a conductive adhesive 84 to electrically connect the respective electrode portions 78. The contact area between the conductive adhesive 84 and the electrode portion 78 is increased to perform more reliable electrical connection, and the bonding force between the semiconductor chips is increased.
【００４３】この半導体装置７４は、次のごとくして製
造する。まず、素子や電極部７８などを形成した半導体
ウエハまたは半導体チップ７６の電極部７８の上に存在
するパッシベーション膜８６をエッチングなどによって
除去し、電極部７８を露出させる。次に、電極部７８を
露出させた半導体ウエハまたは半導体チップを、電極部
７８を対応させて複数積層する。その後、半導体ウエハ
または半導体チップ７６を積層した状態において、各半
導体チップ７６の電極部７８と半導体基板８０とを貫通
した貫通穴８２を一括して形成し、半導体基板８０の貫
通孔８２の壁面に図示しない絶縁膜を設ける。この絶縁
膜は、前記第２実施の形態と同様にして形成することが
できるが、次のようにして形成してもよい。The semiconductor device 74 is manufactured as follows. First, the passivation film 86 existing on the electrode portion 78 of the semiconductor wafer or the semiconductor chip 76 on which the elements and the electrode portions 78 are formed is removed by etching or the like to expose the electrode portions 78. Next, a plurality of semiconductor wafers or semiconductor chips with the electrode portions 78 exposed are stacked in correspondence with the electrode portions 78. Thereafter, in a state where the semiconductor wafers or the semiconductor chips 76 are stacked, through holes 82 penetrating the electrode portions 78 of the respective semiconductor chips 76 and the semiconductor substrate 80 are collectively formed, and are formed on the wall surfaces of the through holes 82 of the semiconductor substrate 80. An insulating film (not shown) is provided. This insulating film can be formed in the same manner as in the second embodiment, but may be formed as follows.
【００４４】積層した状態で貫通穴８２を形成した半導
体ウエハまたは半導体チップ７６をそのままＣＶＤ装置
に入れ、ＴＥＯＳなどを用いてＣＶＤ法によってシリコ
ン酸化膜を貫通穴８２の壁面に形成する。このとき、図
６（ａ）に示したように、シリコン酸化膜８９は、一番
上の半導体ウエハまたは半導体チップ７６ａの上面と、
各半導体ウエハまたは半導体チップ７６ａ〜７６ｃの貫
通孔８２の壁面に堆積され、各半導体ウエハまたは各半
導体チップ７６間に形成される空隙８８を形成している
面にはほとんど形成されない。これは、パッシベーショ
ン膜８６が薄いために空隙８８の上下方向の幅が狭く、
しかも周囲が密閉状体となっているために原料ガスが空
隙８８の奥まで供給されないためである。The semiconductor wafer or semiconductor chip 76 having the through-hole 82 formed in the stacked state is put into a CVD apparatus as it is, and a silicon oxide film is formed on the wall surface of the through-hole 82 by CVD using TEOS or the like. At this time, as shown in FIG. 6A, the silicon oxide film 89 is formed on the upper surface of the uppermost semiconductor wafer or semiconductor chip 76a,
It is deposited on the wall surface of the through hole 82 of each semiconductor wafer or semiconductor chip 76a to 76c, and is hardly formed on the surface forming the gap 88 formed between each semiconductor wafer or each semiconductor chip 76. This is because the width of the gap 88 in the vertical direction is small because the passivation film 86 is thin,
In addition, the raw material gas is not supplied to the interior of the gap 88 because the periphery is a closed body.
【００４５】このようにしてシリコン酸化膜８９を形成
したならば、シリコン酸化膜８９が形成された半導体ウ
エハまたは半導体チップ７６ａの上方から全面的にエッ
チングし、図６（ｂ）に示したように、半導体ウエハま
たは半導体チップ７６ａの上面に成膜されたシリコン酸
化膜８９を除去する。これにより、貫通穴８２の壁面に
シリコン酸化膜８９からなる絶縁膜が形成される。After the silicon oxide film 89 is formed in this manner, the entire surface is etched from above the semiconductor wafer or the semiconductor chip 76a on which the silicon oxide film 89 is formed, as shown in FIG. Then, the silicon oxide film 89 formed on the upper surface of the semiconductor wafer or the semiconductor chip 76a is removed. Thus, an insulating film made of the silicon oxide film 89 is formed on the wall surface of the through hole 82.
【００４６】次に、貫通穴８２の下部を密閉し、貫通穴
８２の上部から導電性接着剤８４を圧入し、貫通穴８２
と空隙８８の内部に導電性接着剤８４を充填するととも
に、一番上の電極部７８の上面に被るように配置して硬
化させる。その後、前記したと同様に、積層したものが
半導体ウエハであればチップサイズに分割し、パッケー
ジ基板に実装する。Next, the lower portion of the through-hole 82 is sealed, and a conductive adhesive 84 is press-fitted from above the through-hole 82.
And the gap 88 is filled with a conductive adhesive 84, and is arranged so as to cover the upper surface of the uppermost electrode portion 78 and is cured. Thereafter, as described above, if the stacked wafer is a semiconductor wafer, the wafer is divided into chip sizes and mounted on a package substrate.
【００４７】図５（ｂ）は、第３実施形態に係る半導体
装置の変形例を示したものである。この半導体装置１１
０は、半導体チップ１１２（１１２ａ〜１１２ｃ）が積
層してある。各半導体チップ１１２は、半導体基板８０
の能動面の一部に凹部１１４が形成してあり、この凹部
１１４に電極部１１６が形成してある。このため、各半
導体チップ１１２を積層すると、下側の半導体チップの
電極部１１６の上部に空隙１１８が形成される。また、
凹部１１４の中央部には、電極部１１６と半導体基板８
０とを貫通した貫通穴８２が設けてある。この貫通穴８
２の壁面には、酸化シリコンなどからなる図示しない絶
縁膜が形成してある。そして、貫通穴８２と空隙１１８
とには、導電性接着剤８４が充填してあって、各半導体
チップ１１２の電極部１１６を電気的に接続していると
ともに、上下方向に隣接している半導体チップ１１２を
相互に接合している。この変形例の半導体装置１１０に
おいても前記と同様の効果を得ることができる。FIG. 5B shows a modification of the semiconductor device according to the third embodiment. This semiconductor device 11
0 indicates that the semiconductor chips 112 (112a to 112c) are stacked. Each semiconductor chip 112 includes a semiconductor substrate 80
A concave portion 114 is formed in a part of the active surface of FIG. Therefore, when the semiconductor chips 112 are stacked, a gap 118 is formed above the electrode portion 116 of the lower semiconductor chip. Also,
The electrode part 116 and the semiconductor substrate 8
0 is provided. This through hole 8
An insulating film (not shown) made of silicon oxide or the like is formed on the wall surface of No. 2. Then, the through hole 82 and the gap 118
Is filled with a conductive adhesive 84 to electrically connect the electrode portions 116 of the respective semiconductor chips 112 and to join the vertically adjacent semiconductor chips 112 to each other. I have. The same effect as described above can be obtained in the semiconductor device 110 of this modification.
【００４８】図７は、第４実施形態に係る半導体装置の
一部断面図である。図７（ａ）に示した半導体装置９０
は、２つの半導体チップ７６ａ、７６ｂが電極部７８を
対応させて積層してある。そして、上側の半導体チップ
７６ａは、電極部７８の下方の半導体基板８０に、非能
動面側となる下側に向けて漸次拡開しているテーパ状の
貫通穴９２が形成してあるとともに、電極部７８にも貫
通穴９２より小さな貫通穴９４が形成してある。また、
電極部７８には、例えば金からなるスタッドバンプ９６
が設けてある。このスタッドバンプ９６は、一部が貫通
穴９４を介して電極部７８の下方に延在するとともに、
半導体基板８０の下端から突出した接続部９８を有して
いて、接続部９８の下端が半導体チップ７６ａの下側に
配置、固定した半導体チップ７６ｂの電極部７８の上面
に接触し、両半導体チップ７６ａ、７６ｂのそれぞれの
電極部７８を電気的に接続している。FIG. 7 is a partial sectional view of a semiconductor device according to the fourth embodiment. Semiconductor device 90 shown in FIG.
In the semiconductor device, two semiconductor chips 76a and 76b are stacked so as to correspond to the electrode portions 78. The upper semiconductor chip 76a has a tapered through-hole 92 gradually expanding toward the lower side, which is the non-active surface side, in the semiconductor substrate 80 below the electrode portion 78, The electrode portion 78 also has a through hole 94 smaller than the through hole 92. Also,
The electrode portion 78 has a stud bump 96 made of, for example, gold.
Is provided. The stud bump 96 partially extends below the electrode portion 78 via the through hole 94,
It has a connecting portion 98 protruding from the lower end of the semiconductor substrate 80, and the lower end of the connecting portion 98 contacts the upper surface of the electrode portion 78 of the semiconductor chip 76 b which is arranged and fixed below the semiconductor chip 76 a, The respective electrode portions 78 of 76a and 76b are electrically connected.
【００４９】このように構成した半導体装置９０は、半
導体チップ７６ａの電極部７８上のパッシベーション膜
８６を除去したのち、半導体基板８０をエッチングして
貫通穴９２を形成する。さらに、半導体チップ７６ａの
電極部７８をエッチングして貫通穴９４を形成する。そ
の後、ワイヤボンディング装置のキャピラリーを電極部
７８の貫通穴９４の上に配置し、金ワイヤを引き出しつ
つスタッドバンプ９６を形成する。これにより、スタッ
ドバンプ９６が図７（ａ）に示したように、電極部７８
の下方に突出し、接続部９８が形成される。そして、電
極部７８を対応させて半導体チップ７６ａ、７６ｂを重
ね合わせて両者を接着剤などによって固着するとによ
り、スタッドバンプ９６の接続部９８を下方の半導体チ
ップ７６ｂの電極部７８に接触させ、電気的に接続す
る。In the semiconductor device 90 configured as described above, after removing the passivation film 86 on the electrode portion 78 of the semiconductor chip 76a, the semiconductor substrate 80 is etched to form a through hole 92. Further, the electrode portion 78 of the semiconductor chip 76a is etched to form a through hole 94. After that, the capillary of the wire bonding apparatus is arranged on the through hole 94 of the electrode section 78, and the stud bump 96 is formed while the gold wire is pulled out. As a result, the stud bumps 96 are connected to the electrode portions 78 as shown in FIG.
And a connecting portion 98 is formed. Then, the semiconductor chips 76a and 76b are overlapped so as to correspond to the electrode portions 78, and the semiconductor chips 76a and 76b are fixed to each other with an adhesive or the like, so that the connection portion 98 of the stud bump 96 is brought into contact with the electrode portion 78 of the lower semiconductor chip 76b. Connection.
【００５０】図７（ｂ）は、第４実施形態の変形例を示
したものである。この半導体装置１００は、上側の半導
体チップ７６ａの半導体基板８０と電極部７８とに貫通
穴９２、９４が形成してある。さらに、上側の半導体チ
ップ７６ａには、電極部７８にスタッドバンプ９６が形
成してある。このスタッドバンプ９６は、下部が電極部
７８を貫通して電極部７８の下方に突出した接続部９８
となっている。そして、接続部９８は、導電性接着剤１
０２を介して下側の半導体チップ７６ｂの電極部７８に
電気的に接続してある。このように導電性接着剤１０２
を用いて下側の半導体チップ７６ｂの電極部７８とスタ
ッドバンプ９６とを接合することにより、電気的接続を
より確実にすることができるとともに、半導体チップ７
６ａ、７６ｂを相互に接合することができる。なお、貫
通穴９２の壁面には、図示しない絶縁膜が設けてある。FIG. 7B shows a modification of the fourth embodiment. In the semiconductor device 100, through holes 92 and 94 are formed in the semiconductor substrate 80 and the electrode portion 78 of the upper semiconductor chip 76a. Further, stud bumps 96 are formed on the electrode portions 78 on the upper semiconductor chip 76a. The stud bump 96 has a connection portion 98 whose lower portion penetrates through the electrode portion 78 and protrudes below the electrode portion 78.
It has become. The connecting portion 98 is made of the conductive adhesive 1
02, it is electrically connected to the electrode portion 78 of the lower semiconductor chip 76b. Thus, the conductive adhesive 102
Is used to join the electrode portion 78 of the lower semiconductor chip 76b and the stud bump 96, so that electrical connection can be made more reliable and the semiconductor chip 7
6a, 76b can be joined together. An insulating film (not shown) is provided on the wall surface of the through hole 92.
【００５１】このように構成した図７（ｂ）の半導体装
置１００は、上側となる半導体チップ７６ａの電極部７
８に、前記と同様にしてスタッドバンプ９６を形成す
る。このスタットバンプ９６は、下端が半導体基板８０
の下面から突出しない程度の大きさにする。また、下側
となる半導体チップ７６ｂは、電極部７８の上のパッシ
ベーション膜８６を除去したのち、電極部７８の上に適
量の導電性接着剤１０２を配置する。そして、半導体チ
ップ７６ａを半導体チップ７６ｂの上に重ねて配置し、
両半導体チップ７６ａ、７６ｂの電極部７８を導電性接
着剤１０２、スタッドバンプ９６を介して電気的に接続
する。The semiconductor device 100 of FIG. 7B configured as described above has the electrode portion 7 of the upper semiconductor chip 76a.
8, a stud bump 96 is formed in the same manner as described above. The lower end of the stat bump 96 has a semiconductor substrate 80.
To a size that does not protrude from the lower surface of the. In the lower semiconductor chip 76b, after removing the passivation film 86 on the electrode portion 78, an appropriate amount of the conductive adhesive 102 is disposed on the electrode portion 78. Then, the semiconductor chip 76a is placed over the semiconductor chip 76b,
The electrode portions 78 of both the semiconductor chips 76a and 76b are electrically connected via the conductive adhesive 102 and the stud bumps 96.
【００５２】図７（ｃ）は、半導体基板に形成する貫通
穴の他の例を示したものである。この貫通穴１０４は、
電極部７８を設けた能動面側が半導体基板８０の面と直
交した壁面を有するストレート穴部１０６となってお
り、半導体基板８０の非能動面側が非能動面に向けて漸
次拡開した拡大穴部１０８となっている。FIG. 7 (c) shows another example of a through hole formed in a semiconductor substrate. This through hole 104
The active surface side on which the electrode portion 78 is provided is a straight hole portion 106 having a wall surface orthogonal to the surface of the semiconductor substrate 80, and the inactive surface side of the semiconductor substrate 80 is gradually enlarged toward the non-active surface. 108.
【００５３】このようにストレート穴部１０６と拡大穴
部１０８とからなる漏斗状の貫通穴１０４を形成する
と、半導体基板８０が厚い場合に、貫通穴１０４の非能
動面における開口が必要以上に大きくなるのを防げ、上
側の半導体チップの電極部と対応する下側半導体チップ
の電極部に隣接した電極部と接触する（接続される）危
険を避けることができる。さらに、電極部７８が近接し
て設けてある場合、隣接した貫通穴同士が途中でつなが
るのを防止できる。また、漏斗状の貫通穴１０４は、導
電材を充填する場合、全体がテーパ状に形成されている
貫通穴に比較して導電材の充填量を少なくできる。そし
て、電極部７８の上にスタッドバンプなどのバンプを形
成した半導体チップを積層する場合、バンプと貫通穴と
の位置合わせ、すなわち積層する半導体チップの位置合
わせを容易に行うことができる。When the funnel-shaped through hole 104 including the straight hole portion 106 and the enlarged hole portion 108 is formed as described above, the opening in the inactive surface of the through hole 104 becomes larger than necessary when the semiconductor substrate 80 is thick. Therefore, the risk of contact (connection) with an electrode portion of the lower semiconductor chip corresponding to the electrode portion of the upper semiconductor chip can be avoided. Further, when the electrode portions 78 are provided close to each other, it is possible to prevent adjacent through holes from being connected in the middle. Further, when the funnel-shaped through hole 104 is filled with a conductive material, the filling amount of the conductive material can be reduced as compared with a through hole formed in a tapered shape as a whole. When stacking semiconductor chips having bumps such as stud bumps formed on the electrode portions 78, alignment between the bumps and the through holes, that is, alignment of the stacked semiconductor chips can be easily performed.
【００５４】この貫通穴１０４は、次のようにして形成
することができる。This through hole 104 can be formed as follows.
【００５５】まず、半導体基板８０を非能動面側からウ
エットエッチングして拡大孔部１０８を形成する。所定
時間エッチングして拡大孔部１０８を形成したならば、
半導体チップ７６を洗浄、乾燥し、非能動面側からレー
ザ光を照射してストレート穴部１０６を形成する。な
お、ストレート穴部１０６を形成したのちにウエットエ
ッチングして貫通穴１０４の壁面を滑らかにする整形を
行ってもよい。また、電極部７８の貫通穴９４は、前記
と同様にして形成する。そして、ストレート穴１０６
は、プラズマを用いたドライエッチングによって形成し
てもよい。さらに、最初に体基板８０を貫通したストレ
ート穴１０６をレーザ光やプラズマエッチングによって
形成し、その後、ウエットエッチングによって拡大穴部
１０８を形成するようにしてもよい。First, the semiconductor substrate 80 is wet-etched from the non-active surface side to form the enlarged hole 108. After etching for a predetermined time to form the enlarged hole 108,
The semiconductor chip 76 is cleaned and dried, and a laser beam is irradiated from the non-active surface side to form the straight hole 106. After the formation of the straight hole portion 106, the wall surface of the through hole 104 may be shaped by wet etching to make the wall surface smooth. The through hole 94 of the electrode part 78 is formed in the same manner as described above. And the straight hole 106
May be formed by dry etching using plasma. Further, the straight hole 106 penetrating the body substrate 80 may be formed first by laser light or plasma etching, and then the enlarged hole 108 may be formed by wet etching.
【００５６】[0056]
【発明の効果】以上に説明したように、本発明によれ
ば、ワイヤを用いずに積層した半導体チップを相互に電
気的に接続することができ、電気的接続が容易となると
ともに、積層するほど半導体チップを小さくしなければ
ならないようなことがなく、パッケージの実装効率を高
めることができる。また、導電材によって電極部を接合
することにより、接着剤を用いずに半導体チップを相互
に接合することができる。As described above, according to the present invention, the stacked semiconductor chips can be electrically connected to each other without using wires, so that the electrical connection is facilitated and the stacked semiconductor chips are stacked. Thus, there is no need to make the semiconductor chip smaller, and the packaging efficiency can be improved. In addition, by joining the electrode portions with a conductive material, the semiconductor chips can be joined to each other without using an adhesive.
【図１】本発明の第１実施の形態に係る半導体装置の一
部断面図である。FIG. 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
【図２】第１実施形態に係る半導体装置の製造方法の実
施形態を説明する要部工程図である。FIG. 2 is a main part process diagram explaining the embodiment of the method for manufacturing the semiconductor device according to the first embodiment;
【図３】本発明の第２実施の形態に係る半導体装置の一
部断面図である。FIG. 3 is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
【図４】第２実施形態に係る半導体装置の製造方法の実
施形態を説明するフローチャートである。FIG. 4 is a flowchart illustrating an embodiment of a method of manufacturing a semiconductor device according to a second embodiment.
【図５】本発明の第３実施形態に係る半導体装置の一部
断面図である。FIG. 5 is a partial cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
【図６】積層した半導体ウエハまたは半導体チップの貫
通穴の壁面に絶縁膜を形成する方法を説明する図であ
る。FIG. 6 is a diagram illustrating a method of forming an insulating film on the wall surface of a through hole of a stacked semiconductor wafer or semiconductor chip.
【図７】本発明の第４実施形態に係る半導体装置の一部
断面図と、半導体基板に形成する貫通穴の他の例を示す
断面図である。FIG. 7 is a partial cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention and a cross-sectional view illustrating another example of a through hole formed in a semiconductor substrate.
１０ 半導体装置 １２ａ〜１２ｄ 半導体チップ １４、８０ 半導体基板 １６、１６ａ〜１６ｃ 電極部 １８ 導電材（半田） ２０ 貫通穴（接続穴） ３４ 導電材（半田ペースト） ３６ 半田プラグ ４０、５０ 半導体装置 ４２、７８ 電極部 ４４、８２ 貫通穴 ４５ 絶縁膜 ４６ 導電材（金属膜） ７６ａ〜７６ｃ 半導体チップ ８４ 導電材（導電性接着剤） ８８、１１８ 空隙 ８９ シリコン酸化膜 ９０、１００ 半導体装置 ９２、９４、１０４ 貫通穴 ９６ スタットバンプ １０２ 導電性接着剤 １１０ 半導体装置 １１２ａ〜１１２ｃ 半導体チップ １１６ 電極部 Reference Signs List 10 semiconductor device 12a to 12d semiconductor chip 14, 80 semiconductor substrate 16, 16a to 16c electrode portion 18 conductive material (solder) 20 through hole (connection hole) 34 conductive material (solder paste) 36 solder plug 40, 50 semiconductor device 42, 78 electrode portion 44, 82 through hole 45 insulating film 46 conductive material (metal film) 76a to 76c semiconductor chip 84 conductive material (conductive adhesive) 88, 118 void 89 silicon oxide film 90, 100 semiconductor device 92, 94, 104 Through hole 96 Stat bump 102 Conductive adhesive 110 Semiconductor device 112a-112c Semiconductor chip 116 Electrode
Claims (17)
層してある半導体装置において、前記各半導体チップの
電極部と対応した部分の半導体基板を貫通して形成した
穴に充填した導電材により、前記各半導体チップを相互
に接合したことを特徴とする半導体装置。In a semiconductor device in which a plurality of semiconductor chips on which elements are formed are stacked, a conductive material filled in a hole formed through a semiconductor substrate in a portion corresponding to an electrode portion of each semiconductor chip is provided. A semiconductor device, wherein the semiconductor chips are joined to each other.
あることを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the conductive material is a solder or a low melting point metal.
を特徴とする請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein said conductive material is a conductive adhesive.
層した半導体装置において、前記各半導体チップは電極
部を対応させて積層してあり、これらの電極部が電極部
と半導体基板とを貫通して設けた貫通穴内に配置した導
電材により、電気的に相互に接続してあることを特徴と
する半導体装置。4. In a semiconductor device in which a plurality of semiconductor chips on which elements are formed are stacked, each of the semiconductor chips is stacked so as to correspond to an electrode portion, and these electrode portions penetrate the electrode portion and the semiconductor substrate. A semiconductor device electrically connected to each other by a conductive material disposed in the through hole provided.
した導電性膜であることを特徴とする請求項４に記載の
半導体装置。5. The semiconductor device according to claim 4, wherein said conductive material is a conductive film formed on a wall surface of said through hole.
電性接着剤であることを特徴とする請求項４に記載の半
導体装置。6. The semiconductor device according to claim 4, wherein the conductive material is a conductive adhesive filled in the through hole.
記半導体チップの前記電極部上の保護膜が除去されて形
成された空隙を充填していることを特徴とする請求項６
に記載の半導体装置。7. The semiconductor device according to claim 6, wherein the conductive adhesive fills a gap formed by removing a protective film on the electrode portion of the semiconductor chip located below.
3. The semiconductor device according to claim 1.
積層した半導体装置において、 前記各半導体チップは、電極部を対応させて積層してあ
り、 上方に位置する前記半導体チップは、前記電極部に対応
した部分の半導体基板に形成した貫通穴と、前記電極部
を貫通して形成したバンプとを有し、 下方に位置する前記半導体チップは、前記電極部が前記
バンプを介して上方に位置する前記半導体チップの前記
電極部に電気的に接続してある、 ことを特徴とする半導体装置。8. A semiconductor device in which a plurality of semiconductor chips on which elements are formed are stacked, wherein each of the semiconductor chips is stacked so as to correspond to an electrode portion, and the semiconductor chip located above is formed by the electrode portion. A through hole formed in the semiconductor substrate in a portion corresponding to the above, and a bump formed through the electrode portion, wherein the semiconductor chip located below the electrode portion is located above the bump via the bump. A semiconductor device that is electrically connected to the electrode portion of the semiconductor chip.
電極部と前記上方に位置する半導体チップの前記バンプ
とは、導電性接着剤により接合してあることを特徴とす
る請求項８に記載の半導体装置。9. The semiconductor device according to claim 8, wherein the electrode portion of the lower semiconductor chip and the bump of the upper semiconductor chip are joined by a conductive adhesive. Semiconductor device.
と対応した部分の半導体基板に貫通穴を形成する工程
と、 前記貫通穴を覆って導電材の盛上げ部を形成する工程
と、 前記導電材を配置した前記半導体チップの複数を積層し
て前記電極部を相互に電気的に接続するとともに、前記
各半導体チップを相互に接合する工程と、 を有することを特徴とする半導体装置の製造方法。10. A step of forming a through hole in a portion of the semiconductor substrate corresponding to an electrode portion of a semiconductor chip on which an element is formed; a step of forming a raised portion of a conductive material covering the through hole; Stacking a plurality of the semiconductor chips on which the electrodes are arranged, electrically connecting the electrode portions to each other, and joining the semiconductor chips to each other.
の半田ペーストを配置する工程と、半田ペーストを配置
した前記半導体チップを加熱して半田ペーストを溶融
し、半田ペースト中のフラックスを除去する工程とによ
り形成し、 前記接合は、積層した複数の前記半導体チップを加熱し
て前記貫通穴に配置された半田を溶融して行う、 ことを特徴とする請求項１０に記載の半導体装置の製造
方法。11. The method according to claim 11, wherein the conductive material is a solder paste, and the raised portion covers the through hole and arranges more solder paste than the volume of the hole, and heats the semiconductor chip on which the solder paste is arranged. And melting the solder paste to remove the flux in the solder paste. The bonding is performed by heating the plurality of stacked semiconductor chips and melting the solder arranged in the through holes. The method of manufacturing a semiconductor device according to claim 10, wherein:
金属を加熱、加圧して行うことを特徴とする請求項１０
に記載の半導体装置の製造方法。12. The semiconductor device according to claim 10, wherein the conductive material is a low-melting metal, and the bonding is performed by heating and pressing the low-melting metal of a plurality of stacked semiconductor chips.
13. The method for manufacturing a semiconductor device according to item 5.
導体チップの複数を、予め定めた電極部を対応させて積
層する工程と、 積層した前記半導体ウエハまたは半導体チップの前記電
極部と半導体基板とを貫通した貫通穴を形成する工程
と、 前記貫通穴内に導電材を設けて前記電極部を相互に電気
的に接続する工程と、 を有することを特徴とする半導体装置の製造方法。13. A step of laminating a plurality of semiconductor wafers or semiconductor chips having elements formed thereon in correspondence with predetermined electrode portions, and penetrating through the electrode portions and the semiconductor substrate of the laminated semiconductor wafers or semiconductor chips. Forming a through hole, and providing a conductive material in the through hole to electrically connect the electrode portions to each other.
穴の壁面に蒸着またはメッキにより金属膜を形成して行
うことを特徴とする請求項１３に記載の半導体装置の製
造方法。14. The method according to claim 13, wherein the electrical connection of the electrode unit is performed by forming a metal film on a wall surface of the through hole by vapor deposition or plating.
チップは、前記電極部の上に形成してある保護膜の一部
が除去され、前記電極部の少なくとも一部が露出させて
あり、 前記各電極部の電気的接続は、前記貫通穴と前記保護膜
を除去して形成された空隙とに導電性接着剤を注入して
行うこと、 を特徴とする請求項１３に記載の半導体装置の製造方
法。15. The semiconductor wafer or the semiconductor chip, wherein a part of a protective film formed on the electrode part is removed, and at least a part of the electrode part is exposed. The method for manufacturing a semiconductor device according to claim 13, wherein the electrical connection of the portions is performed by injecting a conductive adhesive into the through hole and a gap formed by removing the protective film. .
電極部に対応した半導体基板とを貫通した貫通穴を形成
する工程と、 前記電極部に形成した貫通穴を介して電極部を貫通した
バンプを形成する工程と、 前記第１の半導体チップの非能動面側に第２の半導体チ
ップを重ねて配置し、前記バンプを介して前記第２の半
導体チップの電極部を前記第１の半導体チップの前記電
極部に電気的に接続する工程と、 を有することを特徴とする半導体装置の製造方法。16. A step of forming a through hole penetrating an electrode portion of a first semiconductor chip and a semiconductor substrate corresponding to the electrode portion, and penetrating the electrode portion through the through hole formed in the electrode portion. Forming a bump formed on the first semiconductor chip, disposing a second semiconductor chip on the non-active surface side of the first semiconductor chip, and connecting an electrode portion of the second semiconductor chip to the first semiconductor chip via the bump. Electrically connecting the semiconductor chip to the electrode portion of the semiconductor chip.
半導体チップとの電極部を電気的に接続する工程は、 前記第１の半導体チップの半導体基板に形成した貫通穴
内、または前記第２の半導体チップの前記電極部上に導
電性接着剤を配置する工程と、 第１の半導体チップの非能動面側に前記第２の半導体装
置を配置して重ね、前記第２の半導体チップの電極部と
前記バンプとを前記導電性接着剤によって接合する工程
と、 を有することを特徴とする請求項１６に記載の半導体装
置の製造方法。17. The step of electrically connecting the electrode portions of the first semiconductor chip and the second semiconductor chip, the step of electrically connecting the electrode portions in a through-hole formed in a semiconductor substrate of the first semiconductor chip or the second semiconductor chip. Disposing a conductive adhesive on the electrode portion of the semiconductor chip; and disposing and overlapping the second semiconductor device on the non-active surface side of the first semiconductor chip, thereby forming an electrode on the second semiconductor chip. 17. The method according to claim 16, further comprising: bonding a portion and the bump with the conductive adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23457799A JP3726579B2 (en) | 1999-08-20 | 1999-08-20 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23457799A JP3726579B2 (en) | 1999-08-20 | 1999-08-20 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001060654A true JP2001060654A (en) | 2001-03-06 |
| JP3726579B2 JP3726579B2 (en) | 2005-12-14 |
Family
ID=16973203
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23457799A Expired - Lifetime JP3726579B2 (en) | 1999-08-20 | 1999-08-20 | Semiconductor device and manufacturing method thereof |
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