JP2011146655A - Semiconductor device manufacturing method and laminated semiconductor device - Google Patents

Semiconductor device manufacturing method and laminated semiconductor device Download PDF

Info

Publication number
JP2011146655A
JP2011146655A JP2010008444A JP2010008444A JP2011146655A JP 2011146655 A JP2011146655 A JP 2011146655A JP 2010008444 A JP2010008444 A JP 2010008444A JP 2010008444 A JP2010008444 A JP 2010008444A JP 2011146655 A JP2011146655 A JP 2011146655A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
substrates
recess
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010008444A
Other languages
Japanese (ja)
Other versions
JP2011146655A5 (en
JP5445159B2 (en
Inventor
Yasuo Tezuka
靖夫 手塚
So Mitsuishi
創 三ッ石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nikon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp filed Critical Nikon Corp
Priority to JP2010008444A priority Critical patent/JP5445159B2/en
Publication of JP2011146655A publication Critical patent/JP2011146655A/en
Publication of JP2011146655A5 publication Critical patent/JP2011146655A5/ja
Application granted granted Critical
Publication of JP5445159B2 publication Critical patent/JP5445159B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9205—Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of efficiently manufacturing a laminated semiconductor device having a plurality of substrates stacked. <P>SOLUTION: A semiconductor device manufacturing method is the method of manufacturing the laminated semiconductor device by stacking the plurality of substrates, and includes a recess forming step of forming a recess in one of the plurality of substrates where a circuit is formed, a superposing step of superposing one substrate on another substrate among the plurality of substrates, and a conduction formation step of forming an electric conduction path between a circuit of the one substrate and a circuit of the other substrate by introducing a conductive material into the recess of the one substrate after the superposing step. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置製造方法及び積層半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a stacked semiconductor device.

半導体装置の実装面積を拡大することなく、実効的な実装密度を向上させる目的で、各々に素子および回路が形成された半導体基板を複数積層する積層半導体装置が注目されている。積層半導体装置の製造方法としては、特許文献１に記載されているように、回路が形成された半導体基板に接続用バンプを形成して、基板と基板の間をバンプで接続することにより、複数の基板を厚さ方向に積層することが知られている。   For the purpose of improving the effective mounting density without increasing the mounting area of the semiconductor device, a stacked semiconductor device in which a plurality of semiconductor substrates each having an element and a circuit formed thereon is attracting attention. As described in Patent Document 1, a method for manufacturing a laminated semiconductor device includes forming connection bumps on a semiconductor substrate on which a circuit is formed, and connecting the substrate and the substrate with bumps. It is known that these substrates are laminated in the thickness direction.

特開平１１−２６１０００号公報JP 11-261000 A

しかしながら、確実なバンプ接続を確保することを目的として、適切なバンプ用材料を選択しなければならない上に、バンプの形成に加熱プロセスなどを要するので、製造過程の工程数及び時間を増やさなければならない。   However, in order to ensure a reliable bump connection, an appropriate bump material must be selected, and a heating process is required to form the bump, so the number of manufacturing steps and time must be increased. Don't be.

上記課題を解決するために、本発明の第１の態様においては、複数の基板を貼り合わせて積層半導体装置を製造する半導体装置製造方法であって、回路が形成された複数の基板を準備する準備ステップと、複数の基板のうちの一の基板に凹部を形成する凹部形成ステップと、一の基板を複数の基板のうちの他の基板に重ね合わせる重ね合わせステップと、重ね合わせステップの後に、一の基板の凹部に導電性材料を導入することにより、一の基板の回路と他の基板の回路との間の電気的な導通路を形成する導通形成ステップとを備える半導体装置製造方法が提供される。   In order to solve the above problems, in the first aspect of the present invention, a semiconductor device manufacturing method for manufacturing a laminated semiconductor device by bonding a plurality of substrates, wherein a plurality of substrates on which circuits are formed is prepared. After the preparation step, the concave portion forming step for forming the concave portion in one of the plurality of substrates, the superposing step for superposing one substrate on the other substrate among the plurality of substrates, and the superposing step, Provided is a semiconductor device manufacturing method including a conduction forming step of forming an electrical conduction path between a circuit of one substrate and a circuit of another substrate by introducing a conductive material into a recess of the one substrate Is done.

本発明の第２の態様においては、上記半導体装置製造方法により製造される積層半導体装置が提供される。   In a second aspect of the present invention, a laminated semiconductor device manufactured by the above semiconductor device manufacturing method is provided.

なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではない。また、これらの特徴群のサブコンビネーションもまた、発明となりうる。   It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

半導体装置製造方法の一実施形態のフローチャートを示す。2 shows a flowchart of an embodiment of a semiconductor device manufacturing method. 回路が形成された基板１００を概念的に示す平面図である。It is a top view which shows notionally the board | substrate 100 with which the circuit was formed. 基板１００の断面の概念図である。1 is a conceptual diagram of a cross section of a substrate 100. FIG. 基板３００の断面の概念図である。2 is a conceptual diagram of a cross section of a substrate 300. FIG. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 基板４００の断面の概念図である。2 is a conceptual diagram of a cross section of a substrate 400. FIG. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 基板６００の断面の概念図である。2 is a conceptual diagram of a cross section of a substrate 600. FIG. 基板７００の断面の概念図である。2 is a conceptual diagram of a cross section of a substrate 700. FIG. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device. 半導体装置の製造過程における基板の断面の概念図である。It is a conceptual diagram of the cross section of the board | substrate in the manufacture process of a semiconductor device.

以下、発明の実施の形態を通じて本発明を説明するが、以下の実施形態は特許請求の範囲にかかる発明を限定するものではない。また、実施形態の中で説明されている特徴の組み合わせの全てが発明の解決手段に必須であるとは限らない。   Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

図１は、複数の基板を貼り合わせて積層半導体装置を製造する半導体装置製造方法の一実施形態のフローチャートを示す。本半導体装置製造方法は、回路が形成された複数の基板を準備するステップＳ０１０と、基板に凹部を形成するステップＳ０２０と、基板の凹部を貫通孔に加工するステップＳ０３０と、複数の基板を重ね合わせるステップＳ０４０と、電気的な導通路を形成するステップＳ０５０と、複数基板の間に樹脂を注入するステップＳ０６０と、貼り合わせた基板を個片化するステップＳ０７０とを備える。図２から図１２は、本半導体装置製造方法により半導体装置を製造する各過程を示す概念図である。以下図面を用いて本半導体装置製造方法を説明する。   FIG. 1 shows a flowchart of an embodiment of a semiconductor device manufacturing method for manufacturing a laminated semiconductor device by bonding a plurality of substrates. In this semiconductor device manufacturing method, step S010 for preparing a plurality of substrates on which circuits are formed, step S020 for forming recesses in the substrate, step S030 for processing recesses in the substrate into through holes, and stacking the plurality of substrates are overlapped. Step S040 for matching, Step S050 for forming an electrical conduction path, Step S060 for injecting resin between the plurality of substrates, and Step S070 for separating the bonded substrates into individual pieces are provided. 2 to 12 are conceptual diagrams showing each process of manufacturing a semiconductor device by this semiconductor device manufacturing method. The semiconductor device manufacturing method will be described below with reference to the drawings.

図２は、電子回路が形成された基板１００を概念的に示す平面図であり、図３は基板１００の断面図である。ステップＳ０１０において、このように電子回路が形成された基板を複数準備する。図２の基板１００は円盤状であり、少なくとも一方の面に、電気回路が二次元的に周期的に形成されている。基板１００は、ウェハ１０２と、回路１１０を含む。回路１１０は、電子素子１０４と、プラグ１０６と、配線１０８と、電極１１２と、絶縁層１１４とを含む。これら、電子素子１０４、プラグ１０６、配線１０８、電極１１２および絶縁層１１４は、リソグラフィ、エッチング等の半導体プロセスにより形成される。   FIG. 2 is a plan view conceptually showing the substrate 100 on which an electronic circuit is formed, and FIG. 3 is a cross-sectional view of the substrate 100. In step S010, a plurality of substrates on which electronic circuits are thus formed are prepared. The substrate 100 shown in FIG. 2 has a disk shape, and an electric circuit is periodically and two-dimensionally formed on at least one surface. The substrate 100 includes a wafer 102 and a circuit 110. The circuit 110 includes an electronic element 104, a plug 106, a wiring 108, an electrode 112, and an insulating layer 114. The electronic element 104, the plug 106, the wiring 108, the electrode 112, and the insulating layer 114 are formed by a semiconductor process such as lithography and etching.

ウェハ１０２は、電子素子を形成する基板であって、搬送等に対して十分な機械的強度を有する。ウェハ１０２は、Ｓｉ基板、ＳＯＩ（ｓｉｌｉｃｏｎ−ｏｎ−ｉｎｓｕｌａｔｏｒ）基板、Ｇｅ基板、ＧＯＩ（ｇｅｒｍａｎｉｕｍ−ｏｎ−ｉｎｓｕｌａｔｏｒ）基板等であってもよく、ＧａＡｓ等の化合物半導体基板であってよい。さらに、ウェハ１０２は、例えば単結晶基板である。   The wafer 102 is a substrate on which electronic elements are formed, and has sufficient mechanical strength for transportation and the like. The wafer 102 may be a Si substrate, an SOI (silicon-on-insulator) substrate, a Ge substrate, a GOI (germanium-on-insulator) substrate, or a compound semiconductor substrate such as GaAs. Further, the wafer 102 is, for example, a single crystal substrate.

電子素子１０４は、基板１００の電気回路を形成する。図３には、電子素子１０４の一例として、電界効果トランジスタを概略的に示したが、電界効果トランジスタに限られず、抵抗等の他の電子素子あってもよい。   The electronic element 104 forms an electric circuit of the substrate 100. Although FIG. 3 schematically shows a field effect transistor as an example of the electronic element 104, the electronic element 104 is not limited to the field effect transistor, and may be another electronic element such as a resistor.

配線１０８は、電子素子と電子素子との間を接続する電気的な導通路である。図３に示されるように、配線１０８は、多層に形成されてよい。配線１０８は、導電性材料により形成される。   The wiring 108 is an electrical conduction path that connects between the electronic elements. As shown in FIG. 3, the wiring 108 may be formed in multiple layers. The wiring 108 is formed of a conductive material.

プラグ１０６は、電子素子１０４と配線１０８との間、又は異なる配線層間の配線１０８を接続する電気的な導通路である。プラグ１０６は、導電性材料により形成される。   The plug 106 is an electrical conduction path that connects the wiring 108 between the electronic element 104 and the wiring 108 or between different wiring layers. The plug 106 is made of a conductive material.

電極１１２は、当該基板１００に対して他の基板が積層される場合に、それらの基板の間の電気的な導通を確保する。電極１１２は、基板１００の表面（図３においては基板１００の上の面）より突出するように形成される。例えば、電極１１２は、基板１００の表面より数μｍ高く形成される。電極１１２は、導電性材料により形成される。電極１１２の材料として、Ａｌ、Ｃｕ又はＷ等が例示できる。   The electrode 112 ensures electrical continuity between the substrates when another substrate is stacked on the substrate 100. The electrode 112 is formed so as to protrude from the surface of the substrate 100 (the surface above the substrate 100 in FIG. 3). For example, the electrode 112 is formed several μm higher than the surface of the substrate 100. The electrode 112 is formed of a conductive material. Examples of the material of the electrode 112 include Al, Cu, and W.

絶縁層１１４は、電子素子と配線との間、電子素子と電子素子との間、又は異なる配線層の間の電気的な絶縁を確保する。絶縁層１１４は、配線層に合わせて多層に形成されてよい。絶縁層１１４は、電気絶縁材料により形成される。絶縁層１１４の材料として、ＳｉＯ２、Ａｌ２Ｏ３、ＳｉＮ、Ｓｉ３Ｎ４等が例示できる。 The insulating layer 114 ensures electrical insulation between the electronic element and the wiring, between the electronic element and the electronic element, or between different wiring layers. The insulating layer 114 may be formed in multiple layers in accordance with the wiring layer. The insulating layer 114 is made of an electrically insulating material. Examples of the material of the insulating layer 114 include SiO 2 , Al 2 O 3 , SiN, Si 3 N 4 and the like.

図４は、基板１００に重ね合わされる他の基板３００の断面を概念的に示す。基板３００は、図２に示す基板１００と同様に、円盤状であり、少なくとも一方の面に、電気回路が二次元的に周期的に形成されている。基板３００も基板１００と同様に、ウェハ３０２と、回路３１０を含む。回路３１０は、電子素子３０４と、プラグ３０６と、配線３０８と、電極３１２と、金属層３１４と、絶縁膜３１６と、絶縁層３１８とを含む。ウェハ３０２、電子素子３０４、プラグ３０６、配線３０８及び電極３１２は、それぞれ基板１００のウェハ１０２、電子素子１０４、プラグ１０６、配線１０８及び電極１１２と同様の構成および作用を有するので説明を省略する。   FIG. 4 conceptually shows a cross section of another substrate 300 superimposed on the substrate 100. Similar to the substrate 100 shown in FIG. 2, the substrate 300 has a disk shape, and an electric circuit is periodically and two-dimensionally formed on at least one surface. Similar to the substrate 100, the substrate 300 includes a wafer 302 and a circuit 310. The circuit 310 includes an electronic element 304, a plug 306, a wiring 308, an electrode 312, a metal layer 314, an insulating film 316, and an insulating layer 318. Since the wafer 302, the electronic element 304, the plug 306, the wiring 308, and the electrode 312 have the same configurations and functions as the wafer 102, the electronic element 104, the plug 106, the wiring 108, and the electrode 112 of the substrate 100, respectively, description thereof is omitted.

金属層３１４は、電極３１２の上に形成され、基板３００に積層される基板１００との電気的接続をより確実にする。金属層３１４は、電気伝導率の高い金属、例えばＡｕ、Ａｕ／Ｉｎ、Ｃｕ、Ａｌ等により形成される。金属層３１４は、省かれてもよい。   The metal layer 314 is formed on the electrode 312 and makes the electrical connection with the substrate 100 stacked on the substrate 300 more reliable. The metal layer 314 is formed of a metal having high electrical conductivity, such as Au, Au / In, Cu, Al, or the like. The metal layer 314 may be omitted.

図５から図７は、基板１００に凹部１２０が形成されるステップ（Ｓ０２０）を示す概略断面図である。図５に示すように、凹部１２０が形成されるべき位置に開口が設けられたレジストパターン１１６を、リソグラフィにより基板１００の表面に形成する。その後、選択エッチング等により凹部１２０を形成する。また、凹部１２０は、基板１００作成する過程において形成されても良い。   5 to 7 are schematic cross-sectional views showing the step (S020) in which the recess 120 is formed in the substrate 100. FIG. As shown in FIG. 5, a resist pattern 116 having an opening at a position where the recess 120 is to be formed is formed on the surface of the substrate 100 by lithography. Thereafter, the recess 120 is formed by selective etching or the like. Further, the recess 120 may be formed in the process of forming the substrate 100.

図６に示すように、基板１００の表面には絶縁膜１２２が成膜される。絶縁膜１２２は、電気絶縁材料により形成される。絶縁膜１２２の材料として、ＳｉＯ２、ＳｉＮ、Ｓｉ３Ｎ４等が例示できる。絶縁膜１２２の成膜方法としては、スパッタ、ＣＶＤ又は熱酸化等が挙げられる。 As shown in FIG. 6, an insulating film 122 is formed on the surface of the substrate 100. The insulating film 122 is made of an electrically insulating material. Examples of the material of the insulating film 122 include SiO 2 , SiN, Si 3 N 4 and the like. Examples of a method for forming the insulating film 122 include sputtering, CVD, and thermal oxidation.

図７に示すように、リソグラフィ及びエッチングにより、不要な絶縁膜１２２が除去されて、凹部１２０の表面だけが絶縁膜１２２に覆われた凹部１３０が形成される。これにより絶縁膜１２２に覆われた凹部１３０を有する基板１４０が得られる。絶縁膜１２２は、凹部１３０の内部に形成する導通路からの電流リークを防止することができる。   As shown in FIG. 7, unnecessary insulating film 122 is removed by lithography and etching, and a recess 130 in which only the surface of recess 120 is covered with insulating film 122 is formed. As a result, the substrate 140 having the recess 130 covered with the insulating film 122 is obtained. The insulating film 122 can prevent current leakage from a conduction path formed inside the recess 130.

図７に示す状態において、凹部１３０は基板１４０を貫通していない。なお、図５から図７においては電子回路が形成された基板１００を準備し、当該基板１００に凹部１２０、１３０を形成した例を説明した。ただし、凹部１２０の形成のタイミングはこれに限られず、基板１００の電子回路を形成する半導体プロセスにおいて凹部１２０、１３０を同時に形成してもよい。   In the state shown in FIG. 7, the recess 130 does not penetrate the substrate 140. 5 to 7, the example in which the substrate 100 on which the electronic circuit is formed is prepared and the recesses 120 and 130 are formed on the substrate 100 has been described. However, the formation timing of the recess 120 is not limited to this, and the recesses 120 and 130 may be formed simultaneously in a semiconductor process for forming an electronic circuit of the substrate 100.

図８および図９は、基板１４０の凹部１３０が貫通孔２０２に加工されるステップ（Ｓ０３０）を示す概略断面図である。ステップＳ０３０において、基板１４０が薄化されることにより、ステップＳ０２０で形成された基板１４０を貫通していない凹部１３０が貫通孔２０２に加工される。   8 and 9 are schematic cross-sectional views showing a step (S030) in which the recess 130 of the substrate 140 is processed into the through hole 202. FIG. In step S030, the substrate 140 is thinned, so that the recess 130 that does not penetrate the substrate 140 formed in step S020 is processed into the through hole 202.

図８に示すように、基板１４０の表面に支持基板１５０を貼り合せる。支持基板１５０は、後続の基板１４０の薄化プロセスにおいて、基板１４０が破壊しないように基板１４０を補強する。支持基板１５０は、基板１４０を補強するのに十分な強度を有する。例えば、支持基板１５０の材料としては、シリコン等の半導体、ガラス、セラミックス等が挙げられる。この場合に、支持基板１５０の表面に接着剤を塗布して、基板１４０を貼り合せる。接着剤に代えて、分子間力又は静電気力等により支持基板１５０を基板１４０に貼付してもよい。   As shown in FIG. 8, a support substrate 150 is bonded to the surface of the substrate 140. The support substrate 150 reinforces the substrate 140 so that the substrate 140 is not destroyed in the subsequent thinning process of the substrate 140. The support substrate 150 has sufficient strength to reinforce the substrate 140. For example, examples of the material of the support substrate 150 include a semiconductor such as silicon, glass, ceramics, and the like. In this case, an adhesive is applied to the surface of the support substrate 150, and the substrate 140 is bonded. Instead of the adhesive, the support substrate 150 may be attached to the substrate 140 by intermolecular force or electrostatic force.

図９に示すように、グラインド、ＣＭＰ等の方法により、基板１４０を裏面から薄化して、上記の凹部１３０を貫通孔２０２に加工する。例えば、８インチ径で厚さ７０５μｍまたは１２インチ径で厚さ７７５μｍの基板１４０を、厚さ５０μｍに薄化する。これにより、貫通孔２０２を有する基板２００が得られる。積層半導体装置を形成する基板の厚さを薄くすることにより、積層半導体装置を小型化することができる。さらに、薄化により凹部１３０を貫通孔２０２に加工するので、厚い状態の基板１００に深い貫通孔を形成するのに比べて、加工時間を短縮することができる。   As shown in FIG. 9, the substrate 140 is thinned from the back surface by a method such as grinding or CMP, and the recess 130 is processed into the through hole 202. For example, the substrate 140 having a diameter of 8 inches and a thickness of 705 μm or a diameter of 12 inches and a thickness of 775 μm is thinned to a thickness of 50 μm. Thereby, the substrate 200 having the through hole 202 is obtained. By reducing the thickness of the substrate on which the stacked semiconductor device is formed, the stacked semiconductor device can be reduced in size. Furthermore, since the recess 130 is processed into the through hole 202 by thinning, the processing time can be shortened as compared with the case where the deep through hole is formed in the thick substrate 100.

図１０は、複数の基板を重ね合わせるステップ（Ｓ０４０）を示す概略断面図である。ステップＳ０４０において、基板３００と基板２００とが重ね合わされる。重ね合わせは、別途設けられるアライナーにより、基板３００の金属層３１４と基板２００の貫通孔２０２との位置が合うように、精密に基板３００と基板２００の位置合せがされてから、基板３００と基板２００とが重ね合わせされる。基板３００は、製造された積層半導体装置の全体の強度を確保するべく、薄化しなくてよい。さらに、基板３００と基板２００を加熱して接合してもよく、加圧して接合してもよく、又は加熱及び加圧して接合してもよい。基板３００と基板２００とを重ね合わせた後に、基板２００から支持基板１５０が除去される。   FIG. 10 is a schematic cross-sectional view showing the step of superposing a plurality of substrates (S040). In step S040, the substrate 300 and the substrate 200 are overlaid. Overlaying is performed after the substrate 300 and the substrate 200 are precisely aligned so that the metal layer 314 of the substrate 300 and the through hole 202 of the substrate 200 are aligned by an aligner provided separately. 200 is superimposed. The substrate 300 does not have to be thinned to ensure the overall strength of the manufactured laminated semiconductor device. Further, the substrate 300 and the substrate 200 may be bonded by heating, may be bonded by pressing, or may be bonded by heating and pressing. After the substrate 300 and the substrate 200 are overlapped, the support substrate 150 is removed from the substrate 200.

図１１は、基板３００上に、複数の基板２００、２１０、２２０が重ね合わされた状態を示す。図１１に示すように、それぞれの基板２００、２１０、２２０における貫通孔２０２の位置が合うように、基板２００の上に基板２１０を重ね合わせて、更にその上に基板２２０を重ね合わせる。即ち、重ね合わせステップＳ０４０を繰り返して、基板３００に基板２００、基板２１０及び基板２２０等を複数重ね合わせる。   FIG. 11 shows a state in which a plurality of substrates 200, 210, and 220 are superimposed on the substrate 300. As shown in FIG. 11, the substrate 210 is overlaid on the substrate 200 so that the positions of the through holes 202 in the respective substrates 200, 210, and 220 are aligned, and further the substrate 220 is overlaid thereon. That is, the overlaying step S040 is repeated to superimpose a plurality of substrates 200, 210, 220, etc. on the substrate 300.

図１１には、４枚の基板を重ね合わせた例が示されているが、重ね合わせる基板の枚数を限定されない。また、図１１には、基板２１０及び基板２２０を基板２００と同じ電子回路構造を有する基板として表示したが、基板２１０及び基板２２０は基板２００と異なる電子回路を有しても良い。   Although FIG. 11 shows an example in which four substrates are superimposed, the number of substrates to be superimposed is not limited. 11 shows the substrate 210 and the substrate 220 as substrates having the same electronic circuit structure as the substrate 200, the substrate 210 and the substrate 220 may have an electronic circuit different from the substrate 200.

図１２は、複数の基板２００等の間の電気的な導通路３３２を形成するステップ（Ｓ０５０）を示す概略断面図である。ステップＳ０５０において、前のステップで位置合せされた基板２００、基板２１０及び基板２２０の貫通孔２０２に導電性材料を導入することにより、導通路３３２を形成する。導通路３３２は、基板２００、基板２１０、基板２２０及び基板３００の電子回路の間の電気的な導通を形成する。   FIG. 12 is a schematic cross-sectional view showing a step (S050) of forming an electrical conduction path 332 between a plurality of substrates 200 and the like. In step S050, a conductive path 332 is formed by introducing a conductive material into the through holes 202 of the substrate 200, the substrate 210, and the substrate 220 aligned in the previous step. The conduction path 332 forms electrical conduction between the electronic circuits of the substrate 200, the substrate 210, the substrate 220, and the substrate 300.

導通路３３２の材料として、Ｃｕ、Ａｕ、Ａｇ、Ａｌ又はＷ等が挙げられる。導通路３３２は、スパッタ、メッキ、ＣＶＤ等の方法により形成される。例えば、無電解メッキ法によりＣｕの導通路３３２を形成する。この場合、基板２００、２１０、２２０は、それぞれの電極１１２によって導通路３３２と導通するとともに、基板３００は金属層３１４を通じて導通路３３２と導通する。よって、基板２００、２１０、２２０、３００は、導通路３３２を介して互いに電気的に接続される。以上のステップにより、積層基板３４０が形成できる。   Examples of the material of the conduction path 332 include Cu, Au, Ag, Al, or W. The conduction path 332 is formed by a method such as sputtering, plating, or CVD. For example, the Cu conduction path 332 is formed by electroless plating. In this case, the substrates 200, 210, and 220 are electrically connected to the conduction path 332 by the respective electrodes 112, and the substrate 300 is electrically connected to the conduction path 332 through the metal layer 314. Therefore, the substrates 200, 210, 220, and 300 are electrically connected to each other through the conduction path 332. Through the above steps, the multilayer substrate 340 can be formed.

さらに、積層基板３４０の間隙３２２及び間隙３２４に樹脂が注入される（Ｓ０６０）。例えばエポキシ系絶縁性接着剤等の樹脂等が注入される。これにより、基板３００と基板２００とを貼り合わせの強度を高めることができる。なお、ステップＳ０６０において樹脂を注入するのに代えて、ステップＳ０４０で基板が重ね合わされる毎に、樹脂を注入してもよい。樹脂を注入することにより、積層半導体装置の強度を補強することができる。なお、絶縁樹脂を注入することにより、基板の間の予想外の電気導通を防ぐことができる。樹脂等を注入することに代えて、基板３００と基板２００との間の分子間力等により、貼り合わせの強度を確保してもよい。   Further, resin is injected into the gap 322 and the gap 324 of the multilayer substrate 340 (S060). For example, a resin such as an epoxy insulating adhesive is injected. Thereby, the intensity | strength of bonding the board | substrate 300 and the board | substrate 200 can be raised. Instead of injecting the resin in step S060, the resin may be injected each time the substrates are overlaid in step S040. By injecting the resin, the strength of the laminated semiconductor device can be reinforced. By injecting the insulating resin, unexpected electrical conduction between the substrates can be prevented. Instead of injecting resin or the like, the bonding strength may be secured by an intermolecular force between the substrate 300 and the substrate 200 or the like.

さらに、積層基板３４０を電子回路毎に個片化する（Ｓ０７０）。ステップＳ０７０において、ダイシング等により積層基板３４０をチップごとに個片化して、パッケージする。これにより、積層半導体装置が製造される。   Further, the multilayer substrate 340 is separated into pieces for each electronic circuit (S070). In step S070, the laminated substrate 340 is separated into individual chips by dicing or the like and packaged. Thereby, a laminated semiconductor device is manufactured.

ここで、図３に示すように、電極１１２は基板１００の表面より高く設けられている。よって、図１２に示すように、電極１１２は、その高くなった部分により導通路３３２に接続できるだけでなく、無電解メッキの過程において、貫通孔２０２の周囲を囲う堰部を形成する。これにより、基板の間の間隙３２４に不必要にメッキ層が広がることを防ぐこともできる。   Here, as shown in FIG. 3, the electrode 112 is provided higher than the surface of the substrate 100. Therefore, as shown in FIG. 12, the electrode 112 not only can be connected to the conduction path 332 by the raised portion, but also forms a weir portion surrounding the through hole 202 in the electroless plating process. This can also prevent the plating layer from unnecessarily spreading in the gap 324 between the substrates.

上記の実施形態において、基板の凹部を貫通孔に加工するステップＳ０３０が、複数の基板を重ね合わせるステップＳ０４０の前にある例を挙げたが、当該ステップＳ０３０は、ステップＳ０４０の後であってもよい。例えば、基板１４０の表面（図７）と基板３００（図４）の表面とを重ね合わせて、即ち、基板１４０における凹部１３０の開口部を基板３００の金属層３１４に位置合わせして重ね合わせてから、グラインド、ＣＭＰ等の方法により基板１４０の裏面から薄化して、凹部１３０を貫通孔２０２に加工することもできる。   In the above embodiment, the example in which the step S030 for processing the concave portion of the substrate into the through-hole is provided before the step S040 in which the plurality of substrates are overlapped, but the step S030 is performed even after the step S040. Good. For example, the surface of the substrate 140 (FIG. 7) and the surface of the substrate 300 (FIG. 4) are overlapped, that is, the opening of the recess 130 in the substrate 140 is aligned with the metal layer 314 of the substrate 300 and overlapped. Therefore, the recess 130 can be processed into the through hole 202 by thinning the back surface of the substrate 140 by a method such as grinding or CMP.

ステップＳ０２０において、一気に基板１００を貫通する貫通孔２０２を形成してもよい。更に貫通孔２０２を形成した後、グラインド、ＣＭＰ等の方法により基板１００を薄化してもよい。また、基板１００の薄化後に貫通孔２０２を形成してもよい。更に薄化加工は複数の基板を重ね合わせるステップＳ０４０前にしてもよくその後にしてもよい。   In step S020, a through hole 202 that penetrates the substrate 100 may be formed at once. Further, after forming the through hole 202, the substrate 100 may be thinned by a method such as grinding or CMP. Further, the through hole 202 may be formed after the substrate 100 is thinned. Further, the thinning process may be performed before or after step S040 in which a plurality of substrates are overlapped.

ステップＳ０４０において、基板２００、基板２１０及び基板２２０の貫通孔２０２は互いが完全に重なっていなくてもよく、部分的に重なってもよい。ステップＳ０５０において、重ね合せられた基板の間に十分に電気的な導通が確保できる導通路３３２が形成できる程度の重なりがあればよい。この場合には、基板２００、２１０、２２０の貫通孔２０２の位置を完全に合わせるのに要する時間を短縮することができる。   In step S040, the through holes 202 of the substrate 200, the substrate 210, and the substrate 220 may not overlap each other completely, or may partially overlap each other. In step S050, it is sufficient that there is an overlap enough to form a conduction path 332 that can sufficiently ensure electrical conduction between the stacked substrates. In this case, the time required to completely align the positions of the through holes 202 of the substrates 200, 210, and 220 can be shortened.

上記実施形態では、ステップＳ０４０において、基板３００に貼り合せる予定の基板２００、基板２１０及び基板２２０を全て重ね合わせてから、電気的な導通路３３２を形成するステップＳ０５０において、一気に導通路３３２を形成する例を挙げた。これに代えて、ステップＳ０４０及びステップＳ０５０を順に繰り返すことにより、導通路３３２を形成してもよい。   In the above embodiment, in step S040, all of the substrate 200, the substrate 210, and the substrate 220 that are to be bonded to the substrate 300 are overlapped, and then the electrical conduction path 332 is formed. In step S050, the conduction path 332 is formed all at once. An example was given. Instead, the conduction path 332 may be formed by repeating step S040 and step S050 in order.

図１３から図１５は、ステップＳ０４０及びステップＳ０５０を順に繰り返すことにより、導通路を形成する方法を示す概略断面図である。まず図１３に示すように、複数の基板を重ね合わせるステップＳ０４０において基板３５０に基板２３０を重ね合わせてから、電気的な導通路を形成するステップＳ０５０において、まず基板２３０の貫通孔２３２に導通路３３４を形成する。次に、図１４に示すように、基板２００を重ね合わせて、基板２００の貫通孔２０２に導通路３３６を形成する。更に、図１５に示すように、基板２４０を重ね合わせて、基板２４０の貫通孔２４２に導通路３３８を形成して、積層基板３６０が得られる。   FIGS. 13 to 15 are schematic cross-sectional views showing a method of forming a conduction path by repeating step S040 and step S050 in order. First, as shown in FIG. 13, in step S040 in which a plurality of substrates are overlapped, the substrate 230 is overlapped on the substrate 350, and then in step S050 in which an electrical conduction path is formed, first, the conduction path is formed in the through hole 232 of the substrate 230. 334 is formed. Next, as shown in FIG. 14, the conductive paths 336 are formed in the through holes 202 of the substrate 200 by overlapping the substrates 200. Further, as shown in FIG. 15, the substrate 240 is overlapped, and a conduction path 338 is formed in the through hole 242 of the substrate 240, so that a laminated substrate 360 is obtained.

基板２３０及び基板２４０は、前述の基板２００の製造方法により製造してよい。基板３５０は、前述の基板３００の製造方法により製造してよい。このようにステップＳ０４０及びステップＳ０５０を順に繰り返すことにより導通路を形成すると、基板３５０に基板を一枚重ね合わせる都度に導通路を形成するので、上下の基板の貫通孔がすべて繋がらなくてもよい。よって、積層半導体装置の設計の自由度が高くなる。   The substrate 230 and the substrate 240 may be manufactured by the method for manufacturing the substrate 200 described above. The substrate 350 may be manufactured by the method for manufacturing the substrate 300 described above. When the conductive path is formed by repeating step S040 and step S050 in this manner, the conductive path is formed each time one substrate is superposed on the substrate 350, so that all the through holes of the upper and lower substrates do not have to be connected. . Therefore, the degree of freedom in designing the stacked semiconductor device is increased.

図１６から図２４を用いて、バリアメタル層を形成する方法を示す概略断面図である。上述の実施形態において、基板に凹部を形成するステップＳ０２０と複数の基板を重ね合わせるステップＳ０４０との間に、バリアメタル層を形成するステップを更に備えてよい。   It is a schematic sectional drawing which shows the method of forming a barrier metal layer using FIGS. 16-24. In the above-described embodiment, a step of forming a barrier metal layer may be further provided between step S020 for forming a recess in the substrate and step S040 for overlapping a plurality of substrates.

この場合にまず、図１６に示すように、ステップＳ０１０において、回路が形成された基板４００を準備する。図１６は、基板４００を概念的に示す断面図である。基板４００は、ウェハ４０２と、電子素子４０４と、プラグ４０６と、配線４０８と、電極４１２と、絶縁層４１４とを含む。ウェハ４０２、電子素子４０４、プラグ４０６、配線４０８、電極４１２及び絶縁層４１４は、それぞれ基板１００のウェハ１０２、電子素子１０４、プラグ１０６、配線１０８、電極１１２および絶縁層１１４と同一の構成および作用を有するので、説明を省略する。   In this case, first, as shown in FIG. 16, in step S010, a substrate 400 on which a circuit is formed is prepared. FIG. 16 is a sectional view conceptually showing the substrate 400. The substrate 400 includes a wafer 402, an electronic element 404, a plug 406, a wiring 408, an electrode 412, and an insulating layer 414. The wafer 402, the electronic element 404, the plug 406, the wiring 408, the electrode 412 and the insulating layer 414 have the same configuration and operation as the wafer 102, the electronic element 104, the plug 106, the wiring 108, the electrode 112 and the insulating layer 114 of the substrate 100, respectively. Description is omitted.

図１７に示すように、ステップＳ０２０において、リソグラフィにより、凹部４２０が形成される位置に開口が設けられたレジストパターン４１６を基板４００の表面に形成する。その後選択エッチング等により凹部４２０を形成する。更に、図１８に示すように、凹部４２０の表面に絶縁膜４２２を成膜して、凹部４３０を有する基板４４０を形成する。絶縁膜４２２の形成は、図６と図７において説明した方法により形成できる。   As shown in FIG. 17, in step S020, a resist pattern 416 having an opening at a position where the concave portion 420 is formed is formed on the surface of the substrate 400 by lithography. Thereafter, a recess 420 is formed by selective etching or the like. Further, as shown in FIG. 18, an insulating film 422 is formed on the surface of the recess 420 to form a substrate 440 having the recess 430. The insulating film 422 can be formed by the method described with reference to FIGS.

次に、図１９に示すように、基板４４０の表面（図１９においては上の面）にバリアメタル層４４２を生成する。バリアメタル層４４２は、後続ステップにおいて形成される導通路の金属が絶縁膜４２２及び基板４４０に拡散して、基板４４０の電気的特性を劣化させることを防ぐことができる。バリアメタル層４４２の材料としては、ＴｉＮ、ＴａＮ等が例示できる。バリアメタル層４４２は、スパッタ、ＣＶＤ等の方法により形成できる。   Next, as shown in FIG. 19, a barrier metal layer 442 is formed on the surface of the substrate 440 (the upper surface in FIG. 19). The barrier metal layer 442 can prevent a conductive path metal formed in a subsequent step from diffusing into the insulating film 422 and the substrate 440 and deteriorating the electrical characteristics of the substrate 440. Examples of the material of the barrier metal layer 442 include TiN and TaN. The barrier metal layer 442 can be formed by a method such as sputtering or CVD.

さらに、図２０に示すように、リソグラフィによりレジストパターン４５２を生成し、図２１に示すように、エッチング等の方法により不要のバリアメタル層４４２を除去する。これにより、基板４６０が得られる。残されたバリアメタル層４４２は、基板４６０の表面にある電極４６２と凹部４５０の表面にあるバリアメタル４６４に分けられる。バリアメタル４６４は、上述のように、後続ステップにおいて形成される導通路金属の拡散を抑制するバリアメタルの役割を果たす。一方、電極４６２は、電極４１２と繋いで他の基板と電気的に接続する電極の役割を果たす。   Further, a resist pattern 452 is generated by lithography as shown in FIG. 20, and an unnecessary barrier metal layer 442 is removed by a method such as etching as shown in FIG. Thereby, the substrate 460 is obtained. The remaining barrier metal layer 442 is divided into an electrode 462 on the surface of the substrate 460 and a barrier metal 464 on the surface of the recess 450. As described above, the barrier metal 464 serves as a barrier metal that suppresses diffusion of the conductive path metal formed in the subsequent step. On the other hand, the electrode 462 serves as an electrode that is connected to the electrode 412 and electrically connected to another substrate.

図２２に示すように、ステップＳ０３０において、基板４６０の表面に支持基板４７０を貼り合せてから、グラインド、ＣＭＰ等の方法により、基板４６０を裏面から薄化して、凹部４５０を貫通孔５０２に加工して、基板５００を形成する。   As shown in FIG. 22, in step S 030, a support substrate 470 is bonded to the surface of the substrate 460, and then the substrate 460 is thinned from the back surface by a method such as grinding or CMP, and the recess 450 is processed into the through hole 502. Then, the substrate 500 is formed.

図２３に示すように、ステップＳ０４０において、基板３００に順次基板５００、基板５１０及び基板５２０を重ね合わせる。図２４に示すように、ステップＳ０５０において、貫通孔５０２に導電性材料を導入することにより、導通路５５０を形成する。以上のステップにより、積層基板５６０が形成できる。更に、基板の間の間隙に樹脂を注入して（Ｓ０６０）、積層基板５６０を個片化して（Ｓ０７０）、パッケージすることで積層半導体装置を得ることができる。   As shown in FIG. 23, the substrate 500, the substrate 510, and the substrate 520 are sequentially overlaid on the substrate 300 in step S040. As shown in FIG. 24, in step S050, a conductive path 550 is formed by introducing a conductive material into the through hole 502. Through the above steps, the multilayer substrate 560 can be formed. Further, by injecting a resin into the gap between the substrates (S060), the laminated substrate 560 is separated into pieces (S070), and packaged to obtain a laminated semiconductor device.

図２５から図３３は、積層半導体装置を製造する半導体装置製造方法の他の実施形態を示す。この実施形態は、基本的に図１のフローチャートに示した各ステップにより実施できるが、基板凹部を貫通孔に加工するステップＳ０３０が不要である。以下、図面を用いてこの半導体装置製造方法の実施形態を説明する。この場合に、まず、ステップＳ０１０において、図２５および図２６に示す基板６００及び基板７００が準備される。   25 to 33 show another embodiment of a semiconductor device manufacturing method for manufacturing a stacked semiconductor device. Although this embodiment can be basically implemented by the steps shown in the flowchart of FIG. 1, step S030 for processing the substrate recess into the through hole is unnecessary. Hereinafter, embodiments of the semiconductor device manufacturing method will be described with reference to the drawings. In this case, first, in step S010, the substrate 600 and the substrate 700 shown in FIGS. 25 and 26 are prepared.

図２５に示すように、基板６００は、ウェハ６０２と、回路６１０を含む。回路６１０は、電子素子６０４と、プラグ６０６と、配線６０８と、電極６１２と、金属層６１４と、絶縁膜６１６と、絶縁層６１８とを含む。ウェハ６０２、電子素子６０４、プラグ６０６、配線６０８、電極６１２、金属層６１４、絶縁膜６１６及び絶縁層６１８は、それぞれウェハ３０２、電子素子３０４、プラグ３０６、配線３０８、電極３１２、金属層３１４、絶縁膜３１６及び絶縁層３１８と同一の構成および作用を有するので説明を省略する。   As shown in FIG. 25, the substrate 600 includes a wafer 602 and a circuit 610. The circuit 610 includes an electronic element 604, a plug 606, a wiring 608, an electrode 612, a metal layer 614, an insulating film 616, and an insulating layer 618. The wafer 602, the electronic element 604, the plug 606, the wiring 608, the electrode 612, the metal layer 614, the insulating film 616, and the insulating layer 618 are respectively the wafer 302, the electronic element 304, the plug 306, the wiring 308, the electrode 312, the metal layer 314, Since the insulating film 316 and the insulating layer 318 have the same configuration and function, description thereof is omitted.

図２６に示すように、基板７００は、ウェハ７０２と、回路７１０を含む。回路７１０は、電子素子７０４と、プラグ７０６と、配線７０８と、電極７１２と、絶縁層７１４と、レジストパターン７１６とを含む。ウェハ７０２、電子素子７０４、プラグ７０６、配線７０８、電極７１２及び絶縁層７１４は、それぞれウェハ１０２、電子素子１０４、プラグ１０６、配線１０８、電極１１２及び絶縁層１１４と同一の構成及び作用を有するので、説明を省略する。レジストパターン７１６は、電極７１２を形成する段階で設けられるが、後続のプロセスにおいて基板７００を補強する効果もたせるべく、残してよい。   As shown in FIG. 26, the substrate 700 includes a wafer 702 and a circuit 710. The circuit 710 includes an electronic element 704, a plug 706, a wiring 708, an electrode 712, an insulating layer 714, and a resist pattern 716. Since the wafer 702, the electronic element 704, the plug 706, the wiring 708, the electrode 712, and the insulating layer 714 have the same configuration and function as the wafer 102, the electronic element 104, the plug 106, the wiring 108, the electrode 112, and the insulating layer 114, respectively. The description is omitted. The resist pattern 716 is provided in the step of forming the electrode 712, but may be left to have an effect of reinforcing the substrate 700 in a subsequent process.

図２７に示すように、ステップＳ０２０において、基板７００の表面に支持基板７２０が貼り合わされる。支持基板７２０は、前述の支持基板１５０と同じく、後続の基板７００の薄化プロセスにおいて、基板７００が破壊しないように基板７００を補強する。支持基板７２０は、支持基板１５０と同じ材料の基板であってよく、同じ方法により基板７００に貼付されて良い。   As shown in FIG. 27, in step S020, a support substrate 720 is bonded to the surface of the substrate 700. The support substrate 720 reinforces the substrate 700 so that the substrate 700 is not destroyed in the subsequent thinning process of the substrate 700, like the support substrate 150 described above. The support substrate 720 may be a substrate of the same material as the support substrate 150 and may be attached to the substrate 700 by the same method.

図２８に示すように、ＣＭＰ等の方法により、基板７００が裏面から薄化される。例えば、厚さ７７５μｍ（または７０５μｍ）から厚さ５０μｍに加工する。薄化後、基板７００の裏面から電極７１２まで届く凹部７３２を形成する。凹部７３２は、リソグラフィにより薄化された基板７００の裏面に、凹部７３２が形成される位置に開口が設けられたレジストパターンを設けてから、選択エッチング等により形成できる。以上のプロセスにより、薄化されて且つ凹部７３２を有する基板７３０が得られる。図１から図２４に示す実施形態と異なり、本実施形態において、凹部７３２が基板７３０の裏面に形成され、且つ、凹部７３２は基板７３０を貫通しない。   As shown in FIG. 28, the substrate 700 is thinned from the back surface by a method such as CMP. For example, the thickness is processed from 775 μm (or 705 μm) to 50 μm. After the thinning, a recess 732 reaching the electrode 712 from the back surface of the substrate 700 is formed. The concave portion 732 can be formed by selective etching or the like after providing a resist pattern having an opening at a position where the concave portion 732 is formed on the back surface of the substrate 700 thinned by lithography. Through the above process, the substrate 730 which is thinned and has the recess 732 is obtained. Unlike the embodiment shown in FIGS. 1 to 24, in this embodiment, the recess 732 is formed on the back surface of the substrate 730, and the recess 732 does not penetrate the substrate 730.

図２９に示すように、凹部７３２の周辺に絶縁膜７４２が成膜される。絶縁膜７４２は、図６及び図７に示す絶縁膜１２２に対応し、絶縁膜１２２と同じ材料を用いて、同じ方法により形成することができる。例えば、絶縁膜１２２と同様に、スパッタ、ＣＶＤ又は熱酸化等の方法により、絶縁膜７４２を形成する。高温プロセスにより絶縁膜７４２を形成する場合には、事前にレジストパターン７１６を除去する。   As shown in FIG. 29, an insulating film 742 is formed around the recess 732. The insulating film 742 corresponds to the insulating film 122 illustrated in FIGS. 6 and 7 and can be formed using the same material and the same method as the insulating film 122. For example, as with the insulating film 122, the insulating film 742 is formed by a method such as sputtering, CVD, or thermal oxidation. In the case where the insulating film 742 is formed by a high temperature process, the resist pattern 716 is removed in advance.

リソグラフィ及びエッチングにより、電極７１２と接する凹部の上の部分の絶縁膜７４２を除去して、周辺だけが絶縁膜７４２により覆われる凹部７４４が形成される。これにより、基板７４０が得られる。   By removing the insulating film 742 over the concave portion in contact with the electrode 712 by lithography and etching, a concave portion 744 in which only the periphery is covered with the insulating film 742 is formed. Thereby, the substrate 740 is obtained.

図３０に示すように、ステップＳ０４０において、基板６００に基板７４０が重ね合わされる。基板６００は、製造する積層半導体装置の全体の強度を確保する基板として、基板７４０のように薄化されない。図１０に示した場合と異なり、本実施形態では、重ね合わせにより、金属層６１４が凹部７４４を完全に塞がず、一定の隙間７４６を残すことが特徴である。重ね合わせは、別途設けられるアライナーにより、基板６００と基板７４０を精密に位置合せしてから行われる。さらに、基板６００と基板７４０を一定の温度に加熱して接合してもよく、一定の圧力に加圧して接合してもよく、又は加熱及び加圧して接合してもよい。   As shown in FIG. 30, in step S <b> 040, the substrate 740 is overlaid on the substrate 600. The substrate 600 is not thinned like the substrate 740 as a substrate for ensuring the strength of the entire laminated semiconductor device to be manufactured. Unlike the case shown in FIG. 10, the present embodiment is characterized in that the metal layer 614 does not completely block the concave portion 744 and leaves a certain gap 746 due to superposition. The superposition is performed after the substrate 600 and the substrate 740 are accurately aligned by an aligner provided separately. Further, the substrate 600 and the substrate 740 may be bonded by heating to a certain temperature, may be bonded by pressing to a certain pressure, or may be bonded by heating and pressing.

図３１に示すように、ステップＳ０５０において、隙間７４６から凹部７４４に導電性材料を導入することにより、導通路７４８が形成される。導通路７４８は、基板６００及び基板７４０の電子回路の間の電気的な導通を形成する。   As shown in FIG. 31, in step S050, a conductive path 748 is formed by introducing a conductive material from the gap 746 into the recess 744. The conduction path 748 forms electrical conduction between the electronic circuit of the substrate 600 and the substrate 740.

導通路７４８の材料として、Ｃｕ、Ａｕ、Ａｇ、Ａｌ又はＷ等が例示できる。導通路７４８は、メッキ、ＣＶＤ等の方法により形成することができる。例えば、無電解メッキ法によりＣｕの導通路７４８を形成する。また、図３０に示す支持基板７２０が導電材料であれば、支持基板７２０を通じて電極７１２を陰極に接続して、電解メッキ法を用いても導通路７４８を形成することができる。導通路７４８を形成した後、支持基板７２０とレジストパターン７１６を除去する。なお、凹部７４４は絶縁膜７４２に覆われているので、導通路７４８から基板７４０へのリーク電流が抑制される。   Examples of the material of the conduction path 748 include Cu, Au, Ag, Al, or W. The conduction path 748 can be formed by a method such as plating or CVD. For example, the Cu conduction path 748 is formed by electroless plating. In addition, when the support substrate 720 illustrated in FIG. 30 is a conductive material, the conductive path 748 can be formed even when the electrode 712 is connected to the cathode through the support substrate 720 and an electrolytic plating method is used. After the conductive path 748 is formed, the support substrate 720 and the resist pattern 716 are removed. Note that since the recess 744 is covered with the insulating film 742, leakage current from the conduction path 748 to the substrate 740 is suppressed.

図３２に示すように、基板７４０の上にさらに、基板７５０を重ね合わせる。基板７５０は、上述した基板７４０を形成する方法により用意することができる。ここでも、後続のプロセスで導通路を形成する目的に、凹部７５２と電極７１２との間に隙間７５４を残す。   As shown in FIG. 32, a substrate 750 is further superimposed on the substrate 740. The substrate 750 can be prepared by the method for forming the substrate 740 described above. Again, a gap 754 is left between the recess 752 and the electrode 712 for the purpose of forming a conduction path in a subsequent process.

図３３に示すように、無電解メッキ又は電解メッキにより凹部７５２に導通路７６２を形成する。レジストパターン７５６と支持基板７５８を除去すると、積層基板８００が得られる。目的に応じて、複数の基板を重ね合わせるステップＳ０４０と電気的な導通路を形成するステップＳ０５０を繰り返すことにより、更に多くの基板を積層することができる。なお、基板の間の間隙に樹脂を注入して（Ｓ０６０）、積層基板８００を個片化して（Ｓ０７０）、パッケージすることで積層半導体装置が得られる。   As shown in FIG. 33, a conductive path 762 is formed in the recess 752 by electroless plating or electrolytic plating. When the resist pattern 756 and the support substrate 758 are removed, the multilayer substrate 800 is obtained. By repeating step S040 for stacking a plurality of substrates and step S050 for forming an electrical conduction path, more substrates can be stacked depending on the purpose. A laminated semiconductor device is obtained by injecting resin into the gap between the substrates (S060), separating the laminated substrate 800 into pieces (S070), and packaging.

上述の実施形態において、支持基板１５０、４７０、７２０、７５８は、弾性材料で形成されてもよい。この場合には、支持基板１５０等が基板２００等を支持する場合に、基板２００等に発生したひずみが是正できる方向に当該弾性材料に一定の弾性変形を与えながら基板２００等と支持基板１５０等と貼り合せることにより、その弾性変形の回復により、基板２００等のひずみを直すことができる。   In the above-described embodiment, the support substrates 150, 470, 720, and 758 may be formed of an elastic material. In this case, when the support substrate 150 or the like supports the substrate 200 or the like, the substrate 200 or the like and the support substrate 150 or the like while giving a certain elastic deformation to the elastic material in a direction in which the distortion generated in the substrate 200 or the like can be corrected. And the distortion of the substrate 200 or the like can be corrected by recovery of the elastic deformation.

上述の実施形態により説明した積層半導体装置の製造方法は、回路が形成された基板を貼り合せるためのバンプが不要であり、バンプ形成のプロセスを省くことができる。また、複数の基板を貼り合わせた後に、複数の基板を貫通するビアホールを形成して、導通路を設ける方法に比して、上述の実施形態においては、基板を重ね合わせる前に、各基板に凹部又は貫通孔を形成するので、凹部又は貫通孔の形成が容易である。   The method for manufacturing a laminated semiconductor device described in the above embodiment does not require a bump for bonding a substrate on which a circuit is formed, and can omit the bump formation process. In addition, in the above-described embodiment, before the substrates are overlaid, the via holes penetrating the plurality of substrates are formed after the plurality of substrates are bonded to each other. Since the recess or the through hole is formed, the formation of the recess or the through hole is easy.

以上、本発明を実施の形態を用いて説明したが、本発明の技術的範囲は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変更または改良を加えることが可能であることが当業者に明らかである。その様な変更または改良を加えた形態も本発明の技術的範囲に含まれ得ることが、特許請求の範囲の記載から明らかである。   As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

特許請求の範囲、明細書、および図面中において示した装置、システム、プログラム、および方法における動作、手順、ステップ、および段階等の各処理の実行順序は、特段「より前に」、「先立って」等と明示しておらず、また、前の処理の出力を後の処理で用いるのでない限り、任意の順序で実現しうることに留意すべきである。特許請求の範囲、明細書、および図面中の動作フローに関して、便宜上「まず、」、「次に、」等を用いて説明したとしても、この順で実施することが必須であることを意味するものではない。   The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

１００ 基板、１０２ ウェハ、１０４ 電子素子、１０６ プラグ、１０８ 配線、１１０ 回路、１１２ 電極、１１４ 絶縁層、１１６ レジストパターン、１２０ 凹部、１２２ 絶縁膜、１３０ 凹部、１４０ 基板、１５０ 支持基板、２００ 基板、２０２ 貫通孔、２１０ 基板、２２０ 基板、２３０ 基板、２３２ 貫通孔、２４０ 基板、２４２ 貫通孔、３００ 基板、３０２ ウェハ、３０４ 電子素子、３０６ プラグ、３０８ 配線、３１０ 回路、３１２ 電極、３１４ 金属層、３１６ 絶縁膜、３１８ 絶縁層、３２２ 間隙、３２４ 間隙、３３２ 導通路、３３４ 導通路、３３６ 導通路、３３８ 導通路、３４０ 積層基板、３５０ 基板、３６０ 積層基板、４００ 基板、４０２ ウェハ、４０４ 電子素子、４０６ プラグ、４０８ 配線、４１２ 電極、４１４ 絶縁層、４１６ レジストパターン、４２０ 凹部、４２２ 絶縁膜、４３０ 凹部、４４０ 基板、４４２ バリアメタル層、４５０ 凹部、４５２ レジストパターン、４６０ 基板、４６２ 電極、４６４ バリアメタル、４７０ 支持基板、５００ 基板、５０２ 貫通孔、５１０ 基板、５２０ 基板、５５０ 導通路、５６０ 積層基板、６００ 基板、６０２ ウェハ、６０４ 電子素子、６０６ プラグ、６０８ 配線、６１０ 回路、６１２ 電極、６１４ 金属層、６１６ 絶縁膜、６１８ 絶縁層、７００ 基板、７０２ ウェハ、７０４ 電子素子、７０６ プラグ、７０８ 配線、７１０ 回路、７１２ 電極、７１４ 絶縁層、７１６ レジストパターン、７２０ 支持基板、７３０ 基板、７３２ 凹部、７４０ 基板、７４２ 絶縁膜、７４４ 凹部、７４６ 隙間、７４８ 導通路、７５０ 基板、７５２ 凹部、７５４ 隙間、７５６ レジストパターン、７５８ 支持基板、７６２ 導通路、８００ 積層基板   100 substrate, 102 wafer, 104 electronic element, 106 plug, 108 wiring, 110 circuit, 112 electrode, 114 insulating layer, 116 resist pattern, 120 recess, 122 insulating film, 130 recess, 140 substrate, 150 support substrate, 200 substrate, 202 Through-hole, 210 Substrate, 220 Substrate, 230 Substrate, 232 Through-hole, 240 Substrate, 242 Through-hole, 300 Substrate, 302 Wafer, 304 Electronic element, 306 Plug, 308 Wiring, 310 Circuit, 312 Electrode, 314 Metal layer, 316 insulating film, 318 insulating layer, 322 gap, 324 gap, 332 conduction path, 334 conduction path, 336 conduction path, 338 conduction path, 340 laminated substrate, 350 substrate, 360 laminated substrate, 400 substrate, 402 wafer, 404 electronic element 406 408 wiring, 412 electrode, 414 insulating layer, 416 resist pattern, 420 recess, 422 insulating film, 430 recess, 440 substrate, 442 barrier metal layer, 450 recess, 452 resist pattern, 460 substrate, 462 electrode, 464 barrier metal 470 Support substrate, 500 substrate, 502 through-hole, 510 substrate, 520 substrate, 550 conduction path, 560 laminated substrate, 600 substrate, 602 wafer, 604 electronic element, 606 plug, 608 wiring, 610 circuit, 612 electrode, 614 metal Layer, 616 insulating film, 618 insulating layer, 700 substrate, 702 wafer, 704 electronic device, 706 plug, 708 wiring, 710 circuit, 712 electrode, 714 insulating layer, 716 resist pattern, 720 support substrate, 730 substrate, 7 2 recesses, 740 substrate, 742 an insulating film, 744 recess, 746 gap, 748 conductive paths, 750 substrate, 752 recess, 754 gap, 756 resist pattern, 758 support substrate 762 conductive paths, 800 laminated substrate

Claims (17)

複数の基板を貼り合わせて積層半導体装置を製造する半導体装置製造方法であって、
回路が形成された前記複数の基板のうちの一の基板に凹部を形成する凹部形成ステップと、
前記一の基板を前記複数の基板のうちの他の基板に重ね合わせる重ね合わせステップと、
前記重ね合わせステップの後に、前記一の基板の前記凹部に導電性材料を導入することにより、前記一の基板の前記回路と前記他の基板の前記回路との間の電気的な導通路を形成する導通形成ステップと
を備える半導体装置製造方法。 A semiconductor device manufacturing method for manufacturing a laminated semiconductor device by bonding a plurality of substrates,
A recess forming step of forming a recess in one of the plurality of substrates on which a circuit is formed;
An overlaying step of superimposing the one substrate on another substrate of the plurality of substrates;
After the superposition step, an electrically conductive path is formed between the circuit of the one substrate and the circuit of the other substrate by introducing a conductive material into the recess of the one substrate. A semiconductor device manufacturing method comprising a conduction forming step. 前記導通形成ステップの前において、前記凹部を、前記一の基板を貫通する貫通孔に加工する貫通孔加工ステップをさらに備える請求項１に記載の半導体装置製造方法。   The semiconductor device manufacturing method according to claim 1, further comprising a through hole processing step of processing the concave portion into a through hole penetrating the one substrate before the conduction forming step. 前記凹部形成ステップは、前記一の基板を貫通しない前記凹部を形成し、
前記貫通孔加工ステップは、前記一の基板を薄化することにより前記凹部を前記貫通孔に加工する請求項２に記載の半導体装置製造方法。 The recess forming step forms the recess that does not penetrate the one substrate,
The semiconductor device manufacturing method according to claim 2, wherein in the through hole processing step, the concave portion is processed into the through hole by thinning the one substrate. 前記凹部形成ステップは、前記凹部として、前記一の基板を貫通する貫通孔を形成する請求項１に記載の半導体装置製造方法。   The semiconductor device manufacturing method according to claim 1, wherein the recess forming step forms a through hole penetrating the one substrate as the recess. 前記重ね合わせステップを繰り返すことにより複数の前記一の基板を前記他の基板に重ね合わせた後に、前記導通形成ステップにおいて、前記複数の一の基板の前記貫通孔に導電性材料を導入することにより、前記複数の一の基板の前記回路および前記他の基板の前記回路との間の電気的な導通路を形成する請求項２から４のいずれかに記載の半導体装置製造方法。   After superposing the plurality of one substrates on the other substrate by repeating the superposition step, in the conduction forming step, by introducing a conductive material into the through holes of the plurality of one substrates. 5. The method of manufacturing a semiconductor device according to claim 2, wherein an electrical conduction path is formed between the circuit of the plurality of one substrate and the circuit of the other substrate. 前記重ね合わせステップにおいて、前記複数の一の基板の前記貫通孔が互いに少なくとも部分的に重なる請求項５に記載の半導体装置製造方法。   The semiconductor device manufacturing method according to claim 5, wherein, in the superimposing step, the through holes of the plurality of one substrates at least partially overlap each other. 前記重ね合わせステップおよび前記導通形成ステップを順に繰り返すことにより、前記複数の基板の前記回路の間の電気的な導通路を形成する請求項２から５のいずれかに記載の半導体装置製造方法。   The semiconductor device manufacturing method according to claim 2, wherein an electrical conduction path between the circuits of the plurality of substrates is formed by sequentially repeating the superposition step and the conduction formation step. 前記導通形成ステップにおいて、前記凹部は前記一の基板を貫通していない請求項１に記載の半導体装置製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein, in the conduction forming step, the concave portion does not penetrate the one substrate. 前記凹部形成ステップは、前記凹部における前記他の基板と接合されるのと反対側に露出する導電部を形成するステップを有する請求項８に記載の半導体装置製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the recess forming step includes a step of forming a conductive portion exposed on the opposite side of the recess from being bonded to the other substrate. 前記重ね合わせステップにおいて、前記他の基板と前記凹部とは隙間を有し、
前記導通形成ステップにおいて、前記隙間から前記導電性材料を導入する請求項８または９に記載の半導体装置製造方法。 In the overlapping step, the other substrate and the recess have a gap,
10. The method of manufacturing a semiconductor device according to claim 8, wherein the conductive material is introduced from the gap in the conduction forming step. 少なくとも前記一の基板を保持部材で保持する保持ステップをさらに備える請求項１から１０のいずれかに記載の半導体装置製造方法。   The semiconductor device manufacturing method according to claim 1, further comprising a holding step of holding at least the one substrate with a holding member. 前記保持部材は弾性を有し、
前記保持ステップにおいて、前記保持部材により前記一の基板のひずみを直して保持する請求項１１に記載の半導体装置製造方法。 The holding member has elasticity;
12. The method of manufacturing a semiconductor device according to claim 11, wherein in the holding step, the holding member fixes and holds the strain of the one substrate. 前記重ね合わせステップの前に、前記一の基板の表面における前記凹部の周囲を囲う堰部を形成する堰形成ステップをさらに備える請求項１から１２のいずれかに記載の半導体装置製造方法。   13. The method of manufacturing a semiconductor device according to claim 1, further comprising a dam forming step of forming a dam portion surrounding the periphery of the concave portion on the surface of the one substrate before the overlaying step. 前記重ね合わせステップの前に、前記一の基板において前記凹部と前記一の基板の表面とを電気的に接続する接続部を形成する接続形成ステップをさらに備える請求項１から１２のいずれかに記載の半導体装置製造方法。   The connection forming step of forming a connection portion that electrically connects the concave portion and the surface of the one substrate in the one substrate before the superposing step. Semiconductor device manufacturing method. 前記複数の基板の間に樹脂を注入する樹脂注入ステップをさらに備える請求項１から１４のいずれかに記載の半導体装置製造方法。   The semiconductor device manufacturing method according to claim 1, further comprising a resin injection step of injecting a resin between the plurality of substrates. 前記複数の基板を個片化する個片化ステップをさらに備える請求項１から１５のいずれかに記載の半導体装置製造方法。   The semiconductor device manufacturing method according to claim 1, further comprising an individualizing step for individualizing the plurality of substrates. 請求項１から１６のいずれかに記載の半導体装置製造方法で製造された積層半導体装置。   A laminated semiconductor device manufactured by the semiconductor device manufacturing method according to claim 1.
JP2010008444A 2010-01-18 2010-01-18 Semiconductor device manufacturing method and laminated semiconductor device Active JP5445159B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010008444A JP5445159B2 (en) 2010-01-18 2010-01-18 Semiconductor device manufacturing method and laminated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010008444A JP5445159B2 (en) 2010-01-18 2010-01-18 Semiconductor device manufacturing method and laminated semiconductor device

Publications (3)

Publication Number Publication Date
JP2011146655A true JP2011146655A (en) 2011-07-28
JP2011146655A5 JP2011146655A5 (en) 2013-03-28
JP5445159B2 JP5445159B2 (en) 2014-03-19

Family

ID=44461213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010008444A Active JP5445159B2 (en) 2010-01-18 2010-01-18 Semiconductor device manufacturing method and laminated semiconductor device

Country Status (1)

Country Link
JP (1) JP5445159B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015119110A (en) * 2013-12-19 2015-06-25 国立大学法人東京工業大学 Semiconductor device and manufacturing method of the same
US10229948B2 (en) 2012-09-28 2019-03-12 Canon Kabushiki Kaisha Semiconductor apparatus
WO2020035898A1 (en) * 2018-08-13 2020-02-20 ウルトラメモリ株式会社 Semiconductor module and method for producing same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6012262B2 (en) 2012-05-31 2016-10-25 キヤノン株式会社 Manufacturing method of semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213943A (en) * 1987-03-03 1988-09-06 Sharp Corp Three-dimensional semiconductor integrated circuit
JP2001060654A (en) * 1999-08-20 2001-03-06 Seiko Epson Corp Semiconductor device and manufacture thereof
JP2001094039A (en) * 1999-09-21 2001-04-06 Seiko Epson Corp Forming method of insulating film, connection method of semiconductor chip, manufacturing method of the semiconductor chip, semiconductor device, substrate for connection and electronic apparatus
JP2001177048A (en) * 1999-12-17 2001-06-29 Seiko Epson Corp Semiconductor device and method for manufacturing the same and electronics
JP2003203914A (en) * 2002-01-09 2003-07-18 Japan Science & Technology Corp Semiconductor integrated circuit device and manufacturing method therefor
JP2005197339A (en) * 2004-01-05 2005-07-21 Seiko Epson Corp Semiconductor device and manufacturing method therefor
JP2006287211A (en) * 2005-03-08 2006-10-19 Sharp Corp Semiconductor device, stacked semiconductor device and method of fabricating the devices
JP2008047895A (en) * 2006-08-01 2008-02-28 Qimonda Ag Electrical through contact

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213943A (en) * 1987-03-03 1988-09-06 Sharp Corp Three-dimensional semiconductor integrated circuit
JP2001060654A (en) * 1999-08-20 2001-03-06 Seiko Epson Corp Semiconductor device and manufacture thereof
JP2001094039A (en) * 1999-09-21 2001-04-06 Seiko Epson Corp Forming method of insulating film, connection method of semiconductor chip, manufacturing method of the semiconductor chip, semiconductor device, substrate for connection and electronic apparatus
JP2001177048A (en) * 1999-12-17 2001-06-29 Seiko Epson Corp Semiconductor device and method for manufacturing the same and electronics
JP2003203914A (en) * 2002-01-09 2003-07-18 Japan Science & Technology Corp Semiconductor integrated circuit device and manufacturing method therefor
JP2005197339A (en) * 2004-01-05 2005-07-21 Seiko Epson Corp Semiconductor device and manufacturing method therefor
JP2006287211A (en) * 2005-03-08 2006-10-19 Sharp Corp Semiconductor device, stacked semiconductor device and method of fabricating the devices
JP2008047895A (en) * 2006-08-01 2008-02-28 Qimonda Ag Electrical through contact

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10229948B2 (en) 2012-09-28 2019-03-12 Canon Kabushiki Kaisha Semiconductor apparatus
JP2015119110A (en) * 2013-12-19 2015-06-25 国立大学法人東京工業大学 Semiconductor device and manufacturing method of the same
WO2020035898A1 (en) * 2018-08-13 2020-02-20 ウルトラメモリ株式会社 Semiconductor module and method for producing same

Also Published As

Publication number Publication date
JP5445159B2 (en) 2014-03-19

Similar Documents

Publication Publication Date Title
JP4937842B2 (en) Semiconductor device and manufacturing method thereof
TWI392054B (en) Process for the collective fabrication of 3d electronic modules
JP6132769B2 (en) Semiconductor device
TWI397972B (en) Semiconductor device manufacturing method
US8362515B2 (en) Chip package and method for forming the same
JP2009071095A (en) Method of manufacturing semiconductor device
JP2010147281A (en) Semiconductor device and method of manufacturing the same
JP2011176003A (en) Semiconductor device, and production method thereof
TW200818443A (en) Semiconductor device and method for manufacturing the same
TW201250963A (en) Semiconductor device and method for manufacturing semiconductor device
TW200412214A (en) Semiconductor device and method of manufacturing the same
JP2011258687A (en) Semiconductor device and method of manufacturing the same
KR20130126979A (en) Method of manufacturing semiconductor device
TW201011872A (en) Package substrate having semiconductor component embedded therein and fabrication method thereof
JP2010074194A (en) Semiconductor device, and method of manufacturing the same
JP6380946B2 (en) Semiconductor device and manufacturing method of semiconductor device
TW200818358A (en) Manufacturing method of semiconductor device
JP5445159B2 (en) Semiconductor device manufacturing method and laminated semiconductor device
TWI266375B (en) Semiconductor device and manufacture method thereof
JP2011049303A (en) Electric component and method of manufacturing the same
JP6341554B2 (en) Manufacturing method of semiconductor device
JP2014082359A (en) Semiconductor substrate, semiconductor device, solid state image pickup device and semiconductor substrate manufacturing method
JP5682496B2 (en) Semiconductor device, multi-chip semiconductor device, device, and manufacturing method of semiconductor device
JP5171726B2 (en) Semiconductor device
JP2016129161A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130118

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130206

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130730

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130926

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131126

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131209

R150 Certificate of patent or registration of utility model

Ref document number: 5445159

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250