JP2001035994A5 - - Google Patents
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- JP2001035994A5 JP2001035994A5 JP1999201965A JP20196599A JP2001035994A5 JP 2001035994 A5 JP2001035994 A5 JP 2001035994A5 JP 1999201965 A JP1999201965 A JP 1999201965A JP 20196599 A JP20196599 A JP 20196599A JP 2001035994 A5 JP2001035994 A5 JP 2001035994A5
- Authority
- JP
- Japan
- Prior art keywords
- chip
- conductivity type
- printed wiring
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 19
- 239000000853 adhesive Substances 0.000 claims 6
- 230000001070 adhesive Effects 0.000 claims 6
- 239000000758 substrate Substances 0.000 claims 4
- 239000002344 surface layer Substances 0.000 claims 4
- 239000003990 capacitor Substances 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 230000003068 static Effects 0.000 claims 1
Claims (13)
前記2個のチップのそれぞれの裏面同士を接着した導電性接着剤
とを具備することを特徴とする半導体集積回路装置。A first well region of a second conductivity type, which is opposite to the first conductivity type, and is formed in a plurality of island shapes selectively on a surface layer portion of a semiconductor substrate of the first conductivity type, the first well region Two chips each including a second well region of a first conductivity type selectively formed in an island shape and a functional circuit formed at least in the second well region;
A semiconductor integrated circuit device comprising: a conductive adhesive that bonds the back surfaces of the two chips to each other.
前記2個のチップのそれぞれの裏面同士を接着した導電性接着剤
とを具備し、前記各チップ領域は、第1導電型の半導体基板の表層部に前記第1導電型とは逆導電型である第2導電型の第1のウエル領域が選択的に島状に複数形成され、前記第1のウエル領域中に第1導電型の第2のウエル領域が選択的に島状に形成され、少なくとも前記第2のウエル領域に機能回路が形成されていることを特徴とする半導体集積回路装置。Two chips in units of a plurality of adjacent chip regions through an inter-chip separation region;
A conductive adhesive that bonds the back surfaces of the two chips to each other, and each chip region has a conductivity type opposite to the first conductivity type on a surface layer portion of a first conductivity type semiconductor substrate. A plurality of first well regions of a certain second conductivity type are selectively formed in an island shape, and a second well region of the first conductivity type is selectively formed in an island shape in the first well region, A semiconductor integrated circuit device, wherein a functional circuit is formed at least in the second well region.
前記印刷配線部材は、前記チップがアセンブリされた面とは反対面側に外部端子が設けられており、
前記接着により積層されたチップ、印刷配線部材およびボンディングワイヤーは絶縁樹脂により封止されていることを特徴とする請求項3記載の半導体集積回路装置。In the chip laminated by the adhesion, the connection terminal on one side is connected and fixed on the printed wiring member by a flip chip method, and the connection terminal on the other side is connected to the connection terminal on the printed wiring member by a bonding wire. Connected to
The printed wiring member is provided with an external terminal on the side opposite to the surface on which the chip is assembled.
4. The semiconductor integrated circuit device according to claim 3 , wherein the chip, the printed wiring member, and the bonding wire laminated by the adhesion are sealed with an insulating resin.
前記第1および第2のチップのそれぞれの裏面同士を接着した導電性接着剤と、
前記接着により積層された第1のチップの片面側と前記第3のチップの片面側とをフリップチップ方式により接続固定したフリップチップ接続部と、
前記第3のチップの他面側がアセンブリされた印刷配線部材と、
前記印刷配線部材およびその上にアセンブリされた三層積層構造のチップを収容し、前記第2のチップの他面側および前記印刷配線部材上の接続端子に選択的かつ電気的に接続される複数の外部端子を有するパッケージ
とを具備することを特徴とする半導体集積回路装置。A first well region of a second conductivity type, which is a reverse conductivity type to the first conductivity type, which is selectively formed in an island shape on a surface layer portion of a semiconductor substrate of the first conductivity type, the first well region First, second, and second well regions having a first conductivity type second well region selectively formed in an island shape and at least one chip region including at least a functional circuit formed in the second well region A third chip;
A conductive adhesive that bonds the back surfaces of the first and second chips;
A flip chip connecting portion for connecting and fixing one side of the first chip and the one side of the third chip laminated by the bonding by a flip chip method;
A printed wiring member assembled on the other side of the third chip;
A plurality of multi-layer stacked chips assembled on the printed wiring member and the printed wiring member are selectively and electrically connected to the other surface side of the second chip and connection terminals on the printed wiring member. A semiconductor integrated circuit device comprising: a package having a plurality of external terminals.
前記第1および第2のチップのそれぞれの裏面同士を接着する導電性接着剤と、A conductive adhesive for bonding the back surfaces of the first and second chips;
前記第1のチップの他面側と印刷配線部材とをフリップチップ方式により接続するフリップチップ接続部と、A flip chip connecting portion for connecting the other surface side of the first chip and the printed wiring member by a flip chip method;
前記第2のチップの他面側に搭載された少なくとも1つの電子部品と、At least one electronic component mounted on the other surface side of the second chip;
前記印刷配線部材およびその上にアセンブリされた前記第1、第2のチップおよび前記少なくとも1つの電子部品を収容し、複数の外部端子を有するパッケージA package having a plurality of external terminals that accommodates the printed wiring member, the first and second chips assembled thereon, and the at least one electronic component.
とを具備することを特徴とする半導体集積回路装置。A semiconductor integrated circuit device comprising:
前記複数個の半導体集積回路装置を片面側に実装した印刷配線基板
とを具備することを特徴とするシステム基板。A plurality of semiconductor integrated circuit devices according to any one of claims 1 to 11,
A printed circuit board on which the plurality of semiconductor integrated circuit devices are mounted on one side.
前記複数個の半導体集積回路装置を両面に実装した印刷配線基板
とを具備することを特徴とするシステム基板。A plurality of semiconductor integrated circuit devices according to any one of claims 1 to 11,
And a printed wiring board having the plurality of semiconductor integrated circuit devices mounted on both sides thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11201965A JP2001035994A (en) | 1999-07-15 | 1999-07-15 | Semiconductor integrated-circuit device and system substratte |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11201965A JP2001035994A (en) | 1999-07-15 | 1999-07-15 | Semiconductor integrated-circuit device and system substratte |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001035994A JP2001035994A (en) | 2001-02-09 |
JP2001035994A5 true JP2001035994A5 (en) | 2005-06-23 |
Family
ID=16449708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11201965A Pending JP2001035994A (en) | 1999-07-15 | 1999-07-15 | Semiconductor integrated-circuit device and system substratte |
Country Status (1)
Country | Link |
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JP (1) | JP2001035994A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004140037A (en) | 2002-10-15 | 2004-05-13 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing process |
JP4408832B2 (en) * | 2005-05-20 | 2010-02-03 | Necエレクトロニクス株式会社 | Semiconductor device |
JP2007188916A (en) | 2006-01-11 | 2007-07-26 | Renesas Technology Corp | Semiconductor device |
TWI390497B (en) * | 2008-06-20 | 2013-03-21 | Novatek Microelectronics Corp | Source driver and liquid crystal display |
JP2014082245A (en) | 2012-10-15 | 2014-05-08 | J Devices:Kk | Semiconductor storage device and method of manufacturing the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5737867A (en) * | 1980-08-18 | 1982-03-02 | Mitsubishi Electric Corp | Semiconductor device |
JPH05109978A (en) * | 1991-10-17 | 1993-04-30 | Fujitsu Ltd | Semiconductor device |
JPH07273275A (en) * | 1994-03-29 | 1995-10-20 | Toshiba Corp | Semiconductor device |
JPH09260441A (en) * | 1996-03-26 | 1997-10-03 | Mitsubishi Electric Corp | Semiconductor device |
JPH1070243A (en) * | 1996-05-30 | 1998-03-10 | Toshiba Corp | Semiconductor integrated circuit and method and apparatus for testing the same |
JPH10256483A (en) * | 1997-03-11 | 1998-09-25 | Toshiba Corp | Mos semiconductor integrated circuit |
JPH113969A (en) * | 1997-06-13 | 1999-01-06 | Matsushita Electric Ind Co Ltd | Substrate component laminated with chip component |
JP3111312B2 (en) * | 1997-10-29 | 2000-11-20 | ローム株式会社 | Semiconductor device |
JP3399808B2 (en) * | 1997-10-21 | 2003-04-21 | ローム株式会社 | How to assemble a multilayer chip |
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1999
- 1999-07-15 JP JP11201965A patent/JP2001035994A/en active Pending
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