JP2001035994A5 - - Google Patents

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JP2001035994A5
JP2001035994A5 JP1999201965A JP20196599A JP2001035994A5 JP 2001035994 A5 JP2001035994 A5 JP 2001035994A5 JP 1999201965 A JP1999201965 A JP 1999201965A JP 20196599 A JP20196599 A JP 20196599A JP 2001035994 A5 JP2001035994 A5 JP 2001035994A5
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chip
conductivity type
printed wiring
semiconductor integrated
integrated circuit
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JP1999201965A
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JP2001035994A (en
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Priority to JP11201965A priority Critical patent/JP2001035994A/en
Priority claimed from JP11201965A external-priority patent/JP2001035994A/en
Publication of JP2001035994A publication Critical patent/JP2001035994A/en
Publication of JP2001035994A5 publication Critical patent/JP2001035994A5/ja
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第１導電型の半導体基板の表層部に選択的に島状に複数形成された前記第１導電型とは逆導電型である第２導電型の第１のウエル領域、前記第１のウエル領域中に選択的に島状に形成された第１導電型の第２のウエル領域および少なくとも前記第２のウエル領域に形成された機能回路を含む２個のチップと、
前記２個のチップのそれぞれの裏面同士を接着した導電性接着剤
とを具備することを特徴とする半導体集積回路装置。A first well region of a second conductivity type, which is opposite to the first conductivity type, and is formed in a plurality of island shapes selectively on a surface layer portion of a semiconductor substrate of the first conductivity type, the first well region Two chips each including a second well region of a first conductivity type selectively formed in an island shape and a functional circuit formed at least in the second well region;
A semiconductor integrated circuit device comprising: a conductive adhesive that bonds the back surfaces of the two chips to each other. チップ間分離領域を介して隣接する複数のチップ領域を単位とする２個のチップと、
前記２個のチップのそれぞれの裏面同士を接着した導電性接着剤
とを具備し、前記各チップ領域は、第１導電型の半導体基板の表層部に前記第１導電型とは逆導電型である第２導電型の第１のウエル領域が選択的に島状に複数形成され、前記第１のウエル領域中に第１導電型の第２のウエル領域が選択的に島状に形成され、少なくとも前記第２のウエル領域に機能回路が形成されていることを特徴とする半導体集積回路装置。Two chips in units of a plurality of adjacent chip regions through an inter-chip separation region;
A conductive adhesive that bonds the back surfaces of the two chips to each other, and each chip region has a conductivity type opposite to the first conductivity type on a surface layer portion of a first conductivity type semiconductor substrate. A plurality of first well regions of a certain second conductivity type are selectively formed in an island shape, and a second well region of the first conductivity type is selectively formed in an island shape in the first well region, A semiconductor integrated circuit device, wherein a functional circuit is formed at least in the second well region. 前記接着により積層されたチップがアセンブリされる印刷配線部材をさらに有ることを特徴とする請求項１又は２記載の半導体集積回路装置。The semiconductor integrated circuit device according to claim 1 or 2, wherein the further certain printed wiring member chips Ru are assembled laminated by the adhesive. 前記接着により積層されたチップは、その片面側の接続端子は前記印刷配線部材上にフリップチップ方式により接続固定されており、その他面側の接続端子はボンディングワイヤーにより前記印刷配線部材上の接続端子に接続されており、
前記印刷配線部材は、前記チップがアセンブリされた面とは反対面側に外部端子が設けられており、
前記接着により積層されたチップ、印刷配線部材およびボンディングワイヤーは絶縁樹脂により封止されていることを特徴とする請求項３記載の半導体集積回路装置。In the chip laminated by the adhesion, the connection terminal on one side is connected and fixed on the printed wiring member by a flip chip method, and the connection terminal on the other side is connected to the connection terminal on the printed wiring member by a bonding wire. Connected to
The printed wiring member is provided with an external terminal on the side opposite to the surface on which the chip is assembled.
4. The semiconductor integrated circuit device according to claim 3 , wherein the chip, the printed wiring member, and the bonding wire laminated by the adhesion are sealed with an insulating resin. 前記印刷配線部材は前記接着により積層されたチップを１個搭載し、前記印刷配線部材のサイズは前記チップのサイズより若干大きめであり、チップサイズパッケージを有することを特徴とする請求項３又は４記載の半導体集積回路装置。The printed wiring member is mounted one the chips stacked by the adhesive, the size of the printed wiring member is slightly larger than the size of the chip, according to claim 3 or 4, characterized in that it has a chip size package The semiconductor integrated circuit device described. 前記印刷配線部材は、前記接着により積層されたチップを複数個搭載したことを特徴とする請求項３又は４記載の半導体集積回路装置。5. The semiconductor integrated circuit device according to claim 3 , wherein the printed wiring member includes a plurality of chips stacked by the adhesion. 第１導電型の半導体基板の表層部に選択的に島状に複数形成された前記第１導電型とは逆導電型である第２導電型の第１のウエル領域、前記第１のウエル領域中に選択的に島状に形成された第１導電型の第２のウエル領域および少なくとも前記第２のウエル領域に形成された機能回路を含むチップ領域を少なくとも１個有する第１、第２および第３のチップと、
前記第１および第２のチップのそれぞれの裏面同士を接着した導電性接着剤と、
前記接着により積層された第１のチップの片面側と前記第３のチップの片面側とをフリップチップ方式により接続固定したフリップチップ接続部と、
前記第３のチップの他面側がアセンブリされた印刷配線部材と、
前記印刷配線部材およびその上にアセンブリされた三層積層構造のチップを収容し、前記第２のチップの他面側および前記印刷配線部材上の接続端子に選択的かつ電気的に接続される複数の外部端子を有するパッケージ
とを具備することを特徴とする半導体集積回路装置。A first well region of a second conductivity type, which is a reverse conductivity type to the first conductivity type, which is selectively formed in an island shape on a surface layer portion of a semiconductor substrate of the first conductivity type, the first well region First, second, and second well regions having a first conductivity type second well region selectively formed in an island shape and at least one chip region including at least a functional circuit formed in the second well region A third chip;
A conductive adhesive that bonds the back surfaces of the first and second chips;
A flip chip connecting portion for connecting and fixing one side of the first chip and the one side of the third chip laminated by the bonding by a flip chip method;
A printed wiring member assembled on the other side of the third chip;
A plurality of multi-layer stacked chips assembled on the printed wiring member and the printed wiring member are selectively and electrically connected to the other surface side of the second chip and connection terminals on the printed wiring member. A semiconductor integrated circuit device comprising: a package having a plurality of external terminals. 第１導電型の半導体基板の表層部に選択的に島状に複数形成された前記第１導電型とは逆導電型である第２導電型の第１のウエル領域、前記第１のウエル領域中に選択的に島状に形成された第１導電型の第２のウエル領域および少なくとも前記第２のウエル領域に形成された機能回路を含むチップ領域を少なくとも１個有する第１および第２のチップと、A first well region of a second conductivity type, which is a reverse conductivity type to the first conductivity type, and is formed in a plurality of island shapes selectively on a surface layer portion of a semiconductor substrate of the first conductivity type, the first well region First and second having at least one chip region including a first conductivity type second well region selectively formed in an island shape and at least a functional circuit formed in the second well region Chips,
前記第１および第２のチップのそれぞれの裏面同士を接着する導電性接着剤と、A conductive adhesive for bonding the back surfaces of the first and second chips;
前記第１のチップの他面側と印刷配線部材とをフリップチップ方式により接続するフリップチップ接続部と、A flip chip connecting portion for connecting the other surface side of the first chip and the printed wiring member by a flip chip method;
前記第２のチップの他面側に搭載された少なくとも１つの電子部品と、At least one electronic component mounted on the other surface side of the second chip;
前記印刷配線部材およびその上にアセンブリされた前記第１、第２のチップおよび前記少なくとも１つの電子部品を収容し、複数の外部端子を有するパッケージA package having a plurality of external terminals that accommodates the printed wiring member, the first and second chips assembled thereon, and the at least one electronic component.
とを具備することを特徴とする半導体集積回路装置。A semiconductor integrated circuit device comprising: 前記少なくとも１つの電子部品は、コンデンサ、インダクタンス、抵抗、発振回路、デコーダ回路のいずれかであることを特徴とする請求項８記載の半導体集積回路装置。9. The semiconductor integrated circuit device according to claim 8, wherein the at least one electronic component is one of a capacitor, an inductance, a resistor, an oscillation circuit, and a decoder circuit. 前記複数の第１のウエル領域中にそれぞれ形成された機能回路は、不揮発性メモリ回路、アナログ回路、デジタル回路、デジタル／アナログ変換回路、スタティック型メモリ回路、ダイナミック型メモリ回路のうち、少なくとも２つを含むことを特徴とする請求項１乃至８のいずれか１項に記載の半導体集積回路装置。  The functional circuits formed in each of the plurality of first well regions are at least two of a nonvolatile memory circuit, an analog circuit, a digital circuit, a digital / analog conversion circuit, a static memory circuit, and a dynamic memory circuit. The semiconductor integrated circuit device according to claim 1, comprising: 前記複数の第１のウエル領域中にそれぞれ形成された機能回路は、全体としてメモリ回路を構成していることを特徴とする請求項１乃至８のいずれか１項に記載の半導体集積回路装置。  9. The semiconductor integrated circuit device according to claim 1, wherein each of the functional circuits formed in the plurality of first well regions constitutes a memory circuit as a whole. それぞれ請求項１乃至１１のいずれか１項に記載の複数個の半導体集積回路装置と、
前記複数個の半導体集積回路装置を片面側に実装した印刷配線基板
とを具備することを特徴とするシステム基板。A plurality of semiconductor integrated circuit devices according to any one of claims 1 to 11,
A printed circuit board on which the plurality of semiconductor integrated circuit devices are mounted on one side. それぞれ請求項１乃至１１のいずれか１項に記載の複数個の半導体集積回路装置と、
前記複数個の半導体集積回路装置を両面に実装した印刷配線基板
とを具備することを特徴とするシステム基板。A plurality of semiconductor integrated circuit devices according to any one of claims 1 to 11,
And a printed wiring board having the plurality of semiconductor integrated circuit devices mounted on both sides thereof.
JP11201965A 1999-07-15 1999-07-15 Semiconductor integrated-circuit device and system substratte Pending JP2001035994A (en)

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JP11201965A JP2001035994A (en) 1999-07-15 1999-07-15 Semiconductor integrated-circuit device and system substratte

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JP11201965A JP2001035994A (en) 1999-07-15 1999-07-15 Semiconductor integrated-circuit device and system substratte

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JP2001035994A JP2001035994A (en) 2001-02-09
JP2001035994A5 true JP2001035994A5 (en) 2005-06-23

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JP2004140037A (en) 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing process
JP4408832B2 (en) * 2005-05-20 2010-02-03 Ｎｅｃエレクトロニクス株式会社 Semiconductor device
JP2007188916A (en) 2006-01-11 2007-07-26 Renesas Technology Corp Semiconductor device
TWI390497B (en) * 2008-06-20 2013-03-21 Novatek Microelectronics Corp Source driver and liquid crystal display
JP2014082245A (en) 2012-10-15 2014-05-08 J Devices:Kk Semiconductor storage device and method of manufacturing the same

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JPS5737867A (en) * 1980-08-18 1982-03-02 Mitsubishi Electric Corp Semiconductor device
JPH05109978A (en) * 1991-10-17 1993-04-30 Fujitsu Ltd Semiconductor device
JPH07273275A (en) * 1994-03-29 1995-10-20 Toshiba Corp Semiconductor device
JPH09260441A (en) * 1996-03-26 1997-10-03 Mitsubishi Electric Corp Semiconductor device
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