JP2000332272A - Method of forming solar battery - Google Patents
Method of forming solar batteryInfo
- Publication number
- JP2000332272A JP2000332272A JP11143383A JP14338399A JP2000332272A JP 2000332272 A JP2000332272 A JP 2000332272A JP 11143383 A JP11143383 A JP 11143383A JP 14338399 A JP14338399 A JP 14338399A JP 2000332272 A JP2000332272 A JP 2000332272A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- electrode
- surface side
- main surface
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はシリコン等の半導体
基板を用いた太陽電池の形成法に関する。The present invention relates to a method for forming a solar cell using a semiconductor substrate such as silicon.
【０００２】[0002]
【従来の技術とその問題点】従来の太陽電池を図３に示
す。図３において、１は一導電型（例えばＰ型）を示す
半導体基板、１ａは半導体基板１の表面部分にリン原子
が高濃度に拡散された他の導電型を呈する領域、２は一
主面側の反射防止膜、３は半導体接合部、４は裏面電
極、５は表面電極である。表面電極５は反射防止膜２が
エッチングされ、もしくはその上から形成される。表面
電極５は、図示されていないが、反射防止膜２の表面に
沿ってバスバー部５ａが設けられると共に、このバスバ
ー部５ａと垂直にフィンガー部５ｂが設けられている。2. Description of the Related Art FIG. 3 shows a conventional solar cell. In FIG. 3, reference numeral 1 denotes a semiconductor substrate showing one conductivity type (for example, P type); 1a, a region exhibiting another conductivity type in which phosphorus atoms are diffused at a high concentration in a surface portion of the semiconductor substrate 1; 3 is a semiconductor junction, 4 is a back electrode, and 5 is a front electrode. The surface electrode 5 is formed by etching the antireflection film 2 or on the antireflection film 2. Although not shown, the surface electrode 5 is provided with a bus bar portion 5a along the surface of the antireflection film 2 and a finger portion 5b perpendicular to the bus bar portion 5a.
【０００３】この種太陽電池の電極パターンは配線抵抗
が極小になるように設計される。すなわち受光面は最大
になり、配線抵抗は最小になるように設計される。従来
の代表的な電極パターンを図４に示す。半田コートの
際、ディップ法では図４（ａ）の太陽電池ではバスバー
部５ａが半導体基板１の片側のみに設けられているの
で、半田膜が張らないように、このバスバー部５ａを下
方に向けて半田コートされる。噴流法でも同様な考え方
で膜が張らない方向に太陽電池が設置される。The electrode pattern of this type of solar cell is designed so that the wiring resistance is minimized. That is, the light receiving surface is designed to be maximum and the wiring resistance is to be minimum. FIG. 4 shows a conventional representative electrode pattern. At the time of solder coating, in the solar cell of FIG. 4A, the bus bar portion 5a is provided only on one side of the semiconductor substrate 1 in the dip method, so that the bus bar portion 5a is directed downward so that the solder film is not stretched. And solder coated. In the jet flow method, solar cells are installed in a direction in which a film is not stretched based on the same concept.
【０００４】しかし、太陽電池が大面積化するとフィン
ガー部５ｂが長くなり、それに伴う配線抵抗が大きくな
る。すなわちフィンガー部５ｂと垂直にバスバ一部５ａ
を複数個設けることによって配線抵抗を低減させること
が必要になり、図４（ｂ）のようにバスバー部５ａを半
導体基板１の両側に平行に設けた電極パターンが採用さ
れる。However, when the area of the solar cell is increased, the finger portion 5b becomes longer, and the wiring resistance is increased accordingly. That is, the bus bar part 5a is perpendicular to the finger part 5b.
It is necessary to reduce the wiring resistance by providing a plurality of the electrodes, and an electrode pattern in which bus bar portions 5a are provided in parallel on both sides of the semiconductor substrate 1 as shown in FIG.
【０００５】このとき、二つのバスバー部５ａとフィン
ガー部５ｂで閉じたパターン部ができるので、ディップ
法、噴流式に拘らず半田を被覆すると、この部分に半田
膜が張る個所が発生する。半導体基板を半田槽から引き
上げた後に、この半田膜がはじけないときは半田ブリッ
ジが形成されてフィンガー部５ｂ間が半田で覆われ受光
面が減少する。一方、半田膜がはじけたときは、行き場
のない半田によって半田玉が電極５部分に形成される。
これら半田ブリッジや半田玉は外観を阻害するととも
に、モジュール化のときの歩留りを低下させる。At this time, since a closed pattern portion is formed by the two bus bar portions 5a and the finger portions 5b, when the solder is coated regardless of the dipping method or the jet flow method, a portion where a solder film is stretched occurs in this portion. If the solder film does not repel after the semiconductor substrate is lifted from the solder bath, a solder bridge is formed, the space between the finger portions 5b is covered with solder, and the light receiving surface is reduced. On the other hand, when the solder film has popped, a solder ball is formed on the electrode 5 by the solder having no place to go.
These solder bridges and solder balls impair the appearance and lower the yield when modularized.
【０００６】従来、これらの解決法として、溶融半田槽
から引き上げるときに、ヒータで熱風を送って半田が剥
がれるようにしたり、引き上げた太陽電池素子を加熱す
るといった方法があった（例えば特開平３−１４５１６
６号）。また、半田と半導体基板との濡れ性を向上させ
るために、必要以上に半田温度を上げたり、半田槽から
ゆっくり引き上げることによって対処していた。Conventionally, as a solution to these problems, there has been a method in which hot air is sent by a heater so that the solder is peeled off when the solder cell is lifted from the molten solder bath, or a solar cell element that has been lifted is heated (for example, Japanese Patent Laid-Open No. Hei 3 (1994)). -14516
No. 6). Further, in order to improve the wettability between the solder and the semiconductor substrate, measures have been taken by raising the solder temperature more than necessary or slowly pulling it out of the solder bath.
【０００７】しかしながら、半田ディップ時や引き上げ
時に、太陽電池を必要以上に加熱すると、表面電極５と
半導体基板１との密着強度が低下するという問題を誘発
する。However, when the solar cell is heated more than necessary at the time of solder dip or pulling, a problem is caused that the adhesion strength between the surface electrode 5 and the semiconductor substrate 1 is reduced.
【０００８】本発明はこのような従来方法の問題点に鑑
みてなされたものであり、電極を半田で被覆する際に、
半田ブリッジや半田玉が生じることを極力解消した太陽
電池の形成方法を提供することを目的とする。[0008] The present invention has been made in view of such problems of the conventional method, and when coating an electrode with solder,
An object of the present invention is to provide a method for forming a solar cell in which the occurrence of solder bridges and solder balls is eliminated as much as possible.
【０００９】[0009]
【問題点を解決するための手段】上記目的を達成するた
めに、請求項１に係る太陽電池の形成方法では、半導体
基板の一主面側と他の主面側に異なる導電領域を形成し
て一主面側にバスバー部とフィンガー部とから成る表面
電極を形成すると共に、他の主面側に裏面電極を形成し
て、これら電極を半田で被覆する太陽電池の形成方法に
おいて、前記表面電極を半田で被覆する際に、前記表面
電極の一部にレジスト膜を塗布して半田で被覆すること
を特徴とする。In order to achieve the above object, in the method for forming a solar cell according to the first aspect, different conductive regions are formed on one main surface side and another main surface side of a semiconductor substrate. Forming a front surface electrode comprising a bus bar portion and a finger portion on one main surface side, forming a back surface electrode on the other main surface side, and coating these electrodes with solder; When the electrode is covered with solder, a resist film is applied to a part of the surface electrode and covered with the solder.
【００１０】また、請求項２に係る太陽電池の形成方法
では、半導体基板の一主面側と他の主面側に異なる導電
領域を形成して一主面側にバスバー部とフィンガー部と
から成る表面電極を形成すると共に、他の主面側に裏面
電極を形成して、これら電極を半田で被覆する太陽電池
素子の形成方法において、前記表面電極の一部を切除し
て半田で被覆した後、配線部材を接合することを特徴と
する。In the method of forming a solar cell according to the second aspect, different conductive regions are formed on one main surface side of the semiconductor substrate and another main surface side, and the bus bar portion and the finger portion are formed on the one main surface side. In the method of forming a solar cell element in which a back electrode is formed on the other main surface side and these electrodes are coated with solder, a part of the front electrode is cut off and coated with solder. Thereafter, the wiring member is joined.
【００１１】これらの方法によれば、半田槽から引き上
げるときに太陽電池素子を加熱などしなくても電極パタ
ーンに半田膜は張らず、半田玉の発生も無くなる。ま
た、半田槽から高速で引き上げることができるので、電
極と半導体基板との密着強度が低下するといった問題が
解決する。According to these methods, no solder film is formed on the electrode pattern even when the solar cell element is not heated or the like when the solar cell element is lifted from the solder bath, and the generation of solder balls is eliminated. In addition, since it can be pulled up from the solder bath at a high speed, the problem that the adhesion strength between the electrode and the semiconductor substrate is reduced is solved.
【００１２】[0012]
【発明の実施の形態】以下、本発明を添付図面にもとづ
き詳細に説明する。図１は本発明の太陽電池素子の形成
方法を断面図で示したものである。まず、半導体基板１
を用意する。（図４（ａ）参照）。この半導体基板１
は、単結晶または多結晶シリコンなどからなる。このシ
リコン基板１は、ボロン（Ｂ）などの一導電型半導体不
純物を１×１０16〜１×１０18ａｔｏｍｓ／ｃｍ3 程度
含有し、比抵抗１．５Ωｃｍ程度の基板である。単結晶
シリコン基板の場合は引き上げ法などによって形成さ
れ、多結晶シリコン基板の場合は鋳造法などによって形
成される。多結晶シリコン基板は、大量生産が可能であ
り、製造コスト面で単結晶シリコン基板よりも有利であ
る。引き上げ法や鋳造法によって形成されたインゴット
を３００〜５００μｍ程度の厚みにスライスして、１０
ｃｍ×１０ｃｍもしくは１５ｃｍ×１５ｃｍ程度の大き
さに切断して半導体基板１とする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing a method for forming a solar cell element of the present invention. First, the semiconductor substrate 1
Prepare (See FIG. 4A). This semiconductor substrate 1
Is made of single crystal or polycrystalline silicon. This silicon substrate 1 is a substrate containing about 1 × 10 16 to 1 × 10 18 atoms / cm 3 of one conductivity type semiconductor impurity such as boron (B) and having a specific resistance of about 1.5 Ωcm. In the case of a single crystal silicon substrate, it is formed by a pulling method or the like, and in the case of a polycrystalline silicon substrate, it is formed by a casting method or the like. A polycrystalline silicon substrate can be mass-produced and is more advantageous than a single crystal silicon substrate in terms of manufacturing cost. The ingot formed by the pulling method or the casting method is sliced into a thickness of about 300 to 500 μm,
The semiconductor substrate 1 is cut into a size of about cm × 10 cm or about 15 cm × 15 cm.
【００１３】次に、シリコン基板１を拡散炉中に配置し
て、オキシ塩化リン（ＰＯＣｌ3 ）などの中で加熱する
ことによって、シリコン基板１の表面部分にリン原子を
１×１０16〜１×１０18ａｔｏｍｓ／ｃｍ3 程度拡散さ
せて他の導電型を呈する領域１ａを形成し、半導体接合
部３を形成する（図１（ｂ）参照）。この他の導電型を
呈する領域１ａは、０．２〜０．５ｍμ程度の深さに形
成され、シート抵抗が４０／□以上になるように形成さ
れる。シリコン基板１の一主面側の他の導電型を呈する
領域１ａのみを残して他の部分の他の導電型を呈する領
域をフッ酸と硝酸を主成分とするエッチング液で除去し
て純水で洗浄する（図１（ｃ））。Next, the silicon substrate 1 is placed in a diffusion furnace and heated in phosphorous oxychloride (POCl 3 ) or the like so that the surface portion of the silicon substrate 1 has phosphorus atoms of 1 × 10 16 to 1 × 10 16. A region 1a exhibiting another conductivity type is formed by diffusing about × 10 18 atoms / cm 3 to form a semiconductor junction 3 (see FIG. 1B). The region 1a having another conductivity type is formed at a depth of about 0.2 to 0.5 mμ, and is formed so that the sheet resistance becomes 40 / □ or more. Except for the region 1a exhibiting another conductivity type on one principal surface side of the silicon substrate 1, the other region exhibiting another conductivity type is removed with an etching solution containing hydrofluoric acid and nitric acid as a main component, and pure water is removed. (FIG. 1 (c)).
【００１４】次に、シリコン基板１の一主面側に反射防
止膜２を形成する（図１（ｄ）参照）。この反射防止膜
はたとえば窒化シリコン膜などからなり、シランとアン
モニアとの混合ガスを用いたプラズマＣＶＤ法などで形
成される。この反射防止膜２は、シリコン基板１の表面
で光が反射するのを防止して、シリコン基板１内に光を
有効に取り込むために設ける。Next, an antireflection film 2 is formed on one main surface of the silicon substrate 1 (see FIG. 1D). This antireflection film is made of, for example, a silicon nitride film or the like, and is formed by a plasma CVD method using a mixed gas of silane and ammonia. The antireflection film 2 is provided to prevent light from being reflected on the surface of the silicon substrate 1 and to effectively take in light into the silicon substrate 1.
【００１５】そして、この反射防止膜２の表面電極５に
相当する部分をエッチングした上で電極ペースト５を塗
布して焼成する。もしくはこの反射防止膜２上に直接電
極ペースト５を塗布して焼成する。電極ペースト５の塗
布と焼成においては、裏面電極材料４を塗布して乾燥し
た後、表面電極材料５を塗布して乾燥して焼成する。こ
の電極材料４、５は銀粉末と有機ビヒクルにガラスフリ
ットを銀１００重量部に対して０．１〜５重量部添加し
てぺ一スト状にしたものをスクリーン印刷法で印刷して
６００〜８００度で１〜３０分程度焼成することにより
焼き付けられる。このガラスフリットは、ＰｂＯ、Ｂ2
Ｏ3 、ＳｉＯ２のうち少なくとも一種を含む軟化点が５
００度以下のものなどから成る。電極材料５、６は受光
面の配線抵抗が極小になるように配設される。すなわち
受光面は最大になり、配線抵抗は最小になるように設計
されたものである。表面電極５は、バスバー部５ａがフ
ィンガー部５ｂに垂直に２本設けられている。Then, after etching a portion corresponding to the surface electrode 5 of the antireflection film 2, an electrode paste 5 is applied and baked. Alternatively, the electrode paste 5 is applied directly on the antireflection film 2 and baked. In the application and firing of the electrode paste 5, the back electrode material 4 is applied and dried, and then the front electrode material 5 is applied and dried and fired. The electrode materials 4 and 5 were prepared by adding 0.1 to 5 parts by weight of glass frit to 100 parts by weight of silver to silver powder and an organic vehicle, and then printing the paste by screen printing. It is baked by baking at 800 degrees for about 1 to 30 minutes. This glass frit is made of PbO, B 2
The softening point containing at least one of O 3 and SiO 2 is 5
It is made of the thing of less than 00 degrees. The electrode materials 5 and 6 are disposed so that the wiring resistance on the light receiving surface is minimized. That is, it is designed so that the light receiving surface is maximized and the wiring resistance is minimized. The surface electrode 5 is provided with two bus bar portions 5a perpendicular to the finger portions 5b.
【００１６】その後、図２に示すように、それぞれのバ
スバー部５ａとフィンガー部５ｂの交わる箇所のバスバ
ー部５ａの中ほどに半田レジスト６を塗布する。この半
田レジスト６は、例えば有機硬化樹脂などから成る。ま
た、塗布のパターンは例えば幅１００μｍ長さ１０００
μｍ程度にすればよい。Thereafter, as shown in FIG. 2, a solder resist 6 is applied to the middle of the bus bar portion 5a where the bus bar portion 5a and the finger portion 5b intersect. The solder resist 6 is made of, for example, an organic cured resin. The pattern of the coating is, for example, 100 μm in width and 1000 in length.
It may be about μm.
【００１７】バスバー部５ａとフィンガー５ｂの交わる
箇所の中ほどに半田レジストを塗布する代わりに、元々
のバスバー部５ａの設計を半田が濡れないように切り取
った電極パターンとしてもよい。この場合は、年極５を
半田で被覆した後に、例えば銅箔などの配線部材を接合
すれば表面電極５の全ての部分が接続されることにな
る。Instead of applying a solder resist in the middle of the location where the bus bar portion 5a and the finger 5b intersect, the original bus bar portion 5a design may be an electrode pattern cut out so as not to wet the solder. In this case, after covering the annual electrode 5 with solder, if a wiring member such as a copper foil is joined, all parts of the surface electrode 5 will be connected.
【００１８】[0018]
【実施例】抵抗１．５Ωｃｍのシリコン基板内の一主面
側に、Ｐを１×１０17ａｔｏｍｓ／ｃｍ3 拡散させて厚
み８５０Åの窒化シリコン膜が形成した。このシリコン
基板の一主面側に銀１００重量部に対してガラスフリッ
トを３重量部含有した銀粉末を有機ビヒクルから成る銀
ペ一ストをバスバーがフィンガーに垂直に２本配設され
ているパタ一ンとなるように印刷して７５０度１５分で
焼き付けた。次に、図２に示したように、バスバーとフ
ィンガーの交わる個所と個所の中ほどにバスバー部を横
切るように半田レジストのラインを印刷して乾燥した。
その後、ディップ法でフィンガー電極の方向と半田槽の
半田液面がほぼ垂直になるように浸漬し、つづいて引き
上げることで半田コートを行った。半田槽から太陽電池
素子を引き上げる速度と半田玉の発生数、半導体基板と
電極の密着強度の関係を表１に示し、従来法で行った場
合を比較のために表２に示す。EXAMPLE P was diffused at 1 × 10 17 atoms / cm 3 on one principal surface side of a silicon substrate having a resistance of 1.5 Ωcm to form a silicon nitride film having a thickness of 850 °. A silver paste composed of an organic vehicle containing silver powder containing 3 parts by weight of glass frit with respect to 100 parts by weight of silver on one principal surface side of the silicon substrate is a pattern in which two bus bars are arranged perpendicular to the fingers. It was printed at 750 degrees and printed at 750 degrees for 15 minutes. Next, as shown in FIG. 2, a line of the solder resist was printed so as to cross the bus bar portion at a portion where the bus bar and the finger intersect and in the middle of the portion, and dried.
Thereafter, the substrate was immersed by the dipping method so that the direction of the finger electrode and the solder liquid level of the solder bath were substantially perpendicular to each other, and then the solder was coated by lifting. Table 1 shows the relationship between the speed at which the solar cell element is pulled up from the solder bath, the number of solder balls generated, and the adhesion strength between the semiconductor substrate and the electrode. Table 2 shows the results obtained by the conventional method for comparison.
【００１９】[0019]
【表１】 [Table 1]
【００２０】[0020]
【表２】 [Table 2]
【００２１】表１から明らかなように、半田槽から引き
上げる速度が２０ｃｍ／秒でも半田玉の発生は皆無であ
った。さらに半田槽での浸漬時間が短いので電極に与え
るダメージが軽減し密着強度は１ｋｇ以上が確保できて
いた。As is clear from Table 1, no solder balls were generated even when the speed of lifting from the solder bath was 20 cm / sec. Furthermore, since the immersion time in the solder bath was short, damage to the electrodes was reduced, and the adhesion strength of 1 kg or more could be secured.
【００２２】[0022]
【発明の効果】以上、詳細に説明したように、請求項１
に係る太陽電池の形成方法によれば、表面電極を半田で
被覆する際に、表面電極の一部にレジスト膜を塗布して
半田で被覆することから、閉じたパターンを持つ電極で
あっても半田ディップ時に半田の膜の形成が無く、従っ
て半田玉の発生を防ぐことができる。また、半田中の浸
漬時間が短縮されるので、半導体基板と電極の密着強度
が向上する。As described in detail above, claim 1 is as follows.
According to the method for forming a solar cell according to the above, when coating the surface electrode with solder, since a resist film is applied to part of the surface electrode and coated with solder, even an electrode having a closed pattern There is no formation of a solder film at the time of solder dipping, so that generation of solder balls can be prevented. Further, since the immersion time in the solder is shortened, the adhesion strength between the semiconductor substrate and the electrode is improved.
【００２３】また、請求項２に係る太陽電池の形成方法
によれば、表面電極の一部を切除して半田で被覆した
後、配線部材を接合することから、閉じたパターンを持
つ電極であっても半田ディップ時に半田の膜の形成が無
く、従って半田玉の発生を防ぐことができる。また、半
田中の浸漬時間が短縮されるので、半導体基板と電極の
密着強度が確保できる。Further, according to the method for forming a solar cell according to the second aspect, since a part of the surface electrode is cut off and covered with solder, and then the wiring member is joined, the electrode has a closed pattern. Even when the solder is dipped, no solder film is formed, and therefore, the occurrence of solder balls can be prevented. Further, since the immersion time in the solder is shortened, the adhesion strength between the semiconductor substrate and the electrode can be secured.
【図１】本発明に係る太陽電池の形成方法の一実施形態
を示す図である。FIG. 1 is a view showing one embodiment of a method for forming a solar cell according to the present invention.
【図２】本発明の一主面側パターンの一例の平面図であ
る。FIG. 2 is a plan view of an example of a main surface side pattern of the present invention.
【図３】従来の太陽電の構造を示す断面図である。FIG. 3 is a cross-sectional view showing the structure of a conventional solar cell.
【図４】従来の太陽電池の電極パターンを示す図であ
り、（ａ）はバスバー部が一つ形成された例、（ｂ）は
バスバー部が二つ形成された例である。4A and 4B are diagrams showing an electrode pattern of a conventional solar cell, wherein FIG. 4A is an example in which one bus bar portion is formed, and FIG. 4B is an example in which two bus bar portions are formed.
１‥‥‥半導体基板、１ａ‥‥‥他の導電型を呈する領
域、２‥‥‥反射防止膜、３‥‥‥半導体接合部、４‥
‥‥裏面電極、５‥‥‥表面電極、５ａ‥‥‥バスバー
部、５ｂ‥‥‥フィンガー部、６‥‥‥半田レジスト1 {semiconductor substrate, 1a} region exhibiting other conductivity type, 2} antireflection film, 3} semiconductor junction, 4 #
{Back electrode, 5} Front electrode, 5a {Busbar part, 5b} Finger part, 6} Solder resist
Claims (2)
なる導電領域を形成して一主面側にバスバー部とフィン
ガー部とから成る表面電極を形成すると共に、他の主面
側に裏面電極を形成して、これら電極を半田で被覆する
太陽電池の形成方法において、前記表面電極を半田で被
覆する際に、前記表面電極の一部にレジスト膜を塗布し
て半田で被覆することを特徴とする太陽電池の形成方
法。1. A semiconductor device according to claim 1, wherein a conductive region is formed on one main surface side of the semiconductor substrate and another conductive surface is formed on another main surface side to form a surface electrode comprising a bus bar portion and a finger portion on one main surface side. In a method for forming a solar cell in which a back electrode is formed on the side and these electrodes are covered with solder, when the front electrode is covered with solder, a resist film is applied to part of the front electrode and covered with solder. A method for forming a solar cell.
なる導電領域を形成して一主面側にバスバー部とフィン
ガー部とから成る表面電極を形成すると共に、他の主面
側に裏面電極を形成して、これら電極を半田で被覆する
太陽電池素子の形成方法において、前記表面電極の一部
を切除して半田で被覆した後、配線部材を接合すること
を特徴とする太陽電池の形成方法。2. A semiconductor device according to claim 1, further comprising: forming a different conductive region on one main surface side and another main surface side to form a surface electrode including a bus bar portion and a finger portion on one main surface side; Forming a back electrode on the side and covering these electrodes with solder, wherein a part of the front electrode is cut off and covered with solder, and then a wiring member is joined. A method for forming a solar cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14338399A JP4091710B2 (en) | 1999-05-24 | 1999-05-24 | Method for forming solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14338399A JP4091710B2 (en) | 1999-05-24 | 1999-05-24 | Method for forming solar cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000332272A true JP2000332272A (en) | 2000-11-30 |
| JP4091710B2 JP4091710B2 (en) | 2008-05-28 |
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ID=15337505
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14338399A Expired - Fee Related JP4091710B2 (en) | 1999-05-24 | 1999-05-24 | Method for forming solar cell |
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| Country | Link |
|---|---|
| JP (1) | JP4091710B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003338631A (en) * | 2002-05-22 | 2003-11-28 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP2008159895A (en) * | 2006-12-25 | 2008-07-10 | Sanyo Electric Co Ltd | Solar cell and solar cell module |
| WO2012057243A1 (en) * | 2010-10-27 | 2012-05-03 | 三洋電機株式会社 | Solar cell and solar cell module |
| WO2012102188A1 (en) * | 2011-01-28 | 2012-08-02 | 三洋電機株式会社 | Solar cell and solar cell module |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08109571A (en) * | 1994-10-07 | 1996-04-30 | Hisaka Works Ltd | Air jet-type treatment of continuous textile product and system therefor |
-
1999
- 1999-05-24 JP JP14338399A patent/JP4091710B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003338631A (en) * | 2002-05-22 | 2003-11-28 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP2008159895A (en) * | 2006-12-25 | 2008-07-10 | Sanyo Electric Co Ltd | Solar cell and solar cell module |
| WO2012057243A1 (en) * | 2010-10-27 | 2012-05-03 | 三洋電機株式会社 | Solar cell and solar cell module |
| WO2012102188A1 (en) * | 2011-01-28 | 2012-08-02 | 三洋電機株式会社 | Solar cell and solar cell module |
| JP2012156460A (en) * | 2011-01-28 | 2012-08-16 | Sanyo Electric Co Ltd | Solar cell and solar cell module |
| CN103339737A (en) * | 2011-01-28 | 2013-10-02 | 三洋电机株式会社 | Solar cell and solar cell module |
| EP2669954A4 (en) * | 2011-01-28 | 2017-06-21 | Panasonic Intellectual Property Management Co., Ltd. | Solar cell and solar cell module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4091710B2 (en) | 2008-05-28 |
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