JP2000286449A - Iii nitride compound semiconductor device and its manufacture - Google Patents
Iii nitride compound semiconductor device and its manufactureInfo
- Publication number
- JP2000286449A JP2000286449A JP9229199A JP9229199A JP2000286449A JP 2000286449 A JP2000286449 A JP 2000286449A JP 9229199 A JP9229199 A JP 9229199A JP 9229199 A JP9229199 A JP 9229199A JP 2000286449 A JP2000286449 A JP 2000286449A
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- layer
- compound semiconductor
- iii nitride
- group iii
- substrate
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はIII族窒化物系化合物半
導体素子及びその製造方法に関する。詳しくは、高品質
のIII族窒化物系化合物半導体層を得るためのIII族窒化
物系化合物半導体素子の製造方法の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a group III nitride compound semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to an improvement in a method of manufacturing a group III nitride compound semiconductor device for obtaining a high quality group III nitride compound semiconductor layer.
【０００２】[0002]
【従来の技術】従来、導電性のシリコン基板上にIII族
窒化物系化合物半導体層を積層した構成の素子が知られ
ている。導電性のシリコン基板を用いることの利点とし
て、基板に直接電極を接続することが可能となり、電極
を接続するために半導体層を複雑にエッチングする工程
が不要となることが挙げられる。また、半導体素子のチ
ャージアップの問題も解消できる等の利点もある。III
族窒化物系化合物半導体素子は、短波長の発光素子、レ
ーザーダイオード、各種電子デバイスとして利用され
る。2. Description of the Related Art Heretofore, there has been known an element having a structure in which a group III nitride compound semiconductor layer is laminated on a conductive silicon substrate. An advantage of using a conductive silicon substrate is that an electrode can be directly connected to the substrate, and a complicated etching step of the semiconductor layer for connecting the electrode is not required. Further, there is an advantage that the problem of charge-up of the semiconductor element can be solved. III
A group nitride compound semiconductor device is used as a short wavelength light emitting device, a laser diode, and various electronic devices.
【０００３】[0003]
【発明が解決しようとする課題】高品質の素子を再現性
良く、かつ高い歩留まりで得るためには、基板ウエハー
上にIII族窒化物系化合物半導体層をその全域において
均質に成長させる必要がある。しかしながら、本発明者
らが、シリコン基板上にＭＯＣＶＤ法により成長させた
III族窒化物系化合物半導体層を観察したところ、その
中央部分と周縁部分とで結晶の様子が異なっていた。す
なわち、中央部分では設計通りに結晶性良くIII族窒化
物系化合物半導体層がエピタキシャル成長しているもの
の、周縁部分ではIII族窒化物系化合物半導体層の結晶
性が低下していた。本発明者らの検討によれば、かかる
周縁部分での結晶性の低下はＭＯＣＶＤ法を実行すると
きの高温でシリコン基板の材料が蒸発し、III族窒化物
系化合物半導体層中へ拡散することによるものと考えら
れる。また、シリコンがIII族窒化物系化合物半導体層
中に拡散するとIII族窒化物系化合物半導体の伝導型及
び導電率にも影響がでるため好ましくない。In order to obtain a high quality device with good reproducibility and high yield, it is necessary to grow a group III nitride compound semiconductor layer uniformly on the substrate wafer over the entire area. . However, the present inventors have grown on a silicon substrate by MOCVD.
When the group III nitride-based compound semiconductor layer was observed, the state of the crystal was different between the central part and the peripheral part. That is, although the group III nitride compound semiconductor layer was epitaxially grown with good crystallinity as designed in the center portion, the crystallinity of the group III nitride compound semiconductor layer was reduced in the peripheral portion. According to the study of the present inventors, such a decrease in crystallinity at the peripheral portion is caused by the fact that the material of the silicon substrate evaporates at a high temperature when performing the MOCVD method and diffuses into the group III nitride-based compound semiconductor layer. It is thought to be due to. In addition, it is not preferable that silicon diffuses into the group III nitride-based compound semiconductor layer, because it also affects the conductivity type and conductivity of the group III nitride-based compound semiconductor.
【０００４】[0004]
【課題を解決するための手段】本発明は、上記課題に鑑
みてなされたものであり、高品質のIII族窒化物系化合
物半導体素子を得るための新規な製造方法を提供するこ
とを目的とする。その構成は以下の通りである。シリコ
ン基板の側壁を拡散防止層で被覆した状態でIII族窒化
物系化合物半導体を前記シリコン基板の上面に成長させ
る、ことを特徴とするIII族窒化物系化合物半導体素子
の製造方法。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a novel manufacturing method for obtaining a high quality group III nitride compound semiconductor device. I do. The configuration is as follows. A method of manufacturing a group III nitride compound semiconductor device, comprising growing a group III nitride compound semiconductor on an upper surface of the silicon substrate while covering a side wall of the silicon substrate with a diffusion preventing layer.
【０００５】上記の製造方法によれば、III族窒化物系
化合物半導体層を成長させるとき当該III族窒化物系化
合物半導体層に最も近いシリコン基板の側壁が酸化シリ
コン層で覆われるため、基板材料であるシリコンがそこ
から蒸発することが防止される。これにより、基板由来
の不純物がIII族窒化物系化合物半導体層に拡散するこ
とが防止され、その結果、結晶性に優れ、かつ全域で均
質のIII族窒化物系化合物半導体層が形成される。ま
た、III族窒化物系化合物半導体層の伝導型及び導電率
も安定する。もって、高品質のIII族窒化物系化合物半
導体素子を再現性良く製造することができる。According to the above manufacturing method, when growing a group III nitride-based compound semiconductor layer, the side wall of the silicon substrate closest to the group III nitride-based compound semiconductor layer is covered with the silicon oxide layer. Is prevented from evaporating therefrom. This prevents the impurity derived from the substrate from diffusing into the group III nitride-based compound semiconductor layer, and as a result, a group III nitride-based compound semiconductor layer having excellent crystallinity and being uniform over the entire region is formed. Further, the conductivity type and conductivity of the group III nitride-based compound semiconductor layer are also stabilized. Thus, a high-quality group III nitride-based compound semiconductor device can be manufactured with good reproducibility.
【０００６】[0006]
【発明の実施の形態】上記において、拡散防止層はIII
族窒化物系化合物半導体を成長させるとき、その成長温
度及び環境において安定であって、シリコン基板の材料
が蒸発することを防止できるものであれば特にその材料
は限定されない。例えば、酸化シリコンや窒化シリコン
などを挙げることができる。かかる拡散防止層の形成方
法も特に限定されるものではなく、CVD法やスパッタ法
等の一般的な方法が採用できる。拡散防止層が酸化シリ
コン製のときは、基板を酸素や水の雰囲気下で高温処理
するか若しくは所定のエッチャント（Ｈ２Ｏ、Ｈ
２Ｏ２、ＮＨ３ＯＨ混合液）へ基板を浸漬することによ
りこれを形成することができる。なお、このような酸化
処理を行うとシリコン基板の裏面にも酸化シリコン層が
形成される場合があるが、この発明は基板裏面への酸化
シリコン層、即ち拡散防止層の形成を除外するものでは
ない。換言すれば、III族窒化物系化合物半導体を成長
させる面以外のシリコン基板の面を当該拡散防止層で被
覆する。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the above, the diffusion preventing layer is III
When growing a group III nitride compound semiconductor, the material is not particularly limited as long as it is stable at the growth temperature and environment and can prevent the material of the silicon substrate from evaporating. For example, silicon oxide, silicon nitride, or the like can be given. The method for forming the diffusion preventing layer is not particularly limited, and a general method such as a CVD method or a sputtering method can be employed. When the diffusion prevention layer is made of silicon oxide, the substrate is subjected to a high temperature treatment in an atmosphere of oxygen or water, or a predetermined etchant (H 2 O, H
This can be formed by immersing the substrate in a mixed solution of 2 O 2 and NH 3 OH. Note that when such an oxidation treatment is performed, a silicon oxide layer may be formed on the back surface of the silicon substrate, but the present invention does not exclude the formation of the silicon oxide layer on the back surface of the substrate, that is, the formation of the diffusion prevention layer. Absent. In other words, the surface of the silicon substrate other than the surface on which the group III nitride compound semiconductor is grown is covered with the diffusion preventing layer.
【０００７】シリコンによる汚染を回避したいIII族窒
化物系化合物半導体層を成長させる前までに拡散防止層
はシリコン基板の側壁へ形成される。ＡｌＮやＧａＮ等
のIII族窒化物系化合物半導体からなる低温成長バッフ
ァ層を用いるときは、その形成時にはシリコンの蒸発量
が少ない。従って、当該バッファ層を形成した後、シリ
コン基板を酸化処理して酸化シリコン製の拡散防止層を
形成する。なお、このときIII族窒化物系化合物半導体
からなるバッファ層は酸化処理の影響を受けない。ま
た、ｎ層のIII族窒化物系化合物半導体にはシリコンが
拡散してもその伝導型に影響が出ないので、発光素子の
場合、ｎクラッド層を形成した後、活性層及びp型クラ
ッド層を形成する前に当該酸化処理を行っても良い。ま
た、シリコン基板表面へ酸化シリコンのストライプ層を
形成する所謂ＬＥＯ法（Ａｐｐｌ.Ｐｈｙｓ.Ｌｅｔｔ.
７１(１８)、３ Ｎｏｖ．１９９７参照）を実行すると
きには、当該酸化シリコンのストライプ層を形成するス
テップを実行する際に、若しくはそのステップの前後に
当該シリコン基板の側面へ酸化シリコン層を形成するこ
とが好ましい。拡散防止層の膜厚は特に限定されない
が、０．０２〜１．０μｍとすることが好ましい。[0007] Before growing a group III nitride compound semiconductor layer for which contamination by silicon is to be avoided, a diffusion preventing layer is formed on the side wall of the silicon substrate. When a low-temperature growth buffer layer made of a group III nitride compound semiconductor such as AlN or GaN is used, a small amount of silicon evaporates during the formation. Therefore, after forming the buffer layer, the silicon substrate is oxidized to form a silicon oxide diffusion prevention layer. At this time, the buffer layer made of the group III nitride compound semiconductor is not affected by the oxidation treatment. In addition, since the diffusion of silicon does not affect the conductivity type of the n-type group III nitride compound semiconductor, in the case of a light emitting device, the active layer and the p-type cladding layer are formed after forming the n-cladding layer. The oxidation treatment may be performed before the formation. Also, a so-called LEO method (Appl. Phys. Lett.) For forming a silicon oxide stripe layer on the surface of a silicon substrate.
71 (18), 3 Nov. When performing the step (1997), it is preferable to form a silicon oxide layer on the side surface of the silicon substrate when performing the step of forming the silicon oxide stripe layer, or before or after the step. The thickness of the diffusion prevention layer is not particularly limited, but is preferably 0.02 to 1.0 μm.
【０００８】III族窒化物系化合物半導体は、一般式と
してＡｌＸＧａＹＩｎ１ーＸーＹＮ（０≦Ｘ≦１、０≦
Ｙ≦１、０≦Ｘ＋Ｙ≦１）で表されるものであるが、更
にIII族元素としてボロン（Ｂ）、タリウム（Ｔｌ）を
含んでもよく、また、窒素（Ｎ）の一部を、リン
（Ｐ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、ビスマス
（Ｂｉ）で置き換えても良い。III族窒化物系化合物半
導体は任意のドーパントを含むものであっても良い。II
I族窒化物系化合物半導体層の形成方法は特に限定され
ないが、例えば、周知の有機金属化合物気相成長法（こ
の明細書で、「ＭＯＣＶＤ法」という。）により形成さ
れる。また、周知の分子線結晶成長法（ＭＢＥ法）やハ
ライド系気相成長法（ＨＶＰＥ法）等によっても形成す
ることができる。III族窒化物系化合物半導体の層は素
子の種類、目的に応じて複数設ける。例えば、後述の実
施例における発光素子では、ｎ型III族窒化物系化合物
半導体層、発光層、ｐ型III族窒化物系化合物半導体層
を形成する。The group III nitride compound semiconductor has a general formula of Al X Ga Y In 1-XY N (0 ≦ X ≦ 1, 0 ≦
Y ≦ 1, 0 ≦ X + Y ≦ 1), and may further contain boron (B) or thallium (Tl) as a group III element. (P), arsenic (As), antimony (Sb), bismuth (Bi) may be substituted. The group III nitride compound semiconductor may contain any dopant. II
The method of forming the group I nitride-based compound semiconductor layer is not particularly limited, but is formed by, for example, a well-known organic metal compound vapor deposition method (hereinafter, referred to as “MOCVD method”). Further, it can also be formed by a well-known molecular beam crystal growth method (MBE method), a halide vapor phase epitaxy method (HVPE method), or the like. A plurality of group III nitride-based compound semiconductor layers are provided depending on the type and purpose of the device. For example, in a light emitting device in an example described later, an n-type group III nitride compound semiconductor layer, a light emitting layer, and a p-type group III nitride compound semiconductor layer are formed.
【０００９】III族窒化物系化合物半導体を成長させる
ときの温度が高いほど、シリコン基板からのシリコンの
脱離量が多くなる。従って、その成長温度が８００〜１
２００℃であるIII族窒化物系化合物半導体を成長させ
る前までに、シリコン基板の側壁に拡散防止層を形成し
ておくことが好ましい。したがって,The higher the temperature at which the group III nitride compound semiconductor is grown, the greater the amount of silicon desorbed from the silicon substrate. Therefore, the growth temperature is 800 to 1
It is preferable to form a diffusion prevention layer on the side wall of the silicon substrate before growing the group III nitride-based compound semiconductor at 200 ° C. Therefore,
【００１０】III族窒化物系化合物半導体層を積層した
後、拡散防止層を除去する。この拡散防止層を残存させ
ても良い。After laminating the group III nitride compound semiconductor layer, the diffusion preventing layer is removed. This diffusion preventing layer may be left.
【００１１】[0011]
【実施例】次にこの発明の実施例について説明する. （第１実施例）図１に本発明の製造方法により作製した
発光素子１０の構成を示す。各層のスペックは次の通り
である。 層 ： 組成：ドーパント （膜厚） ｐクラッド層 １７ ： ｐ−ＧａＮ：Ｍｇ （0.3μm） 発光層 １６ ： 超格子構造 量子井戸層 ：Ｉｎ０．１５Ｇａ０．８５Ｎ （35Å） バリア層 ：ＧａＮ （35Å） 量子井戸とバリア層の繰り返し数：１〜１0 ｎクラッド層 １５ ： ｎ−ＧａＮ：Ｓｉ （4μｍ） バッファ層 １４ ： Ａｌ０．９Ｇａ０．１Ｎ （150Å） ＴｉＮ層 １３ ： ＴｉＮ単結晶 （3000Å） 基板 １１ ： Ｓｉ（１１１） （300μm） バッファ層１４及び各半導体層の成長はＭＯＣＶＤ法に
より行われる。この成長法においては、アンモニアガス
とIII族元素のアルキル化合物ガス、例えばトリメチル
ガリウム（ＴＭＧ）、トリメチルアルミニウム（ＴＭ
Ａ）やトリメチルインジウム（ＴＭＩ）とを適当な温度
に加熱された基板上に供給して熱分解反応させ、もって
所望の結晶を基板の上に成長させる。勿論、各半導体層
の形成方法はこれに限定されるものではなく、周知のＭ
ＢＥ法によっても形成することができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will now be described. (First Embodiment) FIG. 1 shows the structure of a light emitting device 10 manufactured by the manufacturing method of the present invention. The specifications of each layer are as follows. Layer: Composition: Dopant (thickness) P-cladding layer 17: p-GaN: Mg (0.3 μm) Light-emitting layer 16: Superlattice structure Quantum well layer: In 0.15 Ga 0.85 N (35 °) Barrier layer: GaN (35 °) Number of repetitions of quantum well and barrier layer: 1 to 10 n cladding layer 15: n-GaN: Si (4 μm) buffer layer 14: Al 0.9 Ga 0.1 N (150 °) TiN layer 13: TiN single Crystal (3000 °) Substrate 11: Si (111) (300 μm) The buffer layer 14 and each semiconductor layer are grown by MOCVD. In this growth method, ammonia gas and an alkyl compound gas of a group III element such as trimethylgallium (TMG) and trimethylaluminum (TM
A) and trimethylindium (TMI) are supplied onto a substrate heated to an appropriate temperature to cause a thermal decomposition reaction, thereby growing a desired crystal on the substrate. Of course, the method of forming each semiconductor layer is not limited to this, and the well-known M
It can also be formed by the BE method.
【００１２】ｎクラッド層１５は発光層１６側の低電子
濃度ｎ−層とバッファ層１４側の高電子濃度ｎ＋層とな
る２層構造とすることができる。発光層１６は超格子構
造のものに限定されない。発光素子の構成としてはシン
グルへテロ型、ダブルへテロ型及びホモ接合型のものな
どを用いることができる。発光層１６とｐクラッド層１
７との間にマグネシウム等のアクセプタをドープしたバ
ンドキャップの広いＡｌＸＧａＹＩｎ１−Ｘ−ＹＮ（０
≦Ｘ≦１、０≦Ｙ≦１、Ｘ＋Ｙ≦１）層を介在させるこ
とができる。これは発光層１６の中に注入された電子が
ｐクラッド層１７に拡散するのを防止するためである。
ｐクラッド層１７を発光層１６側の低ホール濃度ｐ−層
と電極側の高ホール濃度ｐ＋層とからなる２層構造とす
ることができる。The n-cladding layer 15 can have a two-layer structure in which a low electron concentration n − layer on the light emitting layer 16 side and a high electron concentration n + layer on the buffer layer 14 side. The light emitting layer 16 is not limited to a super lattice structure. As a structure of the light emitting element, a single hetero type, a double hetero type, a homo junction type, or the like can be used. Light emitting layer 16 and p clad layer 1
7 broad Al X band cap doped with acceptor magnesium or the like between the Ga Y In 1-X-Y N (0
≦ X ≦ 1, 0 ≦ Y ≦ 1, X + Y ≦ 1) layer can be interposed. This is to prevent electrons injected into the light emitting layer 16 from diffusing into the p clad layer 17.
The p-cladding layer 17 can have a two-layer structure including a low hole concentration p − layer on the light emitting layer 16 side and a high hole concentration p + layer on the electrode side.
【００１３】以下、図１及び図２を参照しながら実施例
の発光素子１０の製造方法を説明する。まず、Ｓｉ（１
１１）面にＴｉＮ層１３が形成される。成長の方法はＴ
ｈｉｎＳｏｌｉｄ Ｆｉｌｍｓ ２７１（１９９５）
１０８〜１１６頁を参照されたい。その後、ＴｉＮ／Ｓ
ｉサンプルをスパッタ装置からＭＯＣＶＤ装置のチャン
バ内に移し変える。このチャンバ内へ水素ガスを流通さ
せながら当該サンプルを１０００℃まで昇温させて５分
間維持する。Hereinafter, a method for manufacturing the light emitting device 10 according to the embodiment will be described with reference to FIGS. First, Si (1
11) A TiN layer 13 is formed on the surface. The growth method is T
HinSolid Films 271 (1995)
See pages 108-116. Then, TiN / S
The i sample is transferred from the sputtering apparatus into the chamber of the MOCVD apparatus. While flowing hydrogen gas into the chamber, the sample is heated to 1000 ° C. and maintained for 5 minutes.
【００１４】その後、ＡｌＧａＮバッファ層１４を成長
させる（図２（ａ））。次に、バッファ層／ＴｉＮ／Ｓ
ｉサンプル３０を一旦ＭＯＣＶＤ装置のチャンバ内から
取りだし、水蒸気で酸化する装置へ移す。そして、当該
酸化膜形成装置内で９００℃の条件下１５分間放置す
る。これにより、基板１１の側面１１ｓ及び底面１１ｂ
の表面が酸化され、酸化シリコンからなる拡散防止層１
８が形成される（図２（ｂ））。本実施例では、水蒸気
による酸化処理をＭＯＣＶＤ装置とは別の装置で行った
が、もちろんＭＯＣＶＤ装置チャンバ内で同様の処理を
行うこともできる。また、酸化処理は水蒸気によるもの
に限られず、他の一般的な方法を採用できることは言う
までもない。Thereafter, an AlGaN buffer layer 14 is grown (FIG. 2A). Next, a buffer layer / TiN / S
The i-sample 30 is once taken out of the chamber of the MOCVD apparatus, and is transferred to an apparatus that oxidizes with water vapor. Then, it is left for 15 minutes at 900 ° C. in the oxide film forming apparatus. Thereby, the side surface 11s and the bottom surface 11b of the substrate 11
Surface is oxidized and the diffusion prevention layer 1 made of silicon oxide is formed.
8 are formed (FIG. 2B). In this embodiment, the oxidation treatment using water vapor is performed in a device different from the MOCVD device. However, a similar process can be performed in the MOCVD device chamber. Further, the oxidation treatment is not limited to the treatment using steam, and it goes without saying that other general methods can be adopted.
【００１５】その後、サンプル３０をＭＯＣＶＤ装置の
チャンバ内にもどし、常法に従いｎクラッド層１５、発
光層１６、及びｐクラッド層１７が順次積層される（図
２（ｃ））。各半導体層の成長は約１０００℃の高温で
行われるが、予め基板側面及び底面が高温に安定な酸化
シリコンにより被覆されているため、基板材料であるシ
リコンが基板表面より蒸発し各半導体層に拡散すること
が防止される。これにより、結晶性に優れた各半導体層
を成長させることができる。また、基板由来のシリコン
がIII族窒化物系化合物半導体層に拡散すればドナー不
純物として挙動するためIII族窒化物系化合物半導体層
の導電率に影響するが、かかるシリコンの拡散を防止す
ることにより半導体層の導電率を変化させるおそれがな
くなる。その結果、所望の伝導型及び導電率を有するII
I族窒化物系化合物半導体層を再現性良く成長させるこ
とができる。Thereafter, the sample 30 is returned into the chamber of the MOCVD apparatus, and the n-cladding layer 15, the light-emitting layer 16, and the p-cladding layer 17 are sequentially laminated according to a conventional method (FIG. 2C). Although the growth of each semiconductor layer is performed at a high temperature of about 1000 ° C., since the side and bottom surfaces of the substrate are coated in advance with silicon oxide that is stable at a high temperature, silicon as a substrate material evaporates from the surface of the substrate and is deposited on each semiconductor layer. Spreading is prevented. Thereby, each semiconductor layer having excellent crystallinity can be grown. Also, if silicon derived from the substrate diffuses into the group III nitride compound semiconductor layer, it behaves as a donor impurity, which affects the conductivity of the group III nitride compound semiconductor layer. There is no risk of changing the conductivity of the semiconductor layer. As a result, having the desired conductivity type and conductivity II
The group I nitride compound semiconductor layer can be grown with good reproducibility.
【００１６】続いて、ドライエッチング、ウエットエッ
チング等のエッチングにより拡散防止層１８を除去する
（図２（ｄ））。Subsequently, the diffusion preventing layer 18 is removed by etching such as dry etching and wet etching (FIG. 2D).
【００１７】透光性電極１９は金を含む薄膜であり、ｐ
クラッド層１７の上面の実質的な全面を覆って積層され
る。ｐ電極２０も金を含む材料で構成されており、蒸着
により透光性電極１９の上に形成される。なお、Ｓｉ基
板１１がｎ電極となる。そして、その所望の位置にワイ
ヤーがボンディングされる。The translucent electrode 19 is a thin film containing gold.
The cladding layer 17 is laminated so as to cover substantially the entire upper surface. The p-electrode 20 is also made of a material containing gold, and is formed on the translucent electrode 19 by vapor deposition. Note that the Si substrate 11 becomes an n-electrode. Then, the wire is bonded to the desired position.
【００１８】（第３実施例）図３に本発明の第３実施例
に係る製造方法を示す。この実施例では、まずシリコン
基板１１の全面に酸化シリコン層３８を形成する。そし
て、シリコン基板１１の上面の酸化シリコン層を常法に
よりパターンニングしてＥＬＯパターン３１を形成する
（図３（ａ）参照）。その後、ＭＯＣＶＤ法を実行して
基板１１の上面にｎ−ＧａＮ層３５を形成する。このｎ
−ＧａＮ層３５はＥＬＯ（Ｅｐｔａｘｉａｌ Ｌａｔｅ
ｒａｌ Ｏｖｅｒｇｒｏｗｔｈ）成長により好適な結晶
性を有する（図３（ｂ）参照）。続いて、発光層３６及
びｐ−ＧａＮ層３７を同じくＭＯＣＶＤ法で形成する。
これらIII族窒化物系化合物半導体層３５〜３７は前の
実施例のIII族窒化物系化合物半導体層１５〜１７とそ
れぞれ同等の層である（図３（ｃ）参照）。そして、酸
化シリコン層３８を除去し、透光性電極３９を蒸着して
図３（ｄ）の素子構成を得る。(Third Embodiment) FIG. 3 shows a manufacturing method according to a third embodiment of the present invention. In this embodiment, first, a silicon oxide layer 38 is formed on the entire surface of the silicon substrate 11. Then, the silicon oxide layer on the upper surface of the silicon substrate 11 is patterned by an ordinary method to form an ELO pattern 31 (see FIG. 3A). After that, the n-GaN layer 35 is formed on the upper surface of the substrate 11 by performing the MOCVD method. This n
-GaN layer 35 is made of ELO (Eptaxial Late
It has better crystallinity due to ral overgrowth (see FIG. 3B). Subsequently, the light emitting layer 36 and the p-GaN layer 37 are similarly formed by the MOCVD method.
These group III nitride-based compound semiconductor layers 35 to 37 are layers equivalent to the group III nitride-based compound semiconductor layers 15 to 17 of the previous embodiment, respectively (see FIG. 3C). Then, the silicon oxide layer 38 is removed, and the translucent electrode 39 is deposited to obtain the element configuration shown in FIG.
【００１９】本発明が適用される素子は上記の発光ダイ
オードに限定されるものではなく、受光ダイオード、レ
ーザダイオード、太陽電池等の光素子の他、整流器、サ
イリスタ及びトランジスタ等のバイポーラ素子、ＦＥＴ
等のユニポーラ素子並びにマイクロウェーブ素子などの
電子デバイスにも適用できる。また、これらの素子の中
間体としての積層体にも本発明は適用されるものであ
る。The element to which the present invention is applied is not limited to the above-mentioned light emitting diode, but is also applicable to an optical element such as a light receiving diode, a laser diode, a solar cell, a bipolar element such as a rectifier, a thyristor and a transistor, and an FET.
And the like, and electronic devices such as microwave devices. The present invention is also applicable to a laminate as an intermediate of these elements.
【００２０】この発明は、上記発明の実施の形態及び実
施例の説明に何ら限定されるものではない。特許請求の
範囲の記載を逸脱せず、当業者が容易に想到できる範囲
で種々の変形態様もこの発明に含まれる。The present invention is not at all limited to the description of the above-described embodiments and examples. Various modifications are included in the present invention without departing from the scope of the claims and within the scope of those skilled in the art.
【００２１】（１１） シリコン基板の側壁を拡散防止
層で被覆した状態でIII族窒化物系化合物半導体を前記
シリコン基板の上面に成長させる、ことを特徴とする積
層体の製造方法。 （１２） 前記III族窒化物系化合物半導体の成長温度
は８００〜１２００℃である、ことを特徴とする（１
１）に記載の製造方法。 （１３） 前記拡散防止層は酸化シリコン又は窒化シリ
コンからなる、ことを特徴とする（１１）又は（１２）
に記載の製造方法。 （１４） 前記拡散防止層を除去するステップが更に含
まれる、ことを特徴とする（１１）〜（１３）のいずれ
かに記載の製造方法。 （１５） シリコン基板上とその上に形成されたIII族
窒化物系化合物半導体層からなる積層体であって、前記
III族窒化物系化合物半導体層は前記シリコン基板の側
壁を拡散防止層で被覆した状態で形成されたものであ
る、ことを特徴とする積層体。 （１６） 前記III族窒化物系化合物半導体の成長温度
は８００〜１２００℃である、ことを特徴とする（１
５）に記載の積層体。 （１７） 前記拡散防止層は酸化シリコン又は窒化シリ
コンからなる、ことを特徴とする（１５）又は（１６）
に記載の積層体。 （２１） シリコン基板にIII族窒化物系化合物半導体
層を形成するステップと、少なくとも一層のIII族窒化
物系化合物半導体層を形成した後に前記シリコン基板の
前記III族窒化物系化合物半導体層が形成されない面に
酸化シリコン層を形成するステップと、を含んでなるII
I族窒化物系化合物半導体素子の製造方法。 （２２） シリコン基板にIII族窒化物系化合物半導体
層を形成するステップと、前記ステップにより形成され
たIII族窒化物系化合物半導体層／シリコン基板積層体
において前記シリコン基板を選択的に酸化するステップ
と、を含んでなるIII族窒化物系化合物半導体素子の製
造方法。 （２３） シリコン基板に少なくとも一層のIII族窒化
物系化合物半導体層を形成するステップと、前記III族
窒化物系化合物半導体層／シリコン基板積層体において
少なくとも前記シリコン基板の側面にシリコンが前記II
I族窒化物系化合物半導体層に拡散することを防止する
拡散防止層を形成するステップと、を含んでなるIII族
窒化物系化合物半導体素子の製造方法。 （２４） 前記拡散防止層は酸化シリコン又は窒化シリ
コンである、ことを特徴とする（２４）に記載の製造方
法。 （２５） 前記拡散防止層を除去するステップが更に含
まれている、ことを特徴とする（２３）又は（２４）に
記載の製造方法。 （５１） シリコン基板にIII族窒化物系化合物半導体
層を形成するステップと、少なくとも一層のIII族窒化
物系化合物半導体層を形成した後に前記シリコン基板の
前記III族窒化物系化合物半導体層が形成されない面に
酸化シリコン層を形成するステップと、を含んでなる積
層体の製造方法。 （５２） シリコン基板にIII族窒化物系化合物半導体
層を形成するステップと、前記ステップにより形成され
たIII族窒化物系化合物半導体層／シリコン基板積層体
において前記シリコン基板を選択的に酸化するステップ
と、を含んでなる積層体の製造方法。 （５３） シリコン基板に少なくとも一層のIII族窒化
物系化合物半導体層を形成するステップと、前記III族
窒化物系化合物半導体層／シリコン基板積層体において
少なくとも前記シリコン基板の側面にシリコンが前記II
I族窒化物系化合物半導体層に拡散することを防止する
拡散防止層を形成するステップと、を含んでなる積層体
の製造方法。 （５４） 前記拡散防止層は酸化シリコン又は窒化シリ
コンである、ことを特徴とする請求項（５３）に記載の
製造方法。 （５５） 前記拡散防止層を除去するステップが更に含
まれている、ことを特徴とする請求項（５３）又は（５
４）に記載の製造方法。(11) A method for manufacturing a laminate, comprising growing a group III nitride compound semiconductor on the upper surface of the silicon substrate while covering the side wall of the silicon substrate with a diffusion preventing layer. (12) The growth temperature of the group III nitride-based compound semiconductor is 800 to 1200 ° C.
The production method according to 1). (13) The diffusion preventing layer is made of silicon oxide or silicon nitride (11) or (12).
Production method described in 1. (14) The method according to any one of (11) to (13), further including a step of removing the diffusion prevention layer. (15) A laminate comprising a silicon substrate and a group III nitride-based compound semiconductor layer formed thereon, wherein
A stacked body, wherein the group III nitride-based compound semiconductor layer is formed in a state where a side wall of the silicon substrate is covered with a diffusion preventing layer. (16) The growth temperature of the group III nitride-based compound semiconductor is 800 to 1200 ° C.
The laminate according to 5). (17) The diffusion prevention layer is made of silicon oxide or silicon nitride (15) or (16).
3. The laminate according to item 1. (21) forming a group III nitride compound semiconductor layer on a silicon substrate, and forming the group III nitride compound semiconductor layer on the silicon substrate after forming at least one group III nitride compound semiconductor layer; Forming a silicon oxide layer on the surface not to be treated II
A method for manufacturing a group I nitride compound semiconductor device. (22) forming a group III nitride compound semiconductor layer on the silicon substrate, and selectively oxidizing the silicon substrate in the group III nitride compound semiconductor layer / silicon substrate laminate formed by the step; And a method for producing a group III nitride compound semiconductor device. (23) forming at least one group III nitride-based compound semiconductor layer on a silicon substrate; and forming the group II nitride-based compound semiconductor layer / silicon substrate stacked body on the silicon substrate on at least a side surface of the silicon substrate.
Forming a diffusion prevention layer for preventing diffusion into the group I nitride-based compound semiconductor layer. (24) The method according to (24), wherein the diffusion preventing layer is made of silicon oxide or silicon nitride. (25) The method according to (23) or (24), further comprising a step of removing the diffusion prevention layer. (51) forming a group III nitride compound semiconductor layer on a silicon substrate, and forming the group III nitride compound semiconductor layer on the silicon substrate after forming at least one group III nitride compound semiconductor layer; Forming a silicon oxide layer on the surface not to be treated. (52) forming a group III nitride compound semiconductor layer on a silicon substrate, and selectively oxidizing the silicon substrate in the group III nitride compound semiconductor layer / silicon substrate laminate formed by the step; And a method for producing a laminate comprising: (53) forming at least one group III nitride-based compound semiconductor layer on a silicon substrate; and forming the group II nitride-based compound semiconductor layer / silicon substrate laminate such that silicon is formed on at least a side surface of the silicon substrate.
Forming a diffusion prevention layer for preventing diffusion into the group I nitride-based compound semiconductor layer. (54) The method according to (53), wherein the diffusion preventing layer is made of silicon oxide or silicon nitride. (55) The method according to (53) or (5), further comprising a step of removing the diffusion prevention layer.
The production method according to 4).
【図１】本実施例の発光素子１０の構成を示した図であ
る。FIG. 1 is a diagram showing a configuration of a light emitting device 10 of the present embodiment.
【図２】同じく発光素子１０の製造方法を示した工程図
である。FIG. 2 is a process chart showing a method for manufacturing the light emitting element 10;
【図３】本発明の他の実施例の製造方法を示す工程図で
ある。FIG. 3 is a process chart showing a manufacturing method according to another embodiment of the present invention.
１０ 発光素子 １１ 基板 １２ Ａｌ層 １３ ＴｉＮ層 １４ バッファ層 １５ ｎクラッド層 １６ 発光層 １７ ｐクラッド層 １８ 拡散防止層 DESCRIPTION OF SYMBOLS 10 Light emitting element 11 Substrate 12 Al layer 13 TiN layer 14 Buffer layer 15 n clad layer 16 light emitting layer 17 p clad layer 18 diffusion prevention layer
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F041 AA41 CA03 CA04 CA05 CA33 CA34 CA40 CA46 CA49 CA57 CA64 CA65 CA66 CA77 5F045 AA04 AB14 AB17 AB18 AB32 AB33 AD12 AD13 AD14 AD15 AD16 AF03 AF11 AF13 BB06 CA10 CA12 CA13 DA53 DA54 HA12 5F049 MA01 MB07 MB12 NA08 PA03 PA04 PA20 SS03 SS10 WA03 WA05 5F073 AA72 CA07 CB04 CB07 CB19 DA05 DA06 EA29 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) 5F041 AA41 CA03 CA04 CA05 CA33 CA34 CA40 CA46 CA49 CA57 CA64 CA65 CA66 CA77 5F045 AA04 AB14 AB17 AB18 AB32 AB33 AD12 AD13 AD14 AD15 AD16 AF03 AF11 AF13 BB06 CA10 CA12 CA13 DA53 DA54 HA12 5F0 MA01 MB07 MB12 NA08 PA03 PA04 PA20 SS03 SS10 WA03 WA05 5F073 AA72 CA07 CB04 CB07 CB19 DA05 DA06 EA29
Claims (7)
した状態でIII族窒化物系化合物半導体を前記シリコン
基板の上面に成長させる、ことを特徴とするIII族窒化
物系化合物半導体素子の製造方法。1. A method of manufacturing a group III nitride-based compound semiconductor device, comprising: growing a group III nitride-based compound semiconductor on an upper surface of a silicon substrate while covering a side wall of the silicon substrate with a diffusion preventing layer. Method.
温度は８００〜１２００℃である、ことを特徴とする請
求項１に記載の製造方法。2. The method according to claim 1, wherein a growth temperature of the group III nitride-based compound semiconductor is 800 to 1200 ° C.
シリコンからなる、ことを特徴とする請求項１又は２に
記載の製造方法。3. The method according to claim 1, wherein the diffusion preventing layer is made of silicon oxide or silicon nitride.
に含まれる、ことを特徴とする請求項１〜３のいずれか
に記載の製造方法。4. The method according to claim 1, further comprising removing the diffusion preventing layer.
物系化合物半導体層を有する素子であって、 前記III族窒化物系化合物半導体層は前記シリコン基板
の側壁を拡散防止層で被覆した状態で形成されたもので
ある、ことを特徴とするIII族窒化物系化合物半導体素
子。5. An element having a group III nitride compound semiconductor layer formed on a silicon substrate, wherein the group III nitride compound semiconductor layer covers a side wall of the silicon substrate with a diffusion preventing layer. A group III nitride-based compound semiconductor device, characterized by being formed by:
温度は８００〜１２００℃である、ことを特徴とする請
求項５に記載の素子。6. The device according to claim 5, wherein a growth temperature of the group III nitride-based compound semiconductor is 800 to 1200 ° C.
シリコンからなる、ことを特徴とする請求項５又は６に
記載の素子。7. The device according to claim 5, wherein the diffusion preventing layer is made of silicon oxide or silicon nitride.
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| JP9229199A JP3760663B2 (en) | 1999-03-31 | 1999-03-31 | Method for producing group III nitride compound semiconductor device |
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|---|---|---|---|
| JP9229199A JP3760663B2 (en) | 1999-03-31 | 1999-03-31 | Method for producing group III nitride compound semiconductor device |
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