JP2000106302A - Low-resistance chip resistor and its manufacture - Google Patents
Low-resistance chip resistor and its manufactureInfo
- Publication number
- JP2000106302A JP2000106302A JP10275158A JP27515898A JP2000106302A JP 2000106302 A JP2000106302 A JP 2000106302A JP 10275158 A JP10275158 A JP 10275158A JP 27515898 A JP27515898 A JP 27515898A JP 2000106302 A JP2000106302 A JP 2000106302A
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- Japan
- Prior art keywords
- electrode layer
- film
- resistance
- low
- chip resistor
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- Non-Adjustable Resistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電子回路において電
流検出センサーとして組み込まれるように、低抵抗値と
安定した良好なＴＣＲ（抵抗温度特性、以下同じ）を備
えてなる低抵抗チップ抵抗器とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-resistance chip resistor having a low resistance value and a stable and good TCR (resistance temperature characteristic, the same applies hereinafter) so as to be incorporated as a current detection sensor in an electronic circuit, and a low-resistance chip resistor. It relates to a manufacturing method.
【０００２】[0002]
【従来の技術】従来、低抵抗化を目的とした低抵抗チッ
プ抵抗器としては、絶縁基板と、該絶縁基板上に形成さ
れる表電極と、該表電極を跨ぐように形成される抵抗膜
と、該抵抗膜を被覆する保護膜とを備えてなるものが一
般に知られている（特開平９−１８０９０３号公報参
照）。2. Description of the Related Art Conventionally, as a low-resistance chip resistor for the purpose of lowering resistance, an insulating substrate, a front electrode formed on the insulating substrate, and a resistive film formed so as to straddle the front electrode are known. And a protective film for covering the resistive film are generally known (see Japanese Patent Application Laid-Open No. 9-180903).
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
従来の低抵抗チップ抵抗器においては、抵抗膜本来のＥ
ＳＤ(耐静電気破壊)特性等の電気的特性や、ある程度の
低抵抗値範囲が確保されているものの、安定した良好な
ＴＣＲが確保できているとは必ずしも言えない。この従
来の低抵抗チップ抵抗器において具体的に得られている
抵抗値は１００ｍΩ〜数Ωであり、ＴＣＲにあっては２
００ｐｐｍ／℃以上にとどまっているのが実状である。However, in the above-mentioned conventional low-resistance chip resistor, the resistance E of the resistive film is reduced.
Although electrical characteristics such as SD (electrostatic breakdown resistance) characteristics and a certain low resistance value range are secured, a stable and good TCR cannot always be secured. The resistance value specifically obtained in this conventional low-resistance chip resistor is 100 mΩ to several Ω, and in the case of the TCR, it is 2 mΩ.
Actually, it stays at 00 ppm / ° C. or more.
【０００４】本発明は従来の技術の欠点に着目し、これ
を解決せんとしたものであり、その目的は、従来得られ
ていた各種特性を維持しつつ、低抵抗化とより良好なＴ
ＣＲの確保とを可能にする低抵抗チップ抵抗器及びその
製造方法を提供することにある。The present invention focuses on the disadvantages of the prior art and seeks to solve them. The object of the present invention is to reduce the resistance and improve the better T while maintaining the various characteristics conventionally obtained.
An object of the present invention is to provide a low-resistance chip resistor capable of securing a CR and a method of manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】本発明は上記の目的に鑑
みてなされたものであり、その要旨とするところは、絶
縁基板と、該絶縁基板上に形成される一対の表電極と、
該表電極を跨ぐように形成される抵抗膜と、該抵抗膜を
被覆する保護膜とを備えてなる低抵抗チップ抵抗器であ
って、上記表電極が、Ａｇ・Ｐｄ系メタルグレーズ下層
膜及び／又はＡｇ系メタルグレーズ上層膜からなる第１
表電極層と、該第１表電極層上に並設される膜厚３０μ
ｍ以上のＣｕめっき膜からなる第２表電極層とを含むこ
とを特徴とする低抵抗チップ抵抗器にある。Means for Solving the Problems The present invention has been made in view of the above-mentioned object, and its gist is to provide an insulating substrate, a pair of front electrodes formed on the insulating substrate,
A low-resistance chip resistor comprising a resistance film formed so as to straddle the surface electrode and a protective film covering the resistance film, wherein the surface electrode includes an Ag / Pd-based metal glaze underlayer film, And / or a first layer comprising an Ag-based metal glaze upper layer film
A surface electrode layer and a film thickness of 30 μ juxtaposed on the first surface electrode layer
and a second front electrode layer made of a Cu plating film having a thickness of at least m.
【０００６】この態様によれば、低抵抗チップ抵抗器の
表電極において、Ａｇ・Ｐｄ系メタルグレーズ下層膜及
び／又はＡｇ系メタルグレーズ上層膜からなる第１表電
極層と、該第１表電極層上に並設される膜厚３０μｍ以
上のＣｕめっき膜からなる第２表電極層とを採用したの
で、上述した第１表電極層と第２表電極層とが相俟っ
て、従来得られていた各種特性を維持しつつ、低抵抗化
とより良好なＴＣＲ（小さなＴＣＲ）の確保を可能にす
る。According to this aspect, in the front electrode of the low-resistance chip resistor, the first front electrode layer made of the Ag / Pd-based metal glaze lower layer film and / or the Ag-based metal glaze upper layer film; Since the second surface electrode layer made of a Cu plating film having a film thickness of 30 μm or more is juxtaposed on the layer, the first surface electrode layer and the second surface electrode layer described above are combined with each other to obtain the conventional structure. While maintaining various characteristics, it is possible to reduce the resistance and secure a better TCR (small TCR).
【０００７】本発明の他の要旨は、上記低抵抗チップ抵
抗器を製造する方法であって、上記第２表電極層を電気
めっき法により形成することとし、第２表電極層の形成
に先立って、集合絶縁基板の縦横分割溝の部分、並びに
第２表電極層を形成する範囲を除く部分を被覆するよう
にめっきレジストを形成する工程と、第２表電極層の形
成後に、めっきレジストを除去する工程と、を含むこと
を特徴とする低抵抗チップ抵抗器の製造方法にある。Another aspect of the present invention is a method of manufacturing the low-resistance chip resistor, wherein the second surface electrode layer is formed by electroplating, and prior to the formation of the second surface electrode layer. Forming a plating resist so as to cover the portion of the vertical and horizontal dividing grooves of the collective insulating substrate, and the portion excluding the area where the second front electrode layer is formed; and forming the plating resist after the formation of the second front electrode layer. And a step of removing the low-resistance chip resistor.
【０００８】この態様によれば、低抵抗チップ抵抗器を
製造する方法において、第２表電極層を電気めっき法に
より形成することとし、第２表電極層の形成に先立っ
て、集合絶縁基板の縦横分割溝の部分、並びに第２表電
極層を形成する範囲を除く部分を被覆するようにめっき
レジストを形成する工程と、第２表電極層の形成後に、
めっきレジストを除去する工程とを採用したので、比較
的厚いCuめっき膜からなる第２表電極層が集合絶縁基板
の縦横分割溝上に形成されることがなく、集合絶縁基板
の分割時におけるバリ（欠け）の発生を極力防止するこ
とができる。According to this aspect, in the method of manufacturing a low-resistance chip resistor, the second front electrode layer is formed by electroplating, and prior to the formation of the second front electrode layer, the collective insulating substrate is formed. A step of forming a plating resist so as to cover the portion of the vertical and horizontal dividing grooves, and a portion excluding a range where the second front electrode layer is formed; and, after forming the second front electrode layer,
Since the step of removing the plating resist is adopted, the second front electrode layer made of a relatively thick Cu plating film is not formed on the vertical and horizontal division grooves of the collective insulating substrate, and the burr ( Chipping) can be prevented as much as possible.
【０００９】[0009]
【発明の実施の形態】本発明において採用する低抵抗チ
ップ抵抗器の持つ個々の平面サイズは、長さ方向（以
下、Ｌと称す）：１．６ｍｍ×幅方向（以下、Ｗと称
す）：０．８ｍｍ、Ｌ：２．０ｍｍ×Ｗ：１．２５ｍ
ｍ、L：３．２ｍｍ×Ｗ：１．６ｍｍ、Ｌ：３．５ｍｍ
×Ｗ：２．５ｍｍ、Ｌ：５．０ｍｍ×Ｗ：２．５ｍｍ、
Ｌ：６．３×Ｗ３．２ｍｍ等の態様がある。DESCRIPTION OF THE PREFERRED EMBODIMENTS Each low-resistance chip resistor employed in the present invention has a plane size in a length direction (hereinafter, referred to as L): 1.6 mm × width direction (hereinafter, referred to as W): 0.8 mm, L: 2.0 mm x W: 1.25 m
m, L: 3.2 mm x W: 1.6 mm, L: 3.5 mm
× W: 2.5 mm, L: 5.0 mm × W: 2.5 mm,
L: There are aspects such as 6.3 × W3.2 mm.
【００１０】また、上記Ｃｕめっき膜からなる第２表電
極層は、第１表電極層上に３０μｍ以上の膜厚で形成さ
れるが、低抵抗チップ抵抗器の個々の平面サイズを考慮
すれば、現実的には３０μｍ〜４０μｍ程度の膜厚とす
ることが望ましい。The second surface electrode layer made of the above-mentioned Cu plating film is formed on the first surface electrode layer with a thickness of 30 μm or more, but considering the individual plane size of the low-resistance chip resistor. Actually, it is desirable to set the film thickness to about 30 μm to 40 μm.
【００１１】[0011]
【実施例】以下、本発明の実施例を添付図面に基づいて
説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【００１２】図１に示す低抵抗チップ抵抗器は、絶縁基
板１と、該絶縁基板１に設けられた一対の表電極（２，
５，７）及び裏電極２'と、該表電極を跨ぐように形成
された抵抗膜３と、該抵抗膜３を被覆するように設けら
れた保護膜（４，９）と、上記基板端面に形成される端
面電極１０及び端面めっき膜１１と、を備えてなる。The low-resistance chip resistor shown in FIG. 1 has an insulating substrate 1 and a pair of front electrodes (2, 2) provided on the insulating substrate 1.
5, 7) and a back electrode 2 ', a resistive film 3 formed so as to straddle the front electrode, a protective film (4, 9) provided to cover the resistive film 3, And an end surface plating film 11 formed on the substrate.
【００１３】絶縁基板１は、アルミナ等からなる集合基
板を縦横分割溝１ａ，１ｂに沿って個片状に分割される
ことによって独立した単体チップである。The insulating substrate 1 is an independent single chip obtained by dividing an aggregate substrate made of alumina or the like into individual pieces along vertical and horizontal dividing grooves 1a and 1b.
【００１４】表電極（２，５，７）は、該基板１の上面
に形成された膜厚１０μｍ以下の一対のＡｇ・Ｐｄ系メ
タルグレーズ下層膜２及びＡｇ系メタルグレーズ上層膜
５からなる第１表電極層２と、該第１表電極層上に形成
された膜厚３０μm以上のＣｕめっき膜７からなる第２
表電極層によって構成されている。ここでは、Ａｇ・Ｐ
ｄメタルグレーズ２及びＡｇ系メタルグレーズ５の両者
を採用しているが、何れか一方のみを採用する態様とし
てもよい。尚、基板１の下面には、１０μｍ以下の一対
のＡｇ系メタルグレーズ２'からなる裏電極が形成され
ている。The front electrode (2, 5, 7) is formed of a pair of Ag / Pd-based metal glaze lower film 2 and Ag-based metal glaze upper film 5 having a thickness of 10 μm or less formed on the upper surface of the substrate 1. A second electrode comprising a first surface electrode layer 2 and a Cu plating film 7 having a thickness of 30 μm or more formed on the first surface electrode layer;
It is composed of a front electrode layer. Here, Ag ・ P
Although both the d-metal glaze 2 and the Ag-based metal glaze 5 are employed, only one of them may be employed. A back electrode made of a pair of Ag-based metal glazes 2 ′ of 10 μm or less is formed on the lower surface of the substrate 1.
【００１５】抵抗膜３は、図示するように、上述した第
１表電極層のＡｇ・Ｐｄメタルグレーズ下層膜２及びＡ
ｇ系メタルグレーズ上層膜５によって各端部が挟み込ま
れるように配置されている。ここで、上記表電極におい
ては、第１表電極層の下層膜、上層膜、及び第２電極層
の順に面積抵抗が低くなるように配置してあり、結果と
して表電極の抵抗値が抵抗膜の抵抗値に影響することが
ないように低抵抗化を配慮している。As shown in the figure, the resistance film 3 is composed of the Ag / Pd metal glaze lower film 2 and A
The g-type metal glaze upper layer film 5 is arranged such that each end is sandwiched therebetween. Here, in the above-mentioned front electrode, the lower layer film, the upper layer film, and the second electrode layer of the first front electrode layer are arranged so that the sheet resistance becomes lower in this order. Consideration is given to lowering the resistance so as not to affect the resistance value.
【００１６】また、保護膜（４，９）は、抵抗膜３の露
出部分を被覆するように形成される第１保護コート４
と、該第１保護コート４上からトリミングされた抵抗膜
３を被覆するように形成される第２保護コート９とから
なる。The protective films (4, 9) are formed so as to cover exposed portions of the resistive film 3 with a first protective coat 4 formed thereon.
And a second protective coat 9 formed so as to cover the resistance film 3 trimmed from the first protective coat 4.
【００１７】基板１の各端面に形成された端面電極１０
は、Ａｇ等を含む導電性樹脂塗料からなり、絶縁基板と
の密着性を確保し、上述の表電極と裏電極との電気的接
続を確保している。An end face electrode 10 formed on each end face of the substrate 1
Is made of a conductive resin paint containing Ag or the like, secures adhesion to the insulating substrate, and secures electrical connection between the front electrode and the back electrode.
【００１８】また、上記端面電極１０と表電極及び裏電
極の全体を被覆するように、端面めっき膜１１として、
下層Ｃｕめっき１１ａと、中層Ｎｉめっき１１ｂと、上
層はんだめっき１１ｃとを施している。尚、上記下層Ｃ
ｕめっきの形成は、めっき膜１１の抵抗値を低く保つよ
うに作用する。Further, an end plating film 11 is formed so as to cover the entire surface of the end electrode 10, the front electrode, and the back electrode.
The lower Cu plating 11a, the middle Ni plating 11b, and the upper solder plating 11c are applied. The lower layer C
The formation of the u plating acts to keep the resistance value of the plating film 11 low.
【００１９】以下、上述した低抵抗チップ抵抗器１０の
製造方法について図２〜図５を参照して説明する。Hereinafter, a method of manufacturing the above-described low-resistance chip resistor 10 will be described with reference to FIGS.
【００２０】まず工程Ａにおいて、縦横分割溝１ａ，１
ｂを備えた集合基板の区画域毎に、Ａｇ・Ｐｄ系メタル
グレーズ（重量比 Ａｇ；７０ｗｔ％，Ｐｄ；３０ｗｔ
％）をその上面に印刷・乾燥（８５０℃）することによ
り膜厚１０μm以下の一対の第１表電極層下層膜２を形
成すると共に、Ａｇ系メタルグレーズをその下面に印刷
・乾燥（８５０℃）することにより膜厚１０μm以下の
一対の裏電極２'を形成する。First, in step A, vertical and horizontal dividing grooves 1a, 1
Ag / Pd-based metal glaze (weight ratio: Ag; 70 wt%, Pd; 30 wt%)
%) Is printed on the upper surface thereof and dried (850 ° C.) to form a pair of first surface electrode layer lower layer films 2 having a thickness of 10 μm or less, and an Ag-based metal glaze is printed and dried on the lower surface thereof (850 ° C.). ) To form a pair of back electrodes 2 ′ having a thickness of 10 μm or less.
【００２１】また、工程A後の工程Ｂにおいて、上記第
１電極層のＡｇ・Ｐｄ系メタルグレーズ下層膜２を跨ぐ
ようにＡｇ・Ｐｄ系メタルグレーズ（重量比 Ａｇ；４
５ｗｔ％，Ｐｄ；５５ｗｔ％）を印刷・焼成（８５０
℃）することにより膜厚８μｍ〜２５μｍの抵抗膜３を
形成する。ここで抵抗膜３は、単層の態様に限られず、
印刷・焼成を繰り返して多層化の態様とすることができ
るほか、第１表電極層の上層膜又は下層膜による電極間
隔を調整することにより抵抗膜の抵抗値を所要の値に設
定するといった態様とすることができる。In the step B after the step A, the Ag / Pd-based metal glaze (weight ratio: Ag; 4) is formed so as to straddle the Ag / Pd-based metal glaze underlayer film 2 of the first electrode layer.
5 wt%, Pd; 55 wt%) is printed and fired (850).
C.) to form a resistance film 3 having a thickness of 8 μm to 25 μm. Here, the resistance film 3 is not limited to a single-layer mode,
Printing and baking can be repeated to form a multi-layered mode, and the resistance value of the resistive film can be set to a required value by adjusting the electrode interval between the upper layer film and the lower layer film of the first front electrode layer. It can be.
【００２２】上述したように、第１表電極層下層膜２及
び抵抗膜３におけるＡｇ・Pd系メタルグレーズの重量比
を選択することにより、低抵抗化並びに小さなＴＣＲの
より簡易な確保に寄与することができる。As described above, by selecting the weight ratio of the Ag / Pd-based metal glaze in the lower layer film 2 of the first front electrode layer and the resistance film 3, it contributes to lowering the resistance and ensuring a small TCR more easily. be able to.
【００２３】次いで、工程Ｂ後の工程Ｃにおいて、Ａｇ
系メタルグレーズを印刷・焼成（６００℃）することに
より膜厚１０μｍ以下の第１表電極層上層膜５を形成す
る。Next, in step C after step B, Ag
The first surface electrode layer upper layer film 5 having a thickness of 10 μm or less is formed by printing and baking (600 ° C.) the system metal glaze.
【００２４】更に、工程Ｃ後の工程Ｄにおいて、第１保
護コート４として硼珪酸鉛ガラスペーストを印刷・焼成
（６００℃）する。Further, in a step D after the step C, a lead borosilicate glass paste is printed and fired (600 ° C.) as the first protective coat 4.
【００２５】更にまた、工程Ｄ後の工程Ｅにおいて、図
４に示すように、めっきレジスト６としてピッチ系合成
樹脂を集合基板の縦横分割溝１ａ，１ｂの部分及び第２
表電極層７を形成する範囲を除く部分に印刷・硬化（２
００℃）する。Further, in a step E after the step D, as shown in FIG. 4, a pitch-based synthetic resin is used as the plating resist 6 in the vertical and horizontal dividing grooves 1a and 1b of the collective substrate and the second resist.
Printing / curing (2) except the area where the front electrode layer 7 is formed
00 ° C).
【００２６】そして、工程Ｅ後の工程Ｆにおいて、上記
第２表電極層７を形成する範囲の表面を希塩酸液で粗化
・洗浄する。この粗化・洗浄によれば、良好な電気的接
触と密着性とが確保され、抵抗膜と電極との良好な電流
路が確保される。In the step F after the step E, the surface of the area where the second front electrode layer 7 is to be formed is roughened and washed with a dilute hydrochloric acid solution. According to this roughening / cleaning, good electrical contact and adhesion are secured, and a good current path between the resistive film and the electrode is secured.
【００２７】工程F後の工程Ｇにおいては、集合絶縁基
板の状態で第１表電極層上層膜５上に電気めっき法によ
り膜厚３０μｍ以上のＣｕめっき膜からなる第２表電極
層７を形成する。In the step G after the step F, the second surface electrode layer 7 made of a Cu plating film having a thickness of 30 μm or more is formed on the first surface electrode layer upper layer film 5 by electroplating in the state of the collective insulating substrate. I do.
【００２８】また、工程G後の工程Ｈにおいては、剥離
材を用いてめっきレジストを除去する。In step H after step G, the plating resist is removed using a release material.
【００２９】更に、工程H後の工程Ｉにおいては、上記
第１保護コート４上より抵抗膜３をレーザートリミング
することによって所要の抵抗値に調整する。Further, in step I after step H, the resistance film 3 is adjusted to a required resistance value by laser trimming the resistive film 3 from above the first protective coat 4.
【００３０】更にまた、工程I後の工程Ｊにおいては、
上記工程のトリミング跡８を被覆するようにエポキシ系
又はフェノール変成エポキシ系等の合成樹脂塗料を印刷
・硬化（２００℃）することにより上記第２保護コート
９を形成する。Further, in step J after step I,
The second protective coat 9 is formed by printing and curing (200 ° C.) a synthetic resin paint such as an epoxy-based or phenol-modified epoxy-based so as to cover the trimming marks 8 in the above process.
【００３１】工程J後の工程Ｋにおいて、集合絶縁基板
１を縦分割溝１ａに沿って短冊状に分割する。In a step K after the step J, the collective insulating substrate 1 is divided into strips along the vertical division grooves 1a.
【００３２】そして、工程K後の工程Ｌにおいては、Ａ
ｇ等を含有する導電性樹脂材料を印刷・硬化（２００
℃）することにより端面電極１０を形成する。Then, in step L after step K, A
Printing and curing conductive resin material containing g
C.) to form the end face electrode 10.
【００３３】工程Ｌ後の工程Ｍにおいて、短冊状に分割
された集合絶縁基板１を横分割溝１ｂに沿って個片状に
更に分割することにより単体チップを得る。In a step M after the step L, the collective insulating substrate 1 divided into strips is further divided into individual pieces along the horizontal division grooves 1b to obtain a single chip.
【００３４】最後に、工程Ｍ後の工程Ｎにおいて、電気
めっき法により下層のＣｕめっき１１ａ、中層のニッケ
ルめっき１１ｂ、及びはんだめっき１１ｃとからなるめ
っき膜１１を形成し、本発明にかかる低抵抗チップ抵抗
器の製造が完了する。尚、上述した工程Ａと工程Ｂと
は、工程順序を逆にして実施することもできる。Finally, in a step N after the step M, a plating film 11 composed of a lower Cu plating 11a, a middle nickel plating 11b, and a solder plating 11c is formed by an electroplating method. The manufacture of the chip resistor is completed. Step A and step B described above can be performed in the reverse order of the steps.
【００３５】上述した実施例において得られた低抵抗チ
ップ抵抗器は、抵抗値範囲を２０mΩ程度にまで下げる
ことができ、図６に示すようにＴＣＲを７５ｐｐｍ／℃
〜１００ｐｐｍ／℃に抑制することができた。The low-resistance chip resistor obtained in the above-described embodiment can reduce the resistance value range to about 20 mΩ, and has a TCR of 75 ppm / ° C. as shown in FIG.
-100 ppm / ° C.
【００３６】尚、図６は、上述した実施例におけるＬ：
２．０ｍｍ×Ｗ：１．２５ｍｍの平面サイズを有する単
体チップのものであって、公称抵抗値が２５mΩ、抵抗
値許容差±１％のものを試料とした低抵抗チップ抵抗器
において、２０℃を基準温度として、基準温度より４０
℃高い試験温度と、基準温度より３０℃低い試験温度と
で測定したときのＣｕめっき膜からなる第２表電極層の
膜厚及びＴＣＲの関係を示したグラフである。FIG. 6 is a graph showing L:
2.0 mm × W: 20 ° C. in a single chip having a plane size of 1.25 mm, having a nominal resistance of 25 mΩ and a tolerance of ± 1%. Is set as a reference temperature, and is 40
4 is a graph showing the relationship between the thickness and the TCR of the second front electrode layer made of a Cu plating film when measured at a test temperature higher by ° C and a test temperature lower by 30 ° C than a reference temperature.
【００３７】[0037]
【発明の効果】本発明の低抵抗チップ抵抗器は、低抵抗
チップ抵抗器の表電極において、Ａｇ・Ｐｄ系メタルグ
レーズ下層膜及び／又はＡｇ系メタルグレーズ上層膜か
らなる第１表電極層と、該第１表電極層上に並設される
膜厚３０μｍ以上のＣｕめっき膜からなる第２表電極層
とを採用する態様としたので、上述した第１表電極層と
第２表電極層とが相俟って、従来得られていた各種特性
を維持しつつ、低抵抗化とより良好なＴＣＲ（小さなTC
R）の確保を可能にするといった効果を奏する。According to the low resistance chip resistor of the present invention, the surface electrode of the low resistance chip resistor includes a first surface electrode layer comprising an Ag / Pd-based metal glaze lower layer film and / or an Ag-based metal glaze upper layer film. Since the second surface electrode layer made of a Cu plating film having a thickness of 30 μm or more and arranged in parallel on the first surface electrode layer is adopted, the first surface electrode layer and the second surface electrode layer described above are adopted. In combination with this, while maintaining the various characteristics that have been obtained in the past, lower resistance and better TCR (small TC
R) can be secured.
【００３８】また本発明の低抵抗チップ抵抗器の製造方
法は、低抵抗チップ抵抗器を製造する方法において、第
２表電極層を電気めっき法により形成することとし、第
２表電極層の形成に先立って、集合絶縁基板の縦横分割
溝の部分、並びに第２表電極層を形成する範囲を除く部
分を被覆するようにめっきレジストを形成する工程と、
第２表電極層の形成後に、めっきレジストを除去する工
程とを採用する態様としたので、比較的厚膜のCuめっき
膜からなる第２表電極層が集合絶縁基板の縦横分割溝上
に形成されることがなく、集合絶縁基板の分割時におけ
るバリ（欠け）の発生を極力防止することができるとい
った効果を奏する。In the method of manufacturing a low-resistance chip resistor according to the present invention, in the method of manufacturing a low-resistance chip resistor, the second surface electrode layer is formed by electroplating. Prior to forming a plating resist so as to cover the portion of the vertical and horizontal dividing grooves of the collective insulating substrate, as well as the portion excluding the range for forming the second front electrode layer,
After the formation of the second front electrode layer, the step of removing the plating resist is adopted. Therefore, the second front electrode layer made of a relatively thick Cu plating film is formed on the vertical and horizontal division grooves of the collective insulating substrate. Therefore, it is possible to minimize the occurrence of burrs (chips) when dividing the collective insulating substrate.
【図１】本発明の低抵抗チップ抵抗器の一実施例を示す
概略縦断面図である。FIG. 1 is a schematic vertical sectional view showing one embodiment of a low-resistance chip resistor of the present invention.
【図２】図１の低抵抗チップ抵抗器の製造方法を示す流
れ図である。FIG. 2 is a flowchart illustrating a method of manufacturing the low-resistance chip resistor of FIG. 1;
【図３】図２の工程B時の製造状況を示す概略平面図で
ある。FIG. 3 is a schematic plan view showing a manufacturing state in a step B of FIG. 2;
【図４】図２の工程E時の製造状況を示す概略断面図で
ある。FIG. 4 is a schematic cross-sectional view showing a manufacturing state in a process E of FIG. 2;
【図５】図２の工程Ｊ時の製造状況を示す概略断面図で
ある。FIG. 5 is a schematic cross-sectional view showing a manufacturing state at a time of a process J in FIG. 2;
【図６】本発明におけるＣｕめっき膜からなる第２表電
極層の膜厚と低抵抗チップ抵抗器のＴＣＲの関係を示す
グラフである。FIG. 6 is a graph showing the relationship between the thickness of a second front electrode layer made of a Cu plating film and the TCR of a low-resistance chip resistor according to the present invention.
１ 絶縁基板 ２ 第１表電極層下層膜 ２' 裏電極 ３ 抵抗膜 ４ 第１保護コート ５ 第１表電極層上層膜 ６ めっきレジスト ７ 第２表電極層 ８ トリミング跡 ９ 第２保護コート １０ 端面電極 １１ 端面めっき膜 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 1st front electrode layer lower layer film 2 'back electrode 3 Resistive film 4 1st protective coat 5 1st front electrode layer upper layer film 6 Plating resist 7 2nd front electrode layer 8 Trimming trace 9 2nd protective coat 10 End face Electrode 11 Edge plating film
Claims (2)
一対の表電極と、該表電極を跨ぐように形成される抵抗
膜と、該抵抗膜を被覆する保護膜とを備えてなる低抵抗
チップ抵抗器であって、 上記表電極が、Ａｇ・Ｐｄ系メタルグレーズ下層膜及び
／又はＡｇ系メタルグレーズ上層膜からなる第１表電極
層と、該第１表電極層上に並設される膜厚３０μｍ以上
のＣｕめっき膜からなる第２表電極層とを含むことを特
徴とする低抵抗チップ抵抗器。An insulating substrate, a pair of front electrodes formed on the insulating substrate, a resistive film formed to extend over the front electrode, and a protective film covering the resistive film. A low-resistance chip resistor, wherein the front electrode is provided in parallel with a first front electrode layer including an Ag / Pd-based metal glaze lower layer film and / or an Ag-based metal glaze upper layer film, and on the first front electrode layer. And a second electrode layer made of a Cu plating film having a thickness of 30 μm or more.
製造する方法であって、 上記第２表電極層を電気めっき法により形成することと
し、 第２表電極層の形成に先立って、集合絶縁基板の縦横分
割溝の部分、並びに第２表電極層を形成する範囲を除く
部分を被覆するようにめっきレジストを形成する工程
と、 第２表電極層の形成後に、めっきレジストを除去する工
程と、を含むことを特徴とする低抵抗チップ抵抗器の製
造方法。2. The method for manufacturing a low-resistance chip resistor according to claim 1, wherein the second surface electrode layer is formed by an electroplating method, prior to the formation of the second surface electrode layer. Forming a plating resist so as to cover portions of the vertical and horizontal dividing grooves of the collective insulating substrate and a portion excluding a range for forming the second surface electrode layer; and removing the plating resist after forming the second surface electrode layer. And a method of manufacturing a low-resistance chip resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10275158A JP3134067B2 (en) | 1998-09-29 | 1998-09-29 | Low resistance chip resistor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10275158A JP3134067B2 (en) | 1998-09-29 | 1998-09-29 | Low resistance chip resistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000106302A true JP2000106302A (en) | 2000-04-11 |
| JP3134067B2 JP3134067B2 (en) | 2001-02-13 |
Family
ID=17551492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10275158A Expired - Lifetime JP3134067B2 (en) | 1998-09-29 | 1998-09-29 | Low resistance chip resistor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3134067B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002064003A (en) * | 2000-08-17 | 2002-02-28 | Taiyosha Denki Kk | Chip resistor and its manufacturing method |
| JP2007173574A (en) * | 2005-12-22 | 2007-07-05 | Taiyosha Electric Co Ltd | Chip resistor |
| CN100351956C (en) * | 2001-11-28 | 2007-11-28 | 罗姆股份有限公司 | Chip resistor and method for producing the same |
| JP2009135286A (en) * | 2007-11-30 | 2009-06-18 | Taiyosha Electric Co Ltd | Chip resistor and method of manufacturing chip resistor |
-
1998
- 1998-09-29 JP JP10275158A patent/JP3134067B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002064003A (en) * | 2000-08-17 | 2002-02-28 | Taiyosha Denki Kk | Chip resistor and its manufacturing method |
| CN100351956C (en) * | 2001-11-28 | 2007-11-28 | 罗姆股份有限公司 | Chip resistor and method for producing the same |
| JP2007173574A (en) * | 2005-12-22 | 2007-07-05 | Taiyosha Electric Co Ltd | Chip resistor |
| JP2009135286A (en) * | 2007-11-30 | 2009-06-18 | Taiyosha Electric Co Ltd | Chip resistor and method of manufacturing chip resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3134067B2 (en) | 2001-02-13 |
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