JP2000068320A - Semiconductor device and method for preventing electrostatic breakdown thereof - Google Patents

Semiconductor device and method for preventing electrostatic breakdown thereof

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Publication number
JP2000068320A
JP2000068320A JP10238692A JP23869298A JP2000068320A JP 2000068320 A JP2000068320 A JP 2000068320A JP 10238692 A JP10238692 A JP 10238692A JP 23869298 A JP23869298 A JP 23869298A JP 2000068320 A JP2000068320 A JP 2000068320A
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JP
Japan
Prior art keywords
semiconductor device
pad
probe
static electricity
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10238692A
Other languages
Japanese (ja)
Other versions
JP3769128B2 (en
Inventor
Hitoshi Kurusu
整 久留須
Hiroyuki Hoshi
裕之 星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
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Filing date
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23869298A priority Critical patent/JP3769128B2/en
Publication of JP2000068320A publication Critical patent/JP2000068320A/en
Application granted granted Critical
Publication of JP3769128B2 publication Critical patent/JP3769128B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01082—Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent static electricity from flowing into an inner circuit even if static electricity is charged to a probe by constituting an electrode pad with a plane pad part and an air bridge part which is connected to the pad part and crosses the pattern wiring of the inner circuit with a prescribed gap. SOLUTION: A probe 32 grounded to the other end is brought into contact with a pad part 22. Then, a probe 30 whose other end is connected to a test device 31 and which applies power voltage for test Vcc to a DC pad 4 is brought into contact with an air bridge part 23. Static electricity charged to the probe 30 is discharged through the probe 32. Then, the probe 30 is pressed to a substrate 10-side, and an air bridge part 23 is brought into contact with a pattern wiring 21. Thus, the probe 30 and the pattern wiring 21 are electrically connected. Even if static electricity is charged to the probes of the test device and the bonding device, static electricity is prevented from flowing into an inner circuit.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置、特に
半導体装置の電極パッドの構成に関する。The present invention relates to a semiconductor device, and more particularly to a structure of an electrode pad of the semiconductor device.

【０００２】[0002]

【従来の技術】図８は、従来の高周波装置で使用される
半導体装置１００の機能ブロック図である。半導体装置
１００は、高周波信号の入力用のＲＦ入力パッド１０
１、ＲＦ入力パッド１０１より入力された高周波信号を
処理するＲＦ回路１０２、電源電圧Ｖｃｃの入力用のＤ
Ｃパッド１０３、複数のトランジスタで構成されるトラ
ンジスタ回路１０５、上記ＤＣパッド１０３より入力さ
れる電源電圧Ｖｃｃに対して降圧等の処理を施し、処理
後の電源電圧Ｖｃｃを上記トランジスタ回路１０５の各
トランジスタのゲートに印加するＤＣ回路１０４、トラ
ンジスタ回路１０５から出力される信号に対して所定の
処理を施して高周波信号を出力するＲＦ回路１０６、及
び、ＲＦ回路１０６より出力される高周波信号の出力用
のＲＦ出力パッド１０７で構成される。2. Description of the Related Art FIG. 8 is a functional block diagram of a semiconductor device 100 used in a conventional high-frequency device. The semiconductor device 100 includes an RF input pad 10 for inputting a high-frequency signal.
1. RF circuit 102 for processing a high-frequency signal input from RF input pad 101, D for inputting power supply voltage Vcc
The power supply voltage Vcc input from the DC pad 103 is subjected to processing such as step-down, and the processed power supply voltage Vcc is applied to each transistor of the transistor circuit 105. A DC circuit 104 applied to the gate of the RF circuit 106, an RF circuit 106 that performs predetermined processing on a signal output from the transistor circuit 105 and outputs a high-frequency signal, and an It comprises an RF output pad 107.

【０００３】上記構成の半導体装置１００は、樹脂封止
される前に、テスト装置によって特性テストや動作テス
トが行われる。上記特性テストや動作テストでは、電源
供給用のＤＣパッド１０３や高周波信号の入力用のＲＦ
入力パッド１０１に、テスト装置のプローブを接触さ
せ、該プローブより駆動電圧やテストパターン信号等を
入力し、対応する電極パッド（例えばＲＦ出力パッド１
０７）より検出される電流、電圧又は信号を調べる。Before the semiconductor device 100 having the above configuration is sealed with a resin, a characteristic test and an operation test are performed by a test device. In the characteristic test and the operation test, the DC pad 103 for supplying power and the RF for inputting a high-frequency signal are used.
A probe of a test apparatus is brought into contact with the input pad 101, and a driving voltage, a test pattern signal, and the like are input from the probe, and a corresponding electrode pad (for example, the RF output pad 1)
07) Check the detected current, voltage or signal.

【０００４】[0004]

【発明が解決しようとする課題】図９は、上記半導体装
置１００が備えるＲＦ入力パッド１０１、ＤＣパッド１
０３、又は、ＲＦ出力パッド１０７に対して、テスト装
置１３１のプローブ１３０を接触させた状態を示す図で
ある。テスト装置１３１のプローブ１３０に静電気が帯
電していると、該プローブ１３０をＲＦ入力パッド１０
１、ＤＣパッド１０３、又は、ＲＦ出力パッド１０７に
接触させた瞬間に、半導体装置内の回路に大きな電圧が
印加され、トランジスタ等の回路素子が破壊されること
がある。上記の現象は、半導体装置１００をリードフレ
ームにワイヤボンディングする際に、ボンディング装置
のキャピラリに静電気が帯電していた場合にも生じる。FIG. 9 shows an RF input pad 101 and a DC pad 1 provided in the semiconductor device 100.
FIG. 3 is a diagram showing a state where a probe 130 of the test apparatus 131 is brought into contact with the RF output pad 107. When the probe 130 of the test apparatus 131 is charged with static electricity, the probe 130 is connected to the RF input pad 10.
1. At the moment when the semiconductor device contacts the DC pad 103 or the RF output pad 107, a large voltage is applied to a circuit in the semiconductor device, and a circuit element such as a transistor may be destroyed. The above phenomenon also occurs when the semiconductor device 100 is wire-bonded to a lead frame when static electricity is charged in the capillary of the bonding device.

【０００５】本発明の目的は、テスト装置のプローブや
ボンディング装置のプローブに静電気が帯電している場
合であっても、内部の回路に静電気が流れ込むことを防
止することのできる構成の電極パッドを備える半導体装
置を提供することである。An object of the present invention is to provide an electrode pad having a configuration capable of preventing static electricity from flowing into an internal circuit even when static electricity is charged to a probe of a test apparatus or a probe of a bonding apparatus. It is to provide a semiconductor device provided with.

【０００６】[0006]

【課題を解決するための手段】本発明の第１の半導体装
置は、１以上の電極パッドを供える半導体装置におい
て、上記電極パッドは、平面のパッド部と、該パッド部
に接続され、所定の間隙をもって半導体装置の内部回路
のパターン配線と交差するエアーブリッジ部とで構成さ
れることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device having one or more electrode pads, wherein the electrode pads are connected to a flat pad portion and a predetermined pad portion. The semiconductor device is characterized by comprising an air bridge section intersecting with a pattern wiring of an internal circuit of the semiconductor device with a gap.

【０００７】上記第１の半導体装置の静電破壊の防止方
法は、電極パッドに外部処理装置（テスト装置、ボンデ
ィング装置）の導電性部材（プローブ、キャピラリ）を
接触させる際に、他端の接地されたプローブをパッド部
に接触させるステップと、外部処理装置の導電性部材を
エアーブリッジ部に接触させるステップと、外部処理装
置の導電性部材を押し下げ、エアーブリッジ部をパター
ン配線に接触させるステップと、パッド部に接触させて
いる上記他端の接地されたプローブを引き離すステップ
とからなることを特徴とする。In the first method for preventing electrostatic breakdown of a semiconductor device, when a conductive member (probe, capillary) of an external processing device (test device, bonding device) is brought into contact with an electrode pad, the other end is grounded. Contacting the probe with the pad portion, contacting the conductive member of the external processing device with the air bridge portion, pressing down the conductive member of the external processing device, and contacting the air bridge portion with the pattern wiring. Separating the grounded probe at the other end which is in contact with the pad portion.

【０００８】また、本発明の第２の半導体装置は、１以
上の電極パッドを供える半導体装置において、上記電極
パッドは、該半導体装置の内部回路のパターン配線に接
続される平面のパッド部と、アース端子と、上記パッド
部とアース端子を電気的に接続する切断可能な導電体と
で構成されることを特徴とする。According to a second semiconductor device of the present invention, in the semiconductor device provided with one or more electrode pads, the electrode pad has a flat pad portion connected to a pattern wiring of an internal circuit of the semiconductor device; It is characterized by comprising a ground terminal and a severable conductor for electrically connecting the pad portion and the ground terminal.

【０００９】上記第２の半導体装置の静電破壊の防止方
法は、電極パッドに外部処理装置の導電性部材を接触さ
せる際に、外部処理装置の導電性部材をパッド部に接触
させるステップと、パッド部とアース端子を接続してい
る上記導電体を切断するステップとからなることを特徴
とする。The second method for preventing electrostatic breakdown of a semiconductor device includes the steps of contacting the conductive member of the external processing device with the pad portion when the conductive member of the external processing device is brought into contact with the electrode pad; Cutting the conductor connecting the pad and the ground terminal.

【００１０】[0010]

【発明の実施の形態】（１）実施の形態１ 以下、実施の形態１にかかる半導体装置１の構成につい
て説明する。図１は、実施の形態１にかかる半導体装置
１の機能ブロック図である。半導体装置１は、高周波信
号の入力用のＲＦ入力パッド２、該ＲＦ入力パッド２よ
り入力された高周波信号を処理するＲＦ回路３、電源電
圧Ｖｃｃの入力用のＤＣパッド４、複数のトランジスタ
で構成されるトランジスタ回路６、上記ＤＣパッド４よ
り入力される電源電圧Ｖｃｃに対して降圧等の処理を施
し、処理後の電源電圧Ｖｃｃを上記トランジスタ回路６
の各トランジスタのゲートに印加するＤＣ回路５、トラ
ンジスタ回路６から出力される信号に対して所定の処理
を施して高周波信号を出力するＲＦ回路７、及び、ＲＦ
回路７より出力された高周波信号の出力用のＲＦ出力パ
ッド８で構成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment A configuration of a semiconductor device 1 according to a first embodiment will be described below. FIG. 1 is a functional block diagram of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes an RF input pad 2 for inputting a high-frequency signal, an RF circuit 3 for processing a high-frequency signal input from the RF input pad 2, a DC pad 4 for inputting a power supply voltage Vcc, and a plurality of transistors. The power supply voltage Vcc input from the DC pad 4 is subjected to a process such as stepping down, and the processed power supply voltage Vcc is applied to the transistor circuit 6.
A DC circuit 5 applied to the gates of the respective transistors, an RF circuit 7 for performing predetermined processing on a signal output from the transistor circuit 6 and outputting a high-frequency signal, and RF
An RF output pad 8 for outputting a high-frequency signal output from the circuit 7 is provided.

【００１１】図２は、半導体装置１の備えるＤＣパッド
４の構成を示す図である。なお、ＲＦ入力パッド２、及
び、ＲＦ出力パッド８も同じ構成である。図２の（ａ）
は、基板１０上に設けられるＤＣパッド４の斜視図であ
り、図２の（ｂ）は、（ａ）に示すＤＣパッド４のａ−
ａ’断面図である。図２の（ａ）に示すように、ＤＣパ
ッド４は、ＤＣ回路５に接続されているパターン配線２
１上を所定の間隙を保持しつつまたぐエアーブリッジ構
成のエアーブリッジ部２３、及び、パッド部２２からな
る。なお、ＤＣパッド４及びパターン配線２１の素材に
は、金（Ａｕ）を用いる。FIG. 2 is a diagram showing a configuration of the DC pad 4 provided in the semiconductor device 1. The RF input pad 2 and the RF output pad 8 have the same configuration. FIG. 2 (a)
FIG. 2 is a perspective view of a DC pad 4 provided on a substrate 10, and FIG. 2B is a perspective view of the DC pad 4 shown in FIG.
It is sectional drawing a '. As shown in FIG. 2A, the DC pad 4 is connected to the pattern wiring 2 connected to the DC circuit 5.
1 comprises an air bridge portion 23 having an air bridge configuration and a pad portion 22 while straddling a predetermined gap. Note that gold (Au) is used as a material of the DC pad 4 and the pattern wiring 21.

【００１２】図２の（ｂ）に示すパターン配線２１の厚
みｂは、約５００Åであり、ＤＣパッド４（エアーブリ
ッジ部２３及びパッド部２２）の厚みｃは、約２μｍで
あり、該パターン配線２１とエアーブリッジ部２３との
間隔ｄは、約１０〜２０μｍである。The thickness b of the pattern wiring 21 shown in FIG. 2B is about 500 °, and the thickness c of the DC pad 4 (the air bridge part 23 and the pad part 22) is about 2 μm. The distance d between the air bridge 21 and the air bridge 23 is about 10 to 20 μm.

【００１３】以下、図３及び図４を参照しつつ、上記構
成のＤＣパッド４に対して、外部処理装置の導電性部材
を接触させる方法の一例として、テスト装置のプローブ
を接触させる方法について説明する。 （ステップ１）図３に示すように、他端の接地されたプ
ローブ３２をパッド部２２に接触させる。 （ステップ２）テスト装置３１に他端が接続され、ＤＣ
パッド４にテスト用の電源電圧Ｖｃｃを印加するプロー
ブ３０をエアーブリッジ部２３に接触させる。これによ
り、プローブ３０に帯電していた静電気がプローブ３２
を介して放電される。 （ステップ３）プローブ３０を基板１０側に押し付け、
図４に示すように、エアーブリッジ部２３をパターン配
線２１に接触させる。これにより、プローブ３０とパタ
ーン配線２１とが電気的に接続される。 （ステップ４）プローブ３２をパッド部２２より離す。 以上のステップ１〜ステップ４の手順を実行すること
で、プローブ３０に帯電していた静電気を完全に放電し
た後に、ＤＣ回路５に接続されているパターン配線２１
に接触させることができる。これにより、プローブ３０
に帯電していた静電気によって、ＤＣ回路５やトランジ
スタ回路６内のトランジスタが破壊されるのを防止する
ことができる。Hereinafter, a method of contacting a probe of a test device as an example of a method of contacting a conductive member of an external processing device with the DC pad 4 having the above configuration will be described with reference to FIGS. I do. (Step 1) As shown in FIG. 3, the other end of the probe 32, which is grounded, is brought into contact with the pad portion 22. (Step 2) The other end is connected to the test device 31 and the DC
The probe 30 for applying the test power supply voltage Vcc to the pad 4 is brought into contact with the air bridge portion 23. As a result, the static electricity charged on the probe 30 is
Is discharged through. (Step 3) The probe 30 is pressed against the substrate 10 side,
As shown in FIG. 4, the air bridge 23 is brought into contact with the pattern wiring 21. As a result, the probe 30 and the pattern wiring 21 are electrically connected. (Step 4) The probe 32 is separated from the pad section 22. By performing the above-described steps 1 to 4, the static electricity charged in the probe 30 is completely discharged, and then the pattern wiring 21 connected to the DC circuit 5 is discharged.
Can be contacted. Thereby, the probe 30
It is possible to prevent the transistors in the DC circuit 5 and the transistor circuit 6 from being destroyed by the static electricity that has been charged.

【００１４】なお、テスト装置３１に接続されるプロー
ブ３０から、テスト用の電源電圧Ｖｃｃの出力を開始し
た後に、プローブ３２をパッド部２２から引き離すよう
にしても良い。この場合、テスト装置３１より出力され
るテスト用の電源電圧Ｖｃｃのサージ電圧が、半導体装
置の回路内に印加されることを防止することができる。The probe 32 may be separated from the pad section 22 after the output of the test power supply voltage Vcc from the probe 30 connected to the test apparatus 31 is started. In this case, the surge voltage of the test power supply voltage Vcc output from the test device 31 can be prevented from being applied to the circuit of the semiconductor device.

【００１５】次に、図５及び図６を参照しつつ、上記構
成のＤＣパッド４をワイヤボンディングする場合の方法
について説明する。 （ステップ１０） 図５に示すように、他端の接地され
たプローブ３２をパッド部２２に接触させる。 （ステップ１１） ボンディング装置のキャピラリ４０
をエアーブリッジ部２３に接触させる。これにより、キ
ャピラリ４０に帯電していた静電気がプローブ３２を介
して放電される。 （ステップ１２） キャピラリ４０を基板１０側に押し
下げ、図６の（ａ）に示すように、エアーブリッジ部２
３をパターン配線２１に接触させる。キャピラリ４０の
先端のＡｕボール４１に熱又は超音波振動を与え、該Ａ
ｕボール４１、エアーブリッジ部２３及びパターン配線
２１を溶接する。 （ステップ１３） 図６の（ｂ）に示すように、キャピ
ラリ４０を上に引き上げ、接続するピン（リードフレー
ム）の方向へ移動させる。Ａｕボール４１はエアーブリ
ッジ部２３に接続されているため、キャピラリ４０の移
動に伴いボンディング装置４２内部からＡｕライン４３
が引き出される。 （ステップ１４） プローブ３２をパッド部２２より引
き離す。 以上のステップ１０〜ステップ１４を実行することで、
キャピラリ４０に帯電していた静電気を完全に放電した
後に、キャピラリ４０をＤＣ回路５に接続されているパ
ターン配線２１に接触させることができる。これによ
り、キャピラリ４０に帯電していた静電気が、ＤＣ回路
５やトランジスタ回路６を構成するトランジスタ等の回
路素子に流れ込み、該回路素子が破壊されることを防止
することができる。Next, a method for wire bonding the DC pad 4 having the above configuration will be described with reference to FIGS. (Step 10) As shown in FIG. 5, the other end of the probe 32, which is grounded, is brought into contact with the pad portion 22. (Step 11) Capillary 40 of bonding apparatus
Is brought into contact with the air bridge section 23. Thereby, the static electricity charged in the capillary 40 is discharged through the probe 32. (Step 12) The capillary 40 is pushed down to the substrate 10 side, and as shown in FIG.
3 is brought into contact with the pattern wiring 21. Heat or ultrasonic vibration is applied to the Au ball 41 at the tip of the capillary 40,
The u-ball 41, the air bridge 23 and the pattern wiring 21 are welded. (Step 13) As shown in FIG. 6B, the capillary 40 is pulled up and moved in the direction of the pin (lead frame) to be connected. Since the Au ball 41 is connected to the air bridge portion 23, the Au line 43 is connected from the inside of the bonding device 42 with the movement of the capillary 40.
Is pulled out. (Step 14) The probe 32 is separated from the pad section 22. By executing the above steps 10 to 14,
After the static electricity charged in the capillary 40 is completely discharged, the capillary 40 can be brought into contact with the pattern wiring 21 connected to the DC circuit 5. Accordingly, it is possible to prevent the static electricity charged in the capillary 40 from flowing into circuit elements such as the transistors constituting the DC circuit 5 and the transistor circuit 6 and to break the circuit elements.

【００１６】（２）実施の形態２ 以下、実施の形態２にかかる半導体装置４５の構成につ
いて説明する。半導体装置４５の機能ブロックの構成
は、上記実施の形態１にかかる半導体装置１と同じであ
る。半導体装置４５は、半導体装置１とＲＦ入力パッド
２、ＤＣパッド、及び、ＲＦ出力パッド８の構成が異な
る。以下、半導体装置４５のＤＣパッド４の構成を説明
する。なお、半導体装置４５におけるＲＦ入力パッド
２、ＤＣパッド、及び、ＲＦ出力パッド８の構成は、同
じである。(2) Second Embodiment A configuration of a semiconductor device 45 according to a second embodiment will be described below. The configuration of the functional blocks of the semiconductor device 45 is the same as that of the semiconductor device 1 according to the first embodiment. The semiconductor device 45 differs from the semiconductor device 1 in the configuration of the RF input pad 2, the DC pad, and the RF output pad 8. Hereinafter, the configuration of the DC pad 4 of the semiconductor device 45 will be described. Note that the configurations of the RF input pad 2, the DC pad, and the RF output pad 8 in the semiconductor device 45 are the same.

【００１７】図７は、半導体装置４５のＤＣパッド４の
構成を示す斜視図である。ＤＣパッド４は、ＤＣ回路５
に接続されるパターン配線２１と電気的に接続された状
態で設けられた平面のパッド部５１と、基板５０の裏面
のＧＮＤ端子に接続されるバイアホールを持つアース端
子５３と、パッド部５１及びアース端子５３を電気的に
接続する抵抗であって、レーザにより切断可能な抵抗５
４より構成される。FIG. 7 is a perspective view showing the structure of the DC pad 4 of the semiconductor device 45. The DC pad 4 is a DC circuit 5
A flat pad portion 51 provided in a state electrically connected to the pattern wiring 21 connected to the substrate 50; a ground terminal 53 having a via hole connected to the GND terminal on the back surface of the substrate 50; A resistor that is electrically connected to the ground terminal 53 and that can be cut by a laser.
4

【００１８】以下、上記構成のＤＣパッドをワイヤボン
ディングする方法について説明する。 （ステップ２０） キャピラリ４０の先端に位置するＡ
ｕボール４１をパッド部５１に接触させる。パッド部４
１は、予めアース端子５３に接続されているため、キャ
ピラリ４０に帯電していた静電気は、全てアース端子５
３に放電される。 （ステップ２１） キャピラリ４０の先端のＡｕボール
４１に熱又は超音波振動を与え、該Ａｕボール４１とパ
ッド部５１を溶接する。 （ステップ２２） キャピラリ４０を引き上げた後、接
続するピンの方向へ移動させる。この際、Ａｕボール４
１はパッド部５１に接続されているため、ボンディング
装置４２内部からＡｕライン４３が引き出される。 （ステップ２３） ワイヤボンディングの終了後、抵抗
５４をレーザにより切断する。 以上のステップ２０〜ステップ２３を実行することで、
ワイヤボンディングを行う際にキャピラリ４０に帯電し
ていた静電気が半導体装置の内部回路に流れ込むことを
防止することができる。これにより、キャピラリ４０に
帯電していた静電気によって、ＤＣ回路５やトランジス
タ回路６内のトランジスタ等の回路素子が破壊されるこ
とを防止することができる。Hereinafter, a method of wire bonding the DC pad having the above configuration will be described. (Step 20) A located at the tip of the capillary 40
The u-ball 41 is brought into contact with the pad 51. Pad part 4
1 is connected to the ground terminal 53 in advance, so that any static electricity charged in the capillary 40 is
3 is discharged. (Step 21) Heat or ultrasonic vibration is applied to the Au ball 41 at the tip of the capillary 40, and the Au ball 41 and the pad portion 51 are welded. (Step 22) After the capillary 40 is pulled up, it is moved in the direction of the pin to be connected. At this time, Au ball 4
Since 1 is connected to the pad section 51, the Au line 43 is drawn out from the inside of the bonding apparatus 42. (Step 23) After the completion of the wire bonding, the resistor 54 is cut by a laser. By performing the above steps 20 to 23,
It is possible to prevent static electricity charged in the capillary 40 from flowing into an internal circuit of the semiconductor device when performing wire bonding. Accordingly, it is possible to prevent circuit elements such as transistors in the DC circuit 5 and the transistor circuit 6 from being destroyed by static electricity charged in the capillary 40.

【００１９】[0019]

【発明の効果】本発明の第１の半導体装置は、電極パッ
ドを構成するパッド部に他端の接地されたプローブを接
触させた後に、エアーブリッジ部に外部処理装置の導電
性部材を接触させ、更に該導電性部材を押し下げてエア
ーブリッジ部とパターン配線を接触させることができ
る。これにより、上記導電性部材に帯電していた静電気
を完全に放電した後に、該導電性部材をパターン配線に
接触させることができ、半導体装置内部の回路に静電気
が流れ込むことを防止することができる。According to the first semiconductor device of the present invention, after the probe grounded at the other end is brought into contact with the pad portion constituting the electrode pad, the conductive member of the external processing device is brought into contact with the air bridge portion. Further, the conductive member can be further pressed down to bring the air bridge portion into contact with the pattern wiring. Thus, after the static electricity charged on the conductive member is completely discharged, the conductive member can be brought into contact with the pattern wiring, and the static electricity can be prevented from flowing into a circuit inside the semiconductor device. .

【００２０】本発明の上記第１の半導体装置の静電破壊
の防止方法では、電極パッドに外部処理装置の導電性部
材を接触させる際に、上記導電性部材に帯電していた静
電気を完全に放電した後に、該導電性部材をパターン配
線に接触させることができ、半導体装置内部の回路に静
電気が流れ込むことを防止することができる。In the first method for preventing electrostatic breakdown of a semiconductor device according to the present invention, when the conductive member of the external processing device is brought into contact with the electrode pad, the static electricity charged on the conductive member is completely removed. After the discharge, the conductive member can be brought into contact with the pattern wiring, so that static electricity can be prevented from flowing into a circuit inside the semiconductor device.

【００２１】本発明の第２の半導体装置は、電極パッド
を構成するパッド部に外部処理装置の導電性部材を接触
させた後に、切断可能な導電体を切断することで、上記
導電性部材に帯電していた静電気を完全に放電し、半導
体装置内部の回路に静電気が流れ込むことを防止するこ
とができる。According to the second semiconductor device of the present invention, the conductive member of the external processing device is brought into contact with the pad portion constituting the electrode pad, and then the cuttable conductor is cut, so that the conductive member is cut. It is possible to completely discharge the charged static electricity and prevent the static electricity from flowing into a circuit inside the semiconductor device.

【００２２】本発明の上記第２の半導体装置の静電破壊
の防止方法では、電極パッドに外部処理装置の導電性部
材を接触させる際に、上記導電性部材に帯電していた静
電気を完全に放電し、半導体装置内部の回路に静電気が
流れ込むことを防止することができる。In the second method for preventing electrostatic breakdown of a semiconductor device according to the present invention, when the conductive member of the external processing device is brought into contact with the electrode pad, the static electricity charged on the conductive member is completely removed. Discharge can be prevented, and static electricity can be prevented from flowing into a circuit inside the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 実施の形態１にかかる半導体装置の機能ブロ
ック図である。FIG. 1 is a functional block diagram of a semiconductor device according to a first embodiment;

【図２】 実施の形態１にかかる電極パッドの構成を示
す図である。FIG. 2 is a diagram illustrating a configuration of an electrode pad according to the first embodiment;

【図３】 実施の形態１にかかる半導体装置をテスト装
置によりテストする場合の実施状態を示す図である。FIG. 3 is a diagram illustrating an implementation state when the semiconductor device according to the first embodiment is tested by a test device;

【図４】 実施の形態１にかかる半導体装置のテスト実
施状態を示す断面図である。FIG. 4 is a cross-sectional view illustrating a test execution state of the semiconductor device according to the first embodiment;

【図５】 実施の形態１にかかる半導体装置にワイヤボ
ンディングを施す際の状態を示す図である。FIG. 5 is a diagram illustrating a state when wire bonding is performed on the semiconductor device according to the first embodiment;

【図６】 実施の形態１にかかる半導体装置へのワイヤ
ボンディング実行時における断面図である。FIG. 6 is a cross-sectional view when wire bonding to the semiconductor device according to the first embodiment is performed;

【図７】 実施の形態２にかかる半導体装置にワイヤボ
ンディングを施す際の状態を示す図である。FIG. 7 is a diagram illustrating a state when wire bonding is performed on the semiconductor device according to the second embodiment;

【図８】 従来の高周波回路用の半導体装置の構成を示
す図である。FIG. 8 is a diagram showing a configuration of a conventional semiconductor device for a high-frequency circuit.

【図９】 従来の半導体装置の備えるパッドを用いたテ
スト装置によるテスト実行時の様子を示す図である。FIG. 9 is a diagram showing a state when a test is performed by a test apparatus using pads provided in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１，４５，１００ 半導体装置、２，１０１ ＲＦ入力
パッド、３，１０２ ＲＦ回路、４，１０３ ＤＣパッ
ド、５，１０４ ＤＣ回路、６，１０５ トランジスタ
回路、７，１０６ ＲＦ回路、８，１０７ ＲＦ出力パ
ッド、２１ パターン配線、２２，５１ パッド部、２
３ エアーブリッジ部、３０，３２，１３０ プロー
ブ、３１，１３１ テスト装置、４０ キャピラリ、４
１ Ａｕボール、５３ アース端子1,45,100 semiconductor device, 2,101 RF input pad, 3,102 RF circuit, 4,103 DC pad, 5,104 DC circuit, 6,105 transistor circuit, 7,106 RF circuit, 8,107 RF output Pad, 21 pattern wiring, 22, 51 pad part, 2
3 air bridge section, 30, 32, 130 probe, 31, 131 test equipment, 40 capillary, 4
1 Au ball, 53 ground terminal

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 １以上の電極パッドを供える半導体装置
において、 上記電極パッドは、平面のパッド部と、該パッド部に接
続され、所定の間隙をもって内部回路のパターン配線と
交差するエアーブリッジ部とで構成されることを特徴と
する半導体装置。1. A semiconductor device provided with one or more electrode pads, wherein said electrode pads include a planar pad portion, and an air bridge portion connected to said pad portion and intersecting a pattern wiring of an internal circuit with a predetermined gap. A semiconductor device comprising: 【請求項２】 請求項１に記載の半導体装置の静電破壊
の防止方法であって、 他端の接地されたプローブをパッド部に接触させるステ
ップと、 外部処理装置の導電性部材をエアーブリッジ部に接触さ
せるステップと、 外部処理装置の導電性部材を押し下げ、エアーブリッジ
部をパターン配線に接触させるステップと、 パッド部に接触させている上記他端の接地されたプロー
ブを引き離すステップとからなることを特徴とする半導
体装置の静電破壊の防止方法。2. The method according to claim 1, wherein a grounded probe at the other end is brought into contact with a pad portion, and a conductive member of the external processing device is air-bridged. Contacting the conductive member of the external processing device, bringing the air bridge into contact with the pattern wiring, and separating the grounded probe at the other end in contact with the pad. A method for preventing electrostatic breakdown of a semiconductor device. 【請求項３】 １以上の電極パッドを供える半導体装置
において、 上記電極パッドは、該半導体装置の内部回路のパターン
配線に接続される平面のパッド部と、アース端子と、上
記パッド部とアース端子を電気的に接続する切断可能な
導電体とで構成されることを特徴とする半導体装置。3. A semiconductor device provided with one or more electrode pads, wherein the electrode pads are a flat pad portion connected to a pattern wiring of an internal circuit of the semiconductor device, a ground terminal, and the pad portion and the ground terminal. And a severable conductor for electrically connecting the semiconductor device. 【請求項４】 請求項３に記載の半導体装置の静電破壊
の防止方法であって、 外部処理装置の導電性部材をパッド部に接触させるステ
ップと、 パッド部とアース端子を接続している上記導電体を切断
するステップとからなることを特徴とする半導体装置の
静電破壊の防止方法。4. The method for preventing electrostatic breakdown of a semiconductor device according to claim 3, wherein the step of contacting the conductive member of the external processing device with the pad portion and the step of connecting the pad portion and the ground terminal. Cutting the conductive material. A method for preventing electrostatic breakdown of a semiconductor device.
JP23869298A 1998-08-25 1998-08-25 Wire bonding method to pattern wiring of semiconductor device Expired - Fee Related JP3769128B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23869298A JP3769128B2 (en) 1998-08-25 1998-08-25 Wire bonding method to pattern wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23869298A JP3769128B2 (en) 1998-08-25 1998-08-25 Wire bonding method to pattern wiring of semiconductor device

Publications (2)

Publication Number Publication Date
JP2000068320A true JP2000068320A (en) 2000-03-03
JP3769128B2 JP3769128B2 (en) 2006-04-19

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US9455570B2 (en) 2013-04-25 2016-09-27 Tektronix, Inc. Low insertion loss electrostatic discharge (ESD) limiter
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JP2018179748A (en) * 2017-04-13 2018-11-15 日置電機株式会社 Inspection procedure data generation device, substrate inspection device, and substrate inspection method

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