JP2000031309A - チップスタックパッケ―ジ - Google Patents
チップスタックパッケ―ジInfo
- Publication number
- JP2000031309A JP2000031309A JP11130259A JP13025999A JP2000031309A JP 2000031309 A JP2000031309 A JP 2000031309A JP 11130259 A JP11130259 A JP 11130259A JP 13025999 A JP13025999 A JP 13025999A JP 2000031309 A JP2000031309 A JP 2000031309A
- Authority
- JP
- Japan
- Prior art keywords
- chip stack
- stack package
- semiconductor chips
- lead
- package according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract
接続経路が短く、かつ半導体チップ間の接続長さも短い
チップスタックパッケージを提供することにある。 【構成】 チップスタックパッケージにおいて、両側面
にボンディングパッドを配置し、前記各ボンディングパ
ッドに上下に貫通する溝112を形成し、少なくとも2
個以上を上下に配置した複数の半導体チップ102、1
04と、これらの各半導体チップ102、104の溝1
12に挿入し、各ボンディングパッドを電気的に接続す
る複数のリードフレーム108と、このリードフレーム
108の外部接続部分のみが露出するように、全体をモ
ールドする封止剤116とを有することを特徴とする。
Description
ッケージに関し、特に複数の半導体チップが積層(stack
ing)されたチップスタックパッケージに関する。
端末装置のサイズの低減に伴い、限定した面積内でより
高いメモリ容量を持つチップスタックパッケージが使わ
れている。
な一例を図1に示す。図1を参照すれば、チップスタッ
クパッケージは、半導体チップをそれぞれ有するパッケ
ージが2個以上の層で積層されていることが分かる。図
1に示すスタックチップパッケージは、単位パッケージ
10、20がこれらの側面部に接着されるガイド15に
より互いに電気的に接続している構造からなる。単位パ
ッケージ10、20間の電気的な接続のため、単位パッ
ケージ10、20のアウタリード11、21とガイド1
5との間に半田接合部(図示せず)が提供される。
ッケージでは、単位パッケージ10、20を互いに電気
的に接続する半田接合部の接合信頼性に問題がある。
又、電気的信号伝達がチップサイズパッケージ(chip si
ze package)より遅延されるという欠点がある。その
他、パッケージ駆動時発生される熱を放出するため、従
来のパッケージはヒートシンク(heat sink)を含むべき
で、かつチップサイズパッケージの形態で積層すること
が不可能である。
及び図2(b)に示すようなチップスタックパッケージ
が開発された。図2(a)を参照すれば、チップスタッ
クパッケージ30は、積層されている半導体チップ3
1、32がTAB(Tape Automated Bonding)33により
リードフレーム(lead frame)35に接続した構造であ
る。一方、図2(b)には、前記半導体チップ31、3
2がボンディングワイヤ(bonding wire)37によりリー
ドフレーム35に電気的に接続したチップスタックパッ
ケージ30aを示している。図2(a)及び図2(b)
において符号29は封止剤(epoxy compound)チップスタ
ックパッケージ30aである。
示すチップスタックパッケージは、複数の半導体チップ
とリードフレームとの間の電気的な接続のために、TA
Bまたはボンディングワイヤを利用するので、電気信号
の経路が長くて電気的特性が悪いという欠点がある。ま
た、従来のチップスタックパッケージは、放熱メカニズ
ム(mechanism)が非常に複雑であるか、あるいは熱の発
散が充分でないという欠点もある。このような欠点によ
って、図2(a)及び図2(b)に示すチップスタック
パッケージは実際への適用が非常に困難である。
なされたもので、その目的は、半導体チップと外部ディ
バイスとの電気的な接続経路が短く、かつ半導体チップ
間の接続長さも短いチップスタックパッケージを提供す
ることにある。また、本発明の別の目的は、放熱特性が
優秀なチップスタックパッケージを提供することにあ
る。
ックパッケージは、少なくとも2個以上で積層された半
導体チップを含む。各半導体チップの両側面の各々にボ
ンディングパッドを配置する。前記ボンディングパッド
には上下に開口した形状の溝を形成する。各ボンディン
グパッドの溝にリードフレームを挿入し、そのリードフ
レームにより各ボンディングパッドが電気的に接続す
る。各リードフレームの下端のみが露出するように、全
体を封止剤でモールドする。
を参照して詳細に説明する。図3は、発明の実施の形態
1に係るチップスタックパッケージを示す断面図であ
る。同図を参照すれば、発明の実施の形態1に係るチッ
プスタックパッケージ100は、接着剤層106により
接着されて上下に積層された第1及び第2半導体チップ
102、104を有する。
性樹脂、ACF(Anistropic Conductive Film)またはA
CA(Anistropic Conductive Adhesive)が用いられる。
このうちのTABは、内部に導電回路があり、後述する
半導体チップのボンディングパッドに半田(solder)をリ
フロー(reflow)する際、半田と電気的に接着することに
より、電気的なノイズを減少させる接地面(ground plan
e)の作用を行い、パッケージの電気的な特性向上を図る
ことができるので、より望ましい。
着性物質で形成される最上層及び最下層は各半導体チッ
プ102、104を接着する役割を果たす。導電物質で
形成される中間層は各半導体チップ102、104と電
気的に接続することにより、パワーあるいは接地面の作
用を行う。TABの最上層及び最下層を形成する接着性
物質としては、エポキシ系の熱可塑性樹脂、接着性ガラ
スまたは接着性テープが用いられ、接着性テープの場合
は10〜100μmの厚さを有し、絶縁性ポリマーから
なるのが望ましい。TABの中間層を形成する導電性層
は、平板または網状の平面構造を有しながら単層または
多層構造からなる。
/Ni/Cr/Au、Cu/Ni/Co/Au、Cu/Ni/S
n/Au、Cu/Ni/Cr/Au/AnまたはCu/Ni/
Co/Au/Snからなる群で選択される材料のメタルラ
インで形成されるのが望ましい。この様な導電性層のメ
タルラインは1mil〜4milの厚さを有するのが望まし
い。そして、導電性層には周辺回路との接着及び電気的
な導通のために、導電性粒子を含む接着性物質の異方性
導電体が、ステンシル(stencil)、スクリーンプリント
(screen print)、ディスペンス(dispense)、スタンプ(s
tamp)またはラミネーション(lamination)等の方式にて
塗布されるのが望ましい。なお、接着性物質としては、
エポキシ樹脂 (epoxy resin)、ポリエステル(polyeste
r)、アクリル酸エステル(acrylicester)、エステル、シ
リコン樹脂(silicon resin)、フェノキシ樹脂(phenoxy
resin)、ポリウレタン(polyurethane)、ポリスルフィド
(polysulfide)及び、その他熱硬化性重合体が用いられ
る。又、導電性粒子としては、Ag、Au、Ni、I
n、SnまたはITO(Indium Tin Oxide)等が用いら
れる。導電性粒子は、3〜20μmの粒度を有し、球
形、四角形、三角形、六面体、四角錐、三角錐などの形
状を有する。導電性粒子は、内部のポリマーを導電性金
属が外部で塗布する構造からなる。
104の各両側面には、図4に示すボンディングパッド
160を形成する。ボンディングパッド160はアルミ
材質からなり、最小15μm×15μm乃至最大500
μm×500μmのサイズを持つ。ボンディングパッド
160には上下に開口した形状の溝112を形成する
が、発明の実施の形態1に係る溝112は直方体形状で
形成される。
し、前記リードフレーム108によって各ボンディング
パッド160が電気的に接続する。前記リードフレーム
108は、各溝112に挿入される垂直リード108a
と、垂直リード108aの下端に形成されて外部ディバ
イス、例えば印刷回路基板に電気的に接続する水平リー
ド108bとを含む。前記リードフレーム108の垂直
リード108aが、溝112の全体内壁に密着されるよ
うに、溝112の形状と対応する形状からなる。すなわ
ち、垂直リード108aは幅より高さの方が相対的に非
常に長い直方体形状として、その幅が溝112の幅とほ
ぼ同様である。また、溝112と垂直リード108aと
の間の接着力強化のために、溝112の内壁と、この内
壁に接触される垂直リード108aとの表面に半田11
8a、118bを塗布する。
が露出した表面すなわち下面に、第1及び第2半導体チ
ップ102、104から発生される熱を外部へ放出する
ためのヒートシンク114を取り付ける。第1及び第2
半導体チップ102、104とリードフレーム108を
保護しかつ外部と電気的に絶縁させるために、リードフ
レーム108の水平リード108bの下面とヒートシン
ク114の下面だけが露出するように、全体を封止剤1
16でモールドする。
るチップスタックパッケージは、第1及び第2半導体チ
ップ102、104の両側に配置されたボンディングパ
ッド160が一直線のリードフレーム108により電気
的に接続するので、各半導体チップ102、104と外
部デバイスを電気的に接続する経路と、各半導体チップ
102、104間の経路とが非常に短くなる。また、第
1半導体チップ102が露出した表面にヒートシンク1
14を取り付けるので、半導体チップから発生される高
熱を外部へ容易に放出させることができる。
スタックパッケージ200を示す。同図に示すチップス
タックパッケージ200は、第2半導体チップ104の
上部表面が封止剤116から露出する。これにより、パ
ッケージ200は各半導体チップ102、104から発
生される熱をより容易に外部へ放出させることができる
利点を有する。ただし、垂直リード108aの上端が、
外部に露出しないように、第2半導体チップ104の表
面及び封止剤116の表面と同様に位置するようにな
る。
スタックパッケージ300を示す。同図に示すチップス
タックパッケージ300は、図5に示す2個のパッケー
ジが向かい合う状態で積層される。すなわち、上部に配
置した第1単位パッケージ300aの第2半導体チップ
104が、下部に配置した第2単位パッケージ300b
の第2半導体チップ104aと対向配置される。よっ
て、第1及び第2単位パッケージ300a、300bの
各垂直リード108c、108aも対向配置される。こ
のように配置した各垂直リード108c、108aが、
半田ボール(solderball)118により電気的に接続する
ことにより、計4個の半導体チップ102、104、1
04a、102aが電気的に接続した状態で積層され
る。ここで、符号108dは、第1単位パッケージ30
0aの水平リードである。
スタックパッケージ400を示す。同図に示すチップス
タックパッケージ400は、図3に示すチップスタック
パッケージ100において、水平リードだけを一部変形
したものである。すなわち、水平リード108bはその
外側端部が封止剤116の側面へ延長された構造からな
り、この様な水平リード108bは、PCBに接触され
る面積を増加させるので、パッケージの実装性が向上で
きるという利点を有する。
スタックパッケージ500を示す。同図に示すチップス
タックパッケージ500は、ヒートシンクを有しない点
で図3に示すチップスタックパッケージ100と相違す
る。ヒートシンクを省略すると、ヒートシンクの厚さだ
けパッケージ500の厚さを軽薄短小化させることがで
きるという利点がある。また、パッケージ500は、封
止剤116から露出した水平リード108bの下面に、
半田ボール118をマウントすることにより、PCBに
直接実装されるか、あるいはMCMやセラミックパッケ
ージに挿入されるフリップチップの形態を有することに
なる。
2個の半導体チップを積層したものを例に挙げたが、3
個以上の半導体チップを積層してパッケージが構成でき
ることは勿論である。
次の様な方法にて製造される。まず、図9(a)に示す
ように、ボンディングパッドを配置した第1半導体チッ
プ102の一側上部に、ダイアモンド材質の切削ホイー
ル150を配置し、切削ホイール150を利用して、図
9(b)のように、ボンディングパッド厚さの半分を除
去して半溝を形成する。次に、第1半導体チップ102
の下面全体を残存のボンディンパッド厚さだけ研磨し
て、半溝の底面を露出させることにより、ボンディング
パッドに上下に開口した溝112を形成する。図示して
はないが、前記のような方式にて、第1半導体チップ1
02の他側に配置したボンディングパッドにも溝を形成
し、また第2半導体チップの各ボンディングパッドにも
溝を形成する。
しては、前記方法の他に図10(a)〜図10(d)に
示した方法が用いられる。図10(a)及び図10
(b)までの工程は、図9(a)及び図9(b)と同様
で、図10(c)のように、半溝のみが露出するよう
に、第1半導体チップ102の表面上に食刻マスク15
2を形成する。続いて、食刻マスク152を利用して半
溝を食刻し、図10(d)のように、ボンディングパッ
ドに溝112を形成する。
2を形成した後、溝112が露出するように、第1半導
体チップ102の表面上にスプレーマスク(spray mask)
154を形成する。次に、スプレーマスク154を利用
して、溝112の内壁全体にスプレー、PVDまたはC
VD方式にて半田を形成する。第2半導体チップにも、
前記のような工程を行う。
利用して、第1及び第2半導体チップ102、104を
接着させ、2個の半導体チップ102、104を積層す
る。
た表面上に、エポキシ156を利用してヒートシンク1
14を取り付ける。ここで、ヒートシンク114は第1
半導体チップ102が露出した面の下方に取り付けるこ
ともある。図3は、ヒートシンク114が第1半導体チ
ップ102の下面に取り付けられたパッケージを示す。
な形状を持つリードフレーム108の垂直リード108
aを、各溝112に挿入することにより、各半導体チッ
プ102、104のボンディングパッドが電気的に接続
する。垂直リード108aには、溝112の内壁との接
着信頼性の向上のために、溝112のようにあらかじめ
半田を塗布する。図15は、左右対称の複数個のリード
フレーム108のうち、一側のみを示す斜視図である。
一方、図14及び図15において符号122は、リード
フレーム108の水平リード108bを固定する接着テ
ープである。
ブロック250上に安置させ、ヒーターブロック250
から全体構造物へ熱を加える。これと同時に、溝112
の内壁と垂直リード108aとの間へ、半田ペーストや
ACAのような導電性物質を注入する。この様な注入方
法としては、真空下で溝の内部に導電性物質を注入した
後、大気圧に露出させ、圧力差によって導電性物質が溝
の内部へ完全に入り込むようにする方法が用いられる。
ロー工程を行い、第1及び第2半導体チップ102、1
04のボンディングパッドとリードフレーム108とを
電気的かつ機械的に完全に接合させる。
ド108bの下面とヒートシンク114の下面だけが露
出するように、全体を封止剤116でモールドした後、
シンギュレーション(singulation)工程を行って個々に
分離することにより、図3に示すチップスタックパッケ
ージを製造する。
に係るパッケージの製造方法を説明した。しかし、当業
者であれば、図4〜図8に示す発明の実施の形態2〜5
に係るパッケージを製造する方法が、上記の説明から容
易に理解して実施できるので、発明の実施の形態2〜5
に係るパッケージを製造する方法に関する説明は省略す
る。
ップスタックパッケージは、半導体チップの両側に配置
した直線のリードフレームにより、半導体チップと外部
デバイスが電気的に接続するので、半導体チップと外部
ディバイスとの間の電気的接続経路と、各半導体チップ
間の電気的接続経路とが非常に短くなる。結果的に、ス
タックパッケージの電気的特性が向上する。
シンクを取り付けることにより、半導体チップから発生
される熱を外部へ容易に放出させることができる。
について説明したが、本発明は前記発明の実施の形態に
限らず、当該発明の属する分野における通常の知識を有
する者であれば、特許請求の範囲に記載した本発明の要
旨から逸脱しない範囲で多様に実施・変更ができる。
断面図である。
クパッケージの他の例を示す断面図である。
ケージを示す断面図である。
の付着を説明するための部分斜視図である。
ケージを示す断面図である。
ケージを示す断面図である。
ケージを示す断面図である。
ケージを示す断面図である。
る。
ある。
ある。
ある。
ある。
ある。
ある。
Claims (9)
- 【請求項1】 両側面にボンディングパッドを配置し、
前記各ボンディングパッドに上下に貫通する溝を形成
し、少なくとも2個以上を上下に配置した複数の半導体
チップと、前記各半導体チップの溝に挿入し、各ボンデ
ィングパッドを電気的に接続する複数のリードフレーム
と、前記リードフレームの外部接続部分のみが露出する
ように、全体をモールドする封止剤とを含むことを特徴
とするチップスタックパッケージ。 - 【請求項2】 前記複数の半導体チップの表面の最上部
または最下部面にヒートシンクを取り付け、前記ヒート
シンクは封止剤から露出したことを特徴とする請求項1
記載のチップスタックパッケージ。 - 【請求項3】 前記複数の半導体チップの表面の最上部
または最下部面は、前記封止剤から露出したことを特徴
とする請求項1記載のチップスタックパッケージ。 - 【請求項4】 前記リードフレームは、前記各溝に挿入
した垂直リードと、前記垂直リードの一端に接続した水
平リードとを含むことを特徴とする請求項1記載のチッ
プスタックパッケージ。 - 【請求項5】 前記垂直リードの他端が封止剤から露出
し、このような垂直リードを持つ2個の半導体チップの
積層された2個の単位パッケージが、封止剤から露出し
た各垂直リードが対向するように配置され、前記対向す
る垂直リードが、半田ボールにより電気的に接続したこ
とを特徴とする請求項4記載のチップスタックパッケー
ジ。 - 【請求項6】 前記水平リードは封止剤の外側面まで延
長されたことを特徴とする請求項4記載のチップスタッ
クパッケージ。 - 【請求項7】 前記水平リードの外部と接続する部分に
半田ボールをマウントしたことを特徴とする請求項4記
載のチップスタックパッケージ。 - 【請求項8】 前記各半導体チップは、TAB、熱硬化
性樹脂、ACF及びACAからなる群で選択した接着剤
により取り付けられることを特徴とする請求項1記載の
チップスタックパッケージ。 - 【請求項9】 前記溝の内壁と、前記溝の内壁に接触す
る前記リードフレーム部分とに、半田ボールを塗布する
ことを特徴とする請求項1記載のチップスタックパッケ
ージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1998/P16880 | 1998-05-12 | ||
KR1019980016880A KR100265566B1 (ko) | 1998-05-12 | 1998-05-12 | 칩 스택 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000031309A true JP2000031309A (ja) | 2000-01-28 |
JP3826253B2 JP3826253B2 (ja) | 2006-09-27 |
Family
ID=19537226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13025999A Expired - Fee Related JP3826253B2 (ja) | 1998-05-12 | 1999-05-11 | チップスタックパッケージ |
Country Status (3)
Country | Link |
---|---|
US (1) | US6137162A (ja) |
JP (1) | JP3826253B2 (ja) |
KR (1) | KR100265566B1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7656030B2 (en) | 2006-01-11 | 2010-02-02 | Renesas Technology Corp. | Semiconductor device |
WO2012049934A1 (ja) | 2010-10-13 | 2012-04-19 | 日立オートモティブシステムズ株式会社 | 流量センサおよびその製造方法並びに流量センサモジュールおよびその製造方法 |
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US6893896B1 (en) * | 1998-03-27 | 2005-05-17 | The Trustees Of Princeton University | Method for making multilayer thin-film electronics |
US6586836B1 (en) * | 2000-03-01 | 2003-07-01 | Intel Corporation | Process for forming microelectronic packages and intermediate structures formed therewith |
US6576494B1 (en) | 2000-06-28 | 2003-06-10 | Micron Technology, Inc. | Recessed encapsulated microelectronic devices and methods for formation |
US6561479B1 (en) * | 2000-08-23 | 2003-05-13 | Micron Technology, Inc. | Small scale actuators and methods for their formation and use |
KR100646971B1 (ko) * | 2000-12-07 | 2006-11-17 | 주식회사 하이닉스반도체 | 스택 패키지 제조용 스텐실의 구조 |
TW554191B (en) * | 2000-12-16 | 2003-09-21 | Au Optronics Corp | Laminating structure and its forming method |
US6734538B1 (en) | 2001-04-12 | 2004-05-11 | Bae Systems Information & Electronic Systems Integration, Inc. | Article comprising a multi-layer electronic package and method therefor |
SG111919A1 (en) | 2001-08-29 | 2005-06-29 | Micron Technology Inc | Packaged microelectronic devices and methods of forming same |
KR20030018642A (ko) | 2001-08-30 | 2003-03-06 | 주식회사 하이닉스반도체 | 스택 칩 모듈 |
SG120879A1 (en) * | 2002-08-08 | 2006-04-26 | Micron Technology Inc | Packaged microelectronic components |
SG114585A1 (en) | 2002-11-22 | 2005-09-28 | Micron Technology Inc | Packaged microelectronic component assemblies |
SG143931A1 (en) | 2003-03-04 | 2008-07-29 | Micron Technology Inc | Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths |
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US7196427B2 (en) * | 2005-04-18 | 2007-03-27 | Freescale Semiconductor, Inc. | Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element |
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KR100886718B1 (ko) * | 2007-10-16 | 2009-03-04 | 주식회사 하이닉스반도체 | 적층 반도체 패키지 및 이의 제조 방법 |
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-
1998
- 1998-05-12 KR KR1019980016880A patent/KR100265566B1/ko not_active IP Right Cessation
-
1999
- 1999-05-10 US US09/307,657 patent/US6137162A/en not_active Expired - Lifetime
- 1999-05-11 JP JP13025999A patent/JP3826253B2/ja not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7656030B2 (en) | 2006-01-11 | 2010-02-02 | Renesas Technology Corp. | Semiconductor device |
WO2012049934A1 (ja) | 2010-10-13 | 2012-04-19 | 日立オートモティブシステムズ株式会社 | 流量センサおよびその製造方法並びに流量センサモジュールおよびその製造方法 |
US8640538B2 (en) | 2010-10-13 | 2014-02-04 | Hitachi Automotive Systems, Ltd. | Flow sensor and manufacturing method of the same and flow sensor module and manufacturing method of the same |
US9222813B2 (en) | 2010-10-13 | 2015-12-29 | Hitachi Automotive Systems, Ltd. | Flow sensor and manufacturing method of the same and flow sensor module and manufacturing method of the same |
US9222814B2 (en) | 2010-10-13 | 2015-12-29 | Hitachi Automotive Systems, Ltd. | Flow sensor and manufacturing method of the same and flow sensor module and manufacturing method of the same |
EP3421949A1 (en) | 2010-10-13 | 2019-01-02 | Hitachi Automotive Systems, Ltd. | Flow sensor and manufacturing method of the same and flow sensor module and manufacturing method of the same |
Also Published As
Publication number | Publication date |
---|---|
JP3826253B2 (ja) | 2006-09-27 |
US6137162A (en) | 2000-10-24 |
KR100265566B1 (ko) | 2000-09-15 |
KR19990084838A (ko) | 1999-12-06 |
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