IT8120851A0 - Dispositivo a circuito integrato a semiconduttori. - Google Patents

Dispositivo a circuito integrato a semiconduttori.

Info

Publication number
IT8120851A0
IT8120851A0 IT8120851A IT2085181A IT8120851A0 IT 8120851 A0 IT8120851 A0 IT 8120851A0 IT 8120851 A IT8120851 A IT 8120851A IT 2085181 A IT2085181 A IT 2085181A IT 8120851 A0 IT8120851 A0 IT 8120851A0
Authority
IT
Italy
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
semiconductor
integrated
Prior art date
Application number
IT8120851A
Other languages
English (en)
Other versions
IT1136830B (it
Inventor
Takashi Yamaguchi
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of IT8120851A0 publication Critical patent/IT8120851A0/it
Application granted granted Critical
Publication of IT1136830B publication Critical patent/IT1136830B/it

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT20851/81A 1980-04-04 1981-03-31 Dispositivo a circuito integrato a semiconduttori IT1136830B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4357480A JPS56140648A (en) 1980-04-04 1980-04-04 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
IT8120851A0 true IT8120851A0 (it) 1981-03-31
IT1136830B IT1136830B (it) 1986-09-03

Family

ID=12667512

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20851/81A IT1136830B (it) 1980-04-04 1981-03-31 Dispositivo a circuito integrato a semiconduttori

Country Status (4)

Country Link
JP (1) JPS56140648A (it)
DE (1) DE3113333A1 (it)
GB (1) GB2073489A (it)
IT (1) IT1136830B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3234907A1 (de) * 1982-09-21 1984-03-22 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten schaltung
JPS5955037A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体装置
JPS5982746A (ja) * 1982-11-04 1984-05-12 Toshiba Corp 半導体装置の電極配線方法
US4553044A (en) * 1983-05-11 1985-11-12 National Semiconductor Corporation Integrated circuit output driver stage
DE3741706A1 (de) * 1987-12-09 1989-06-22 Asea Brown Boveri Verfahren zur herstellung von spiralfoermigen duennfilm-flachspulen

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3210677A (en) * 1962-05-28 1965-10-05 Westinghouse Electric Corp Unipolar-bipolar semiconductor amplifier
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置

Also Published As

Publication number Publication date
DE3113333A1 (de) 1982-01-28
IT1136830B (it) 1986-09-03
JPS56140648A (en) 1981-11-04
GB2073489A (en) 1981-10-14

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