IT8025670A0 - Circuito di prova dotato di dispositivi mos. - Google Patents

Circuito di prova dotato di dispositivi mos.

Info

Publication number
IT8025670A0
IT8025670A0 IT8025670A IT2567080A IT8025670A0 IT 8025670 A0 IT8025670 A0 IT 8025670A0 IT 8025670 A IT8025670 A IT 8025670A IT 2567080 A IT2567080 A IT 2567080A IT 8025670 A0 IT8025670 A0 IT 8025670A0
Authority
IT
Italy
Prior art keywords
test circuit
mos devices
circuit equipped
mos
devices
Prior art date
Application number
IT8025670A
Other languages
English (en)
Other versions
IT1134111B (it
Inventor
Peter Draheim
Friedrich Hapke
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of IT8025670A0 publication Critical patent/IT8025670A0/it
Application granted granted Critical
Publication of IT1134111B publication Critical patent/IT1134111B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
IT25670/80A 1979-11-02 1980-10-30 Circuito di prova dotato di dispositivi mos IT1134111B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2944149A DE2944149C2 (de) 1979-11-02 1979-11-02 Integrierte Schaltungsanordnung in MOS-Technik

Publications (2)

Publication Number Publication Date
IT8025670A0 true IT8025670A0 (it) 1980-10-30
IT1134111B IT1134111B (it) 1986-07-24

Family

ID=6084909

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25670/80A IT1134111B (it) 1979-11-02 1980-10-30 Circuito di prova dotato di dispositivi mos

Country Status (6)

Country Link
US (1) US4398146A (it)
JP (1) JPS5674667A (it)
DE (1) DE2944149C2 (it)
FR (1) FR2468919A1 (it)
GB (1) GB2062879B (it)
IT (1) IT1134111B (it)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612499A (en) * 1983-11-07 1986-09-16 Texas Instruments Incorporated Test input demultiplexing circuit
JPS61265829A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体集積回路
FR2594553B1 (fr) * 1985-10-16 1989-02-03 Bendix Electronics Sa Interface de test pour circuit integre en technologie mos
JPS62144532A (ja) * 1985-12-17 1987-06-27 三菱電機株式会社 グル−プ・ケ−ブルの延焼防止法
US4733168A (en) * 1986-03-21 1988-03-22 Harris Corporation Test enabling circuit for enabling overhead test circuitry in programmable devices
US4970454A (en) * 1986-12-09 1990-11-13 Texas Instruments Incorporated Packaged semiconductor device with test circuits for determining fabrication parameters
DE3840225A1 (de) * 1988-11-29 1990-05-31 Siemens Ag Teststruktur und verfahren zur dynamischen belastungsmessung von in einer integrierten schaltung enthaltenen transistoren
KR910006241B1 (ko) * 1988-12-14 1991-08-17 삼성전자 주식회사 복수 테스트모드 선택회로
US5019772A (en) * 1989-05-23 1991-05-28 International Business Machines Corporation Test selection techniques
US5636226A (en) * 1989-12-14 1997-06-03 Texas Instruments Incorporated Fault sensing circuit and method
US5030904A (en) * 1990-02-13 1991-07-09 Hewlett-Packard Company Diagnostic system for integrated circuits using existing pads
US5126659A (en) * 1990-07-13 1992-06-30 Motorola, Inc. Enablement of a test mode in an electronic module with limited pin-outs
JPH0743399B2 (ja) * 1990-08-15 1995-05-15 富士通株式会社 半導体回路
US5161159A (en) * 1990-08-17 1992-11-03 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with multiple clocking for test mode entry
EP0475588B1 (en) * 1990-08-17 1996-06-26 STMicroelectronics, Inc. A semiconductor memory with inhibited test mode entry during power-up
JP3381929B2 (ja) * 1990-12-27 2003-03-04 株式会社東芝 半導体装置
US5432440A (en) * 1991-11-25 1995-07-11 At&T Global Information Solutions Company Detection of tri-state logic signals
US5294883A (en) * 1992-08-04 1994-03-15 International Business Machines Corporation Test detector/shutoff and method for BiCMOS integrated circuit
KR0132756B1 (ko) * 1993-03-15 1998-04-16 원본미기재 이씨엘(ecl) 회로의 번인 방법 및 장치
US5982188A (en) * 1994-07-29 1999-11-09 Stmicroelectronics, Inc. Test mode control circuit of an integrated circuit device
US5627478A (en) * 1995-07-06 1997-05-06 Micron Technology, Inc. Apparatus for disabling and re-enabling access to IC test functions
US5712575A (en) * 1995-12-18 1998-01-27 Micron Technology, Inc. Super-voltage circuit with a fast reset
US5796266A (en) 1996-03-18 1998-08-18 Micron Technology, Inc. Circuit and a method for configuring pad connections in an integrated device
DE69724318T2 (de) * 1996-04-02 2004-05-27 STMicroelectronics, Inc., Carrollton Prüfung und Reparatur einer eingebetteten Speicherschaltung
US5900739A (en) * 1996-09-24 1999-05-04 Advanced Micro Devices Inc. Method and apparatus for entering a test mode of an externally non-programmable device
US5944845A (en) 1997-06-26 1999-08-31 Micron Technology, Inc. Circuit and method to prevent inadvertent test mode entry
KR100311117B1 (ko) * 1998-06-29 2001-12-17 박종섭 반도체메모리소자의옵션기능테스트장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3772595A (en) * 1971-03-19 1973-11-13 Teradyne Inc Method and apparatus for testing a digital logic fet by monitoring currents the device develops in response to input signals
US3789205A (en) * 1972-09-28 1974-01-29 Ibm Method of testing mosfet planar boards
US4051352A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Level sensitive embedded array logic system
JPS5918742B2 (ja) * 1977-02-22 1984-04-28 シャープ株式会社 大規模集積回路
NL7704005A (nl) * 1977-04-13 1977-06-30 Philips Nv Geintegreerde schakeling.
DE2905294A1 (de) * 1979-02-12 1980-08-21 Philips Patentverwaltung Integrierte schaltungsanordnung in mos-technik mit feldeffekttransistoren
DE2905271A1 (de) * 1979-02-12 1980-08-21 Philips Patentverwaltung Integrierte schaltungsanordnung in mos-technik mit feldeffekttransistoren
DE2944148A1 (de) * 1979-11-02 1981-05-14 Philips Patentverwaltung Gmbh, 2000 Hamburg Integrierte schaltungsanordnung in mos-technik

Also Published As

Publication number Publication date
IT1134111B (it) 1986-07-24
FR2468919A1 (fr) 1981-05-08
DE2944149C2 (de) 1985-02-21
FR2468919B1 (it) 1983-11-18
JPS5674667A (en) 1981-06-20
DE2944149A1 (de) 1981-05-14
JPH0122909B2 (it) 1989-04-28
US4398146A (en) 1983-08-09
GB2062879A (en) 1981-05-28
GB2062879B (en) 1983-08-10

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