IT1290887B1 - Procedimento per ottimizzare la fabbricazione di circuiti integrati - Google Patents

Procedimento per ottimizzare la fabbricazione di circuiti integrati

Info

Publication number
IT1290887B1
IT1290887B1 IT97RM000007A ITRM970007A IT1290887B1 IT 1290887 B1 IT1290887 B1 IT 1290887B1 IT 97RM000007 A IT97RM000007 A IT 97RM000007A IT RM970007 A ITRM970007 A IT RM970007A IT 1290887 B1 IT1290887 B1 IT 1290887B1
Authority
IT
Italy
Prior art keywords
optimizing
procedure
manufacture
integrated circuits
circuits
Prior art date
Application number
IT97RM000007A
Other languages
English (en)
Inventor
Angelo Facchini
Antonio Serapiglia
Original Assignee
Consorzio Eagle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consorzio Eagle filed Critical Consorzio Eagle
Priority to IT97RM000007A priority Critical patent/IT1290887B1/it
Priority to US08/999,436 priority patent/US6016391A/en
Priority to EP98830002A priority patent/EP0854430A3/en
Publication of ITRM970007A1 publication Critical patent/ITRM970007A1/it
Application granted granted Critical
Publication of IT1290887B1 publication Critical patent/IT1290887B1/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT97RM000007A 1997-01-08 1997-01-08 Procedimento per ottimizzare la fabbricazione di circuiti integrati IT1290887B1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT97RM000007A IT1290887B1 (it) 1997-01-08 1997-01-08 Procedimento per ottimizzare la fabbricazione di circuiti integrati
US08/999,436 US6016391A (en) 1997-01-08 1997-12-29 Apparatus and method for optimizing integrated circuit fabrication
EP98830002A EP0854430A3 (en) 1997-01-08 1998-01-08 A method for optimizing integrated circuit fabrication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT97RM000007A IT1290887B1 (it) 1997-01-08 1997-01-08 Procedimento per ottimizzare la fabbricazione di circuiti integrati
US08/999,436 US6016391A (en) 1997-01-08 1997-12-29 Apparatus and method for optimizing integrated circuit fabrication

Publications (2)

Publication Number Publication Date
ITRM970007A1 ITRM970007A1 (it) 1998-07-08
IT1290887B1 true IT1290887B1 (it) 1998-12-14

Family

ID=26332109

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97RM000007A IT1290887B1 (it) 1997-01-08 1997-01-08 Procedimento per ottimizzare la fabbricazione di circuiti integrati

Country Status (3)

Country Link
US (1) US6016391A (it)
EP (1) EP0854430A3 (it)
IT (1) IT1290887B1 (it)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07211622A (ja) * 1994-01-27 1995-08-11 Nikon Corp 露光方法及び露光システム
US6070004A (en) * 1997-09-25 2000-05-30 Siemens Aktiengesellschaft Method of maximizing chip yield for semiconductor wafers
US6604233B1 (en) * 1999-06-28 2003-08-05 Texas Instruments Incorporated Method for optimizing the integrated circuit chip size for efficient manufacturing
US6826738B2 (en) * 2002-05-10 2004-11-30 Pdf Solutions, Inc. Optimization of die placement on wafers
DE10243755B4 (de) * 2002-09-20 2005-03-31 Infineon Technologies Ag Verfahren zum Bilden einer matrixförmigen Anordnung von Belichtungsfeldern auf einem idealisierten Halbleiterwafer
JP2004193208A (ja) * 2002-12-09 2004-07-08 Canon Inc 情報処理装置
US6980917B2 (en) * 2002-12-30 2005-12-27 Lsi Logic Corporation Optimization of die yield in a silicon wafer “sweet spot”
US7243325B2 (en) * 2004-07-21 2007-07-10 Bae Systems Information And Electronic Systems Integration Inc. Method and apparatus for generating a wafer map
US7305634B2 (en) * 2004-11-23 2007-12-04 Lsi Corporation Method to selectively identify at risk die based on location within the reticle
US7353077B2 (en) * 2005-07-29 2008-04-01 Taiwan Semiconductor Manufacturing Company Methods for optimizing die placement
US20080201677A1 (en) * 2007-02-21 2008-08-21 Faye Baker Integrated Circuit (IC) Chip Input/Output (I/O) Cell Design Optimization Method And IC chip With Optimized I/O Cells
JP4408298B2 (ja) * 2007-03-28 2010-02-03 株式会社日立ハイテクノロジーズ 検査装置及び検査方法
US8239788B2 (en) * 2009-08-07 2012-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Frame cell for shot layout flexibility
US8843860B2 (en) * 2009-08-07 2014-09-23 Taiwan Semiconductor Manufacturing Co., Ltd. Frame cell for shot layout flexibility
WO2011051785A2 (en) * 2009-10-30 2011-05-05 Synopsys, Inc. Routing method for flip chip package and apparatus using the same
CN103164567A (zh) * 2012-12-04 2013-06-19 天津蓝海微科技有限公司 一种根据流片数据拟合晶圆参数的方法
US9236351B2 (en) * 2013-10-09 2016-01-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor wafer device
CN103969942B (zh) * 2014-05-04 2017-08-25 湘能华磊光电股份有限公司 集成式光刻板制作方法及led芯片晶粒的分选方法
CN109271711B (zh) * 2018-09-25 2023-03-28 重庆大学 一种考虑不均匀特性的渗碳硬化齿轮有限元建模方法
US11163238B2 (en) * 2019-10-04 2021-11-02 Systems On Silicon Manufacturing Co. Pte. Ltd. Optimum layout of dies on a wafer
CN111653500A (zh) * 2020-06-19 2020-09-11 上海华力集成电路制造有限公司 判断晶圆良率损失的方法
EP3992715B1 (en) * 2020-09-09 2023-05-31 Changxin Memory Technologies, Inc. Wafer chip layout calculation method, medium and apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107633A (ja) * 1981-12-21 1983-06-27 Canon Inc 特殊チツプを逃げたシヨツト配列方法
US4843563A (en) * 1985-03-25 1989-06-27 Canon Kabushiki Kaisha Step-and-repeat alignment and exposure method and apparatus
US5561606A (en) * 1991-08-30 1996-10-01 Nikon Corporation Method for aligning shot areas on a substrate
JP3275368B2 (ja) * 1992-07-09 2002-04-15 株式会社ニコン 露光方法及び装置
US5521036A (en) * 1992-07-27 1996-05-28 Nikon Corporation Positioning method and apparatus
JPH07211622A (ja) * 1994-01-27 1995-08-11 Nikon Corp 露光方法及び露光システム
KR100377887B1 (ko) * 1994-02-10 2003-06-18 가부시키가이샤 니콘 정렬방법
JPH0927445A (ja) * 1995-07-13 1997-01-28 Nikon Corp ショットマップ作成方法
JPH0950951A (ja) * 1995-08-04 1997-02-18 Nikon Corp リソグラフィ方法およびリソグラフィ装置

Also Published As

Publication number Publication date
US6016391A (en) 2000-01-18
EP0854430A3 (en) 1999-08-04
EP0854430A2 (en) 1998-07-22
ITRM970007A1 (it) 1998-07-08

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Legal Events

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0001 Granted