IT1191755B - Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido - Google Patents

Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido

Info

Publication number
IT1191755B
IT1191755B IT20253/86A IT2025386A IT1191755B IT 1191755 B IT1191755 B IT 1191755B IT 20253/86 A IT20253/86 A IT 20253/86A IT 2025386 A IT2025386 A IT 2025386A IT 1191755 B IT1191755 B IT 1191755B
Authority
IT
Italy
Prior art keywords
oxide
nitride
manufacturing process
eprom cells
dielectric
Prior art date
Application number
IT20253/86A
Other languages
English (en)
Other versions
IT8620253A0 (it
IT8620253A1 (it
Inventor
Gabriella Ghidini
Giuseppe Crisenza
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT20253/86A priority Critical patent/IT1191755B/it
Publication of IT8620253A0 publication Critical patent/IT8620253A0/it
Priority to DE87200615T priority patent/DE3784758T2/de
Priority to EP87200615A priority patent/EP0243999B1/en
Priority to US07/040,152 priority patent/US4808261A/en
Priority to JP62096391A priority patent/JPH07112020B2/ja
Publication of IT8620253A1 publication Critical patent/IT8620253A1/it
Application granted granted Critical
Publication of IT1191755B publication Critical patent/IT1191755B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
IT20253/86A 1986-04-29 1986-04-29 Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido IT1191755B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT20253/86A IT1191755B (it) 1986-04-29 1986-04-29 Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido
DE87200615T DE3784758T2 (de) 1986-04-29 1987-04-02 Herstellungsverfahren für EPROM-Zellen mit Oxid-Nitrid-oxid-Dielektrikum.
EP87200615A EP0243999B1 (en) 1986-04-29 1987-04-02 Fabrication process for eprom cells with oxide-nitride-oxide dielectric
US07/040,152 US4808261A (en) 1986-04-29 1987-04-20 Fabrication process for EPROM cells with oxide-nitride-oxide dielectric
JP62096391A JPH07112020B2 (ja) 1986-04-29 1987-04-21 Ｅｐｒｏｍセルの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20253/86A IT1191755B (it) 1986-04-29 1986-04-29 Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido

Publications (3)

Publication Number Publication Date
IT8620253A0 IT8620253A0 (it) 1986-04-29
IT8620253A1 IT8620253A1 (it) 1987-10-29
IT1191755B true IT1191755B (it) 1988-03-23

Family

ID=11165173

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20253/86A IT1191755B (it) 1986-04-29 1986-04-29 Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido

Country Status (5)

Country Link
US (1) US4808261A (it)
EP (1) EP0243999B1 (it)
JP (1) JPH07112020B2 (it)
DE (1) DE3784758T2 (it)
IT (1) IT1191755B (it)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1215559B (it) * 1987-06-11 1990-02-14 Sgs Microelettronica Spa Processo di fabbricazione per celle di memoria non volatili epromelettricamente cancellabili e cella cosi' ottenuta.
GB2220735A (en) * 1988-07-04 1990-01-17 Geoffrey Philip Beastall Light emitting diode torch
FR2635410B1 (fr) * 1988-08-11 1991-08-02 Sgs Thomson Microelectronics Memoire de type eprom a haute densite d'integration avec une organisation en damier et un facteur de couplage ameliore et procede de fabrication
US4966864A (en) * 1989-03-27 1990-10-30 Motorola, Inc. Contact structure and method
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5010028A (en) * 1989-12-29 1991-04-23 Texas Instruments Incorporated Method of making hot electron programmable, tunnel electron erasable contactless EEPROM
US5063172A (en) * 1990-06-28 1991-11-05 National Semiconductor Corporation Manufacture of a split-gate EPROM cell using polysilicon spacers
JPH0491469A (ja) * 1990-08-01 1992-03-24 Sharp Corp 不揮発性半導体メモリ
US5120670A (en) * 1991-04-18 1992-06-09 National Semiconductor Corporation Thermal process for implementing the planarization inherent to stacked etch in virtual ground EPROM memories
EP0571692B1 (en) * 1992-05-27 1998-07-22 STMicroelectronics S.r.l. EPROM cell with a readily scalable down interpoly dielectric
KR960009995B1 (ko) * 1992-07-31 1996-07-25 삼성전자 주식회사 반도체 장치의 제조 방법 및 그 구조
US5619052A (en) * 1994-09-29 1997-04-08 Macronix International Co., Ltd. Interpoly dielectric structure in EEPROM device
US5567638A (en) * 1995-06-14 1996-10-22 National Science Council Method for suppressing boron penetration in PMOS with nitridized polysilicon gate
US5937310A (en) * 1996-04-29 1999-08-10 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
US5726100A (en) * 1996-06-27 1998-03-10 Micron Technology, Inc. Method of forming contact vias and interconnect channels in a dielectric layer stack with a single mask
US5882993A (en) 1996-08-19 1999-03-16 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness and process for making same
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
US5872376A (en) * 1997-03-06 1999-02-16 Advanced Micro Devices, Inc. Oxide formation technique using thin film silicon deposition
US5962914A (en) * 1998-01-14 1999-10-05 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
TW409428B (en) * 1998-03-20 2000-10-21 Seiko Epson Corp Non-volatile semiconductor memory apparatus and the manufacture method thereof
US6531364B1 (en) 1998-08-05 2003-03-11 Advanced Micro Devices, Inc. Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer
US6495475B2 (en) 2001-03-28 2002-12-17 Atmel Corporation Method for fabrication of a high capacitance interpoly dielectric
US6589843B1 (en) 2002-01-09 2003-07-08 Micron Technology, Inc. Methods of forming FLASH field effect transistor gates and non-FLASH field effect transistor gates
US20030232507A1 (en) * 2002-06-12 2003-12-18 Macronix International Co., Ltd. Method for fabricating a semiconductor device having an ONO film
US6864163B1 (en) * 2002-10-30 2005-03-08 Advanced Micro Devices, Inc. Fabrication of dual work-function metal gate structure for complementary field effect transistors

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5159281A (en) * 1974-11-20 1976-05-24 Mitsubishi Electric Corp Handotaisochino seizoho
JPS53124084A (en) * 1977-04-06 1978-10-30 Hitachi Ltd Semiconductor memory device containing floating type poly silicon layer and its manufacture
JPS5955071A (ja) * 1982-09-24 1984-03-29 Hitachi Micro Comput Eng Ltd 不揮発性半導体装置
US4688078A (en) * 1982-09-30 1987-08-18 Ning Hseih Partially relaxable composite dielectric structure
JPS59119871A (ja) * 1982-12-27 1984-07-11 Fujitsu Ltd 不揮発性半導体記憶装置の製造方法
US4577390A (en) * 1983-02-23 1986-03-25 Texas Instruments Incorporated Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer
US4458407A (en) * 1983-04-01 1984-07-10 International Business Machines Corporation Process for fabricating semi-conductive oxide between two poly silicon gate electrodes
JPS6068658A (ja) * 1983-09-26 1985-04-19 Fujitsu Ltd 半導体装置の製造方法
JPS61136274A (ja) * 1984-12-07 1986-06-24 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
JPH07112020B2 (ja) 1995-11-29
DE3784758D1 (de) 1993-04-22
EP0243999B1 (en) 1993-03-17
EP0243999A2 (en) 1987-11-04
JPS62257768A (ja) 1987-11-10
IT8620253A0 (it) 1986-04-29
EP0243999A3 (en) 1988-02-03
US4808261A (en) 1989-02-28
IT8620253A1 (it) 1987-10-29
DE3784758T2 (de) 1993-10-07

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429