IT1189143B - Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos - Google Patents
Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmosInfo
- Publication number
- IT1189143B IT1189143B IT20460/86A IT2046086A IT1189143B IT 1189143 B IT1189143 B IT 1189143B IT 20460/86 A IT20460/86 A IT 20460/86A IT 2046086 A IT2046086 A IT 2046086A IT 1189143 B IT1189143 B IT 1189143B
- Authority
- IT
- Italy
- Prior art keywords
- mos
- insulation
- implementation
- procedure
- integrated circuits
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT20460/86A IT1189143B (it) | 1986-05-16 | 1986-05-16 | Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos |
EP87106645A EP0245783A3 (en) | 1986-05-16 | 1987-05-07 | Insulation method for integrated circuits, in particular with mos and cmos devices |
JP62119957A JPS62285440A (ja) | 1986-05-16 | 1987-05-15 | 集積回路のための絶縁方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT20460/86A IT1189143B (it) | 1986-05-16 | 1986-05-16 | Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos |
Publications (3)
Publication Number | Publication Date |
---|---|
IT8620460A0 IT8620460A0 (it) | 1986-05-16 |
IT8620460A1 IT8620460A1 (it) | 1987-11-16 |
IT1189143B true IT1189143B (it) | 1988-01-28 |
Family
ID=11167280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT20460/86A IT1189143B (it) | 1986-05-16 | 1986-05-16 | Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0245783A3 (it) |
JP (1) | JPS62285440A (it) |
IT (1) | IT1189143B (it) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01185936A (ja) * | 1988-01-21 | 1989-07-25 | Fujitsu Ltd | 半導体装置 |
JPH05109762A (ja) * | 1991-05-16 | 1993-04-30 | Internatl Business Mach Corp <Ibm> | 半導体装置及びその製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4238278A (en) * | 1979-06-14 | 1980-12-09 | International Business Machines Corporation | Polycrystalline silicon oxidation method for making shallow and deep isolation trenches |
JPS5958838A (ja) * | 1982-09-29 | 1984-04-04 | Hitachi Ltd | 半導体装置 |
FR2598557B1 (fr) * | 1986-05-09 | 1990-03-30 | Seiko Epson Corp | Procede de fabrication d'une region d'isolation d'element d'un dispositif a semi-conducteurs |
-
1986
- 1986-05-16 IT IT20460/86A patent/IT1189143B/it active
-
1987
- 1987-05-07 EP EP87106645A patent/EP0245783A3/en not_active Withdrawn
- 1987-05-15 JP JP62119957A patent/JPS62285440A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPS62285440A (ja) | 1987-12-11 |
EP0245783A3 (en) | 1989-10-25 |
IT8620460A0 (it) | 1986-05-16 |
IT8620460A1 (it) | 1987-11-16 |
EP0245783A2 (en) | 1987-11-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3782367D1 (de) | Mos-halbleiterschaltung. | |
EP0242623A3 (en) | Mos semiconductor device and method of manufacturing the same | |
IT8722659A0 (it) | Dispositivo semiconduttore e metodo di fabbricazione dello stesso. | |
GB2198285B (en) | Bipolar transistor and method of manufacturing the same | |
DE3774253D1 (de) | Spannungsschalter in mos-technologie. | |
EP0253664A3 (en) | Semiconductor photo-sensor and method for manufacturing the same | |
IT1190325B (it) | Circuito di polarizzazione per dispositivi integrati in tecnologia mos,particolarmente di tipo misto digitale-analogico | |
DE3686310T2 (de) | Dielektrisch isoliertes integriertes halbleiterbauelement und herstellungsverfahren. | |
GB2168534B (en) | Integrated power mos bridge circuit and method | |
IT1185638B (it) | Amplificatore operazionale tutto differenziale per circuiti integrati in tecnologia mos | |
ITTO910929A0 (it) | Procedimento per la fabbricazione di circuiti integrati in tecnologia mos | |
EP0231811A3 (en) | Method for manufacturing integrated electronic devices, in particular high voltage p-channel mos transistors | |
DE3787500T2 (de) | Isolierharz-Zusammensetzung und Halbleitervorrichtung unter deren Verwendung. | |
DE3583113D1 (de) | Integrierte halbleiterschaltungsanordnung in polycell-technik. | |
DE3278605D1 (en) | Intermediate structure for use in the manufacture of semiconductor devices, method of making field effect transistors and transistors | |
GB2168845B (en) | Bipolar transistor integrated circuit and method of manufacturing the same | |
DE3774737D1 (de) | Abschaltbares halbleiterbauelement sowie verwendung desselben. | |
DE3380285D1 (en) | Mos semiconductor device and method of producing the same | |
FR2568723B1 (fr) | Circuit integre notamment de type mos et son procede de fabrication | |
IT1189143B (it) | Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos | |
IT1204375B (it) | Generatore di polarizzazione di sorgenti per transistori naturali in circuiti integrati digitali in tecnologia mos | |
IT1210751B (it) | Sommatore veloce in tecnologia c mos | |
EP0255133A3 (en) | Mos field-effect transistor and method of making the same | |
IT1225625B (it) | Procedimento per la realizzazione di strutture di isolamento incassate nel substrato di silicio per dispositivi cmos ed nmos. | |
IT1224656B (it) | Procedimento per la fabbricazione di condensatori integrati in tecnologia mos. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970530 |