IT1140878B - Metodo di fabricazione di un transistore ad effetto di campo, a porta isolata e transistore fabbricato con l'ausilio di tale metodo - Google Patents

Metodo di fabricazione di un transistore ad effetto di campo, a porta isolata e transistore fabbricato con l'ausilio di tale metodo

Info

Publication number
IT1140878B
IT1140878B IT21514/80A IT2151480A IT1140878B IT 1140878 B IT1140878 B IT 1140878B IT 21514/80 A IT21514/80 A IT 21514/80A IT 2151480 A IT2151480 A IT 2151480A IT 1140878 B IT1140878 B IT 1140878B
Authority
IT
Italy
Prior art keywords
zones
mask
channel
conductivity type
oxide
Prior art date
Application number
IT21514/80A
Other languages
English (en)
Other versions
IT8021514A0 (it
Inventor
Pieter Jochems
Johannes Wilhelmus
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of IT8021514A0 publication Critical patent/IT8021514A0/it
Application granted granted Critical
Publication of IT1140878B publication Critical patent/IT1140878B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/911Differential oxidation and etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT21514/80A 1979-04-23 1980-04-18 Metodo di fabricazione di un transistore ad effetto di campo, a porta isolata e transistore fabbricato con l'ausilio di tale metodo IT1140878B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7903158A NL7903158A (nl) 1979-04-23 1979-04-23 Werkwijze voor het vervaardigen van een veldeffekt- transistor met geisoleerde poortelektrode, en transistor vervaardigd door toepassing van een derge- lijke werkwijze.

Publications (2)

Publication Number Publication Date
IT8021514A0 IT8021514A0 (it) 1980-04-18
IT1140878B true IT1140878B (it) 1986-10-10

Family

ID=19833027

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21514/80A IT1140878B (it) 1979-04-23 1980-04-18 Metodo di fabricazione di un transistore ad effetto di campo, a porta isolata e transistore fabbricato con l'ausilio di tale metodo

Country Status (10)

Country Link
US (1) US4343079A (it)
JP (1) JPS55141758A (it)
AU (1) AU537858B2 (it)
CA (1) CA1146675A (it)
CH (1) CH653482A5 (it)
DE (1) DE3015101A1 (it)
FR (1) FR2455361A1 (it)
GB (1) GB2047961B (it)
IT (1) IT1140878B (it)
NL (1) NL7903158A (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5252505A (en) * 1979-05-25 1993-10-12 Hitachi, Ltd. Method for manufacturing a semiconductor device
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device
JPS60106142A (ja) * 1983-11-15 1985-06-11 Nec Corp 半導体素子の製造方法
US4675982A (en) * 1985-10-31 1987-06-30 International Business Machines Corporation Method of making self-aligned recessed oxide isolation regions
EP0940851B1 (en) 1992-07-31 2005-10-05 Hughes Electronics Corporation Integrated circuit security system and method with implanted interconnections
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
JPS5528229B1 (it) * 1971-03-19 1980-07-26
FR2134290B1 (it) * 1971-04-30 1977-03-18 Texas Instruments France
NL7113561A (it) * 1971-10-02 1973-04-04
US4023195A (en) * 1974-10-23 1977-05-10 Smc Microsystems Corporation MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions
US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
JPS52131483A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Mis-type semiconductor device
NL185376C (nl) * 1976-10-25 1990-03-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
JPS53123661A (en) * 1977-04-04 1978-10-28 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS53123678A (en) * 1977-04-04 1978-10-28 Nec Corp Manufacture of field effect semiconductor device of insulation gate type
JPS53144280A (en) * 1977-05-23 1978-12-15 Hitachi Ltd Mis semiconductor device
US4268950A (en) * 1978-06-05 1981-05-26 Texas Instruments Incorporated Post-metal ion implant programmable MOS read only memory
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Also Published As

Publication number Publication date
GB2047961A (en) 1980-12-03
CA1146675A (en) 1983-05-17
DE3015101C2 (it) 1990-03-29
US4343079A (en) 1982-08-10
GB2047961B (en) 1983-08-03
AU5765180A (en) 1980-10-30
DE3015101A1 (de) 1980-11-06
AU537858B2 (en) 1984-07-19
FR2455361B1 (it) 1983-04-29
JPS55141758A (en) 1980-11-05
IT8021514A0 (it) 1980-04-18
CH653482A5 (de) 1985-12-31
FR2455361A1 (fr) 1980-11-21
NL7903158A (nl) 1980-10-27

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