IN2012DN03251A - - Google Patents

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Publication number
IN2012DN03251A
IN2012DN03251A IN3251DEN2012A IN2012DN03251A IN 2012DN03251 A IN2012DN03251 A IN 2012DN03251A IN 3251DEN2012 A IN3251DEN2012 A IN 3251DEN2012A IN 2012DN03251 A IN2012DN03251 A IN 2012DN03251A
Authority
IN
India
Prior art keywords
substrate
core
terminals
coupled
layers
Prior art date
Application number
Inventor
Qing Ma
Chuan Hu
Patrick Morrow
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2012DN03251A publication Critical patent/IN2012DN03251A/en

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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Abstract

Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.
IN3251DEN2012 2009-12-17 2010-11-01 IN2012DN03251A (en)

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US12/653,722 US9420707B2 (en) 2009-12-17 2009-12-17 Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
PCT/US2010/054931 WO2011084216A2 (en) 2009-12-17 2010-11-01 Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

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US20160322290A1 (en) 2016-11-03

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