IL69320A0 - Clock pulse generating circuit arrangement for a telecommunications system - Google Patents
Clock pulse generating circuit arrangement for a telecommunications systemInfo
- Publication number
- IL69320A0 IL69320A0 IL69320A IL6932083A IL69320A0 IL 69320 A0 IL69320 A0 IL 69320A0 IL 69320 A IL69320 A IL 69320A IL 6932083 A IL6932083 A IL 6932083A IL 69320 A0 IL69320 A0 IL 69320A0
- Authority
- IL
- Israel
- Prior art keywords
- exchange clock
- exchange
- clock signal
- slave
- clock generator
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Time-Division Multiplex Systems (AREA)
- Communication Control (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
1. A circuit arrangement for telecommunications systems, in particular PCM telephone exchange systems, with a duplicated exchange clock supply arrangement (CCG', CCG") in which the respective first of the two exchange clock generators supplies an exchange clock signal (T', T") which is generated independently of the respective other exchange clock generator, and the respective other (slave) exchange clock generator supplies an exchange clock signal which is synchronised so as to be at least approximately in phase with the exchange clock signal supplied by the respective first (master) exchange clock generator, and in which each of the two exchange clock generators, servo-synchronised by a supplied master clock signal (M', M"), generates an intermediate clock signal (H', H") with a clock period which at the maximum is equal to the maximum permissible phase difference between the exchange clock signals supplied by the two exchange clock generators, and in which, in each of the two exchange clock generators, the intermediate clock signal is supplied to a respective frequency divider (BKU, U) for the acquisition of the exchange clock signal, and in which the respective slave exchange clock generator compares its exchange clock signal with the exchange clock signal of the respective master exchange clock generator (PD) and when a phase difference is established which exceeds a limit value in the order of one intermediate clock period (h) by means of a regulating device in the case of a lagging slave exchange clock signal shortens-and in the case of a leading exchange clock signal lengthen-one half period of the slave exchange clock signal by the length of one intermediate clock period, and in which the exchange clock signal supplied by the respective master exchange clock generator is monitored and in the event of the failure thereof the regulating device of the hitherto slave exchange clock generator is disconnected, whereby the hitherto slave exchange clock generator now becomes the master exchange clock generator whose exchange clock signal is now supplied to the hitherto master exchange clock generator which has now become the slave exchange clock generator, characterised in that when it establishes a leading or lagging of the initially slave exchange clock signal the regulating device (UVR) of the initially slave exchange clock generator lengthens or shortens respectively the half period of the exchange clock signal supplied by itself with a time delay which is at least equal to the time interval required to disconnect the regulating device of the slave exchange clock generator in the event of the failure of the master exchange clock signal.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19823227848 DE3227848A1 (en) | 1982-07-26 | 1982-07-26 | CIRCUIT FOR CLOCK GENERATION IN TELECOMMUNICATION SYSTEMS, IN PARTICULAR TIME MULTIPLEX-DIGITAL SWITCHING SYSTEMS |
Publications (1)
Publication Number | Publication Date |
---|---|
IL69320A0 true IL69320A0 (en) | 1983-11-30 |
Family
ID=6169337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL69320A IL69320A0 (en) | 1982-07-26 | 1983-07-25 | Clock pulse generating circuit arrangement for a telecommunications system |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0100076B1 (en) |
JP (1) | JPS5934793A (en) |
AT (1) | ATE35203T1 (en) |
DE (1) | DE3227848A1 (en) |
IL (1) | IL69320A0 (en) |
ZA (1) | ZA835406B (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3227849A1 (en) * | 1982-07-26 | 1984-01-26 | Siemens AG, 1000 Berlin und 8000 München | CIRCUIT FOR CLOCK GENERATION IN TELECOMMUNICATION SYSTEMS, IN PARTICULAR TIME MULTIPLEX-DIGITAL SWITCHING SYSTEMS |
JPS60192027U (en) * | 1984-05-30 | 1985-12-20 | 明星電気株式会社 | microprocessor clock circuit |
US4651103A (en) * | 1985-12-30 | 1987-03-17 | At&T Company | Phase adjustment system |
JPH0817374B2 (en) * | 1987-11-25 | 1996-02-21 | 日本電気株式会社 | Clock transmission method |
JPH0797328B2 (en) * | 1988-10-25 | 1995-10-18 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | False tolerant synchronization system |
ATE126633T1 (en) * | 1989-11-29 | 1995-09-15 | Siemens Ag | CIRCUIT ARRANGEMENT FOR CLOCK REGENERATION IN CLOCK-CONTROLLED INFORMATION PROCESSING SYSTEMS. |
ATE161671T1 (en) * | 1992-08-18 | 1998-01-15 | Siemens Ag | ARRANGEMENT FOR GENERATING A CLOCK SIGNAL WITH BIT-EXACT GAPS |
DE10297775D2 (en) * | 2002-05-27 | 2005-04-21 | Siemens Ag | Method and circuit for clock switching between two clocks provided, in particular for peripheral modules of telecommunication systems |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2907608A1 (en) * | 1979-02-27 | 1980-08-28 | Siemens Ag | CIRCUIT FOR CLOCK GENERATION IN TELECOMMUNICATION SYSTEMS, IN PARTICULAR TIME MULTIPLEX-DIGITAL SWITCHING SYSTEMS |
FR2473235A1 (en) * | 1980-01-08 | 1981-07-10 | Schirlin Marcel | Beat recovering circuit for master-slave sync. system - uses phase-locked loop surveillance delay lines checking signal errors in sync. lines |
DE3227849A1 (en) * | 1982-07-26 | 1984-01-26 | Siemens AG, 1000 Berlin und 8000 München | CIRCUIT FOR CLOCK GENERATION IN TELECOMMUNICATION SYSTEMS, IN PARTICULAR TIME MULTIPLEX-DIGITAL SWITCHING SYSTEMS |
-
1982
- 1982-07-26 DE DE19823227848 patent/DE3227848A1/en active Granted
-
1983
- 1983-07-22 EP EP83107222A patent/EP0100076B1/en not_active Expired
- 1983-07-22 AT AT83107222T patent/ATE35203T1/en not_active IP Right Cessation
- 1983-07-25 ZA ZA835406A patent/ZA835406B/en unknown
- 1983-07-25 IL IL69320A patent/IL69320A0/en unknown
- 1983-07-25 JP JP58134528A patent/JPS5934793A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
EP0100076A2 (en) | 1984-02-08 |
EP0100076B1 (en) | 1988-06-15 |
DE3227848A1 (en) | 1984-01-26 |
DE3227848C2 (en) | 1987-07-02 |
ATE35203T1 (en) | 1988-07-15 |
ZA835406B (en) | 1984-03-28 |
JPH021479B2 (en) | 1990-01-11 |
EP0100076A3 (en) | 1985-10-16 |
JPS5934793A (en) | 1984-02-25 |
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