IL112737A0 - Method and apparatus for controlling dynamic random access memory devices - Google Patents
Method and apparatus for controlling dynamic random access memory devicesInfo
- Publication number
- IL112737A0 IL112737A0 IL11273795A IL11273795A IL112737A0 IL 112737 A0 IL112737 A0 IL 112737A0 IL 11273795 A IL11273795 A IL 11273795A IL 11273795 A IL11273795 A IL 11273795A IL 112737 A0 IL112737 A0 IL 112737A0
- Authority
- IL
- Israel
- Prior art keywords
- random access
- access memory
- memory devices
- dynamic random
- controlling dynamic
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/203,209 US5386383A (en) | 1994-02-28 | 1994-02-28 | Method and apparatus for controlling dynamic random access memory devices |
Publications (1)
Publication Number | Publication Date |
---|---|
IL112737A0 true IL112737A0 (en) | 1995-05-26 |
Family
ID=22752969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL11273795A IL112737A0 (en) | 1994-02-28 | 1995-02-22 | Method and apparatus for controlling dynamic random access memory devices |
Country Status (6)
Country | Link |
---|---|
US (1) | US5386383A (xx) |
EP (1) | EP0669621A1 (xx) |
JP (1) | JPH07254270A (xx) |
KR (1) | KR950033841A (xx) |
CA (1) | CA2142044A1 (xx) |
IL (1) | IL112737A0 (xx) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6725349B2 (en) * | 1994-12-23 | 2004-04-20 | Intel Corporation | Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory |
US5572686A (en) * | 1995-06-05 | 1996-11-05 | Apple Computer, Inc. | Bus arbitration scheme with priority switching and timer |
US5619471A (en) * | 1995-06-06 | 1997-04-08 | Apple Computer, Inc. | Memory controller for both interleaved and non-interleaved memory |
US5737572A (en) * | 1995-06-06 | 1998-04-07 | Apple Computer, Inc. | Bank selection logic for memory controllers |
US5555209A (en) * | 1995-08-02 | 1996-09-10 | Simple Technology, Inc. | Circuit for latching data signals from DRAM memory |
US5802603A (en) * | 1996-02-09 | 1998-09-01 | Intel Corporation | Method and apparatus for asymmetric/symmetric DRAM detection |
US6253302B1 (en) * | 1996-08-29 | 2001-06-26 | Intel Corporation | Method and apparatus for supporting multiple overlapping address spaces on a shared bus |
US5996042A (en) * | 1996-12-16 | 1999-11-30 | Intel Corporation | Scalable, high bandwidth multicard memory system utilizing a single memory controller |
KR100532369B1 (ko) * | 1997-05-20 | 2006-01-27 | 삼성전자주식회사 | 멀티 뱅크 제어장치 및 멀티 뱅크 제어장치를 구비한 메모리 모듈 |
US6001662A (en) * | 1997-12-02 | 1999-12-14 | International Business Machines Corporation | Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits |
US6282622B1 (en) * | 1998-08-10 | 2001-08-28 | Joseph Norman Morris | System, method, and program for detecting and assuring DRAM arrays |
JP4675442B2 (ja) * | 1999-11-02 | 2011-04-20 | 富士通セミコンダクター株式会社 | メモリデバイス |
US6529433B2 (en) * | 2001-04-03 | 2003-03-04 | Hynix Semiconductor, Inc. | Refresh mechanism in dynamic memories |
US6687172B2 (en) * | 2002-04-05 | 2004-02-03 | Intel Corporation | Individual memory page activity timing method and system |
KR100924303B1 (ko) * | 2008-02-22 | 2009-11-02 | 인하대학교 산학협력단 | 메모리 어드레스의 모니터링 방법 및 장치 |
US8959420B1 (en) * | 2012-12-19 | 2015-02-17 | Datadirect Networks, Inc. | Data storage system and method for data migration between high-performance computing architectures and data storage devices using memory controller with embedded XOR capability |
CN103197753A (zh) * | 2013-03-25 | 2013-07-10 | 西安华芯半导体有限公司 | 一种darm存储器省电方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4533843A (en) * | 1978-09-07 | 1985-08-06 | Texas Instruments Incorporated | High performance dynamic sense amplifier with voltage boost for row address lines |
IT1153611B (it) * | 1982-11-04 | 1987-01-14 | Honeywell Inf Systems | Procedimento di mappatura della memoria in sistema di elaborazione dati |
US4757503A (en) * | 1985-01-18 | 1988-07-12 | The University Of Michigan | Self-testing dynamic ram |
JP2523586B2 (ja) * | 1987-02-27 | 1996-08-14 | 株式会社日立製作所 | 半導体記憶装置 |
GB2204721B (en) * | 1987-05-11 | 1991-10-23 | Apple Computer | Method and apparatus for determining available memory size |
US4782487A (en) * | 1987-05-15 | 1988-11-01 | Digital Equipment Corporation | Memory test method and apparatus |
US5003506A (en) * | 1987-06-02 | 1991-03-26 | Anritsu Corporation | Memory capacity detection apparatus and electronic applied measuring device employing the same |
JPH01196647A (ja) * | 1988-01-31 | 1989-08-08 | Nec Corp | 誤り訂正機能を有する記憶装置 |
US4980888A (en) * | 1988-09-12 | 1990-12-25 | Digital Equipment Corporation | Memory testing system |
JPH02146199A (ja) * | 1988-11-28 | 1990-06-05 | Mitsubishi Electric Corp | 半導体記憶装置のテスト回路 |
EP0382360B1 (en) * | 1989-02-08 | 1997-03-19 | Texas Instruments Incorporated | Event qualified testing architecture for integrated circuits |
GB2228112A (en) * | 1989-02-09 | 1990-08-15 | Acer Inc | Computer system and method |
JPH03148732A (ja) * | 1989-07-31 | 1991-06-25 | Texas Instr Inc <Ti> | 状態監視器を備えたデータ処理装置 |
US5228045A (en) * | 1990-08-06 | 1993-07-13 | Ncr Corporation | Test driver for connecting a standard test port integrated circuit chip to a controlling computer |
US5231605A (en) * | 1991-01-31 | 1993-07-27 | Micron Technology, Inc. | DRAM compressed data test mode with expected data |
US5278801A (en) * | 1992-08-31 | 1994-01-11 | Hewlett-Packard Company | Flexible addressing for drams |
-
1994
- 1994-02-28 US US08/203,209 patent/US5386383A/en not_active Expired - Lifetime
-
1995
- 1995-02-08 CA CA002142044A patent/CA2142044A1/en not_active Abandoned
- 1995-02-15 EP EP95300940A patent/EP0669621A1/en not_active Withdrawn
- 1995-02-22 IL IL11273795A patent/IL112737A0/xx unknown
- 1995-02-24 KR KR1019950003599A patent/KR950033841A/ko not_active Application Discontinuation
- 1995-02-27 JP JP7061512A patent/JPH07254270A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0669621A1 (en) | 1995-08-30 |
US5386383A (en) | 1995-01-31 |
JPH07254270A (ja) | 1995-10-03 |
KR950033841A (ko) | 1995-12-26 |
CA2142044A1 (en) | 1995-08-29 |
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