GB762693A - Data processing device - Google Patents
Data processing deviceInfo
- Publication number
- GB762693A GB762693A GB7959/54A GB795954A GB762693A GB 762693 A GB762693 A GB 762693A GB 7959/54 A GB7959/54 A GB 7959/54A GB 795954 A GB795954 A GB 795954A GB 762693 A GB762693 A GB 762693A
- Authority
- GB
- United Kingdom
- Prior art keywords
- adder
- digit
- sign
- input
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3832—Less usual number representations
- G06F2207/3836—One's complement
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
762,693. Digital electric calculating-apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. March 18, 1954 [March 19, 1953], No. 7959/54. Class 106 (1). In a device for forming the twos complement (ones complement plus unity) of a signed series mode binary number, the sign digit coming first in time and the most significant digit last, the number passes through a device 1, Fig. 1, which leaves the sign digit unaltered but inverts the following digits if the sign digit is negative or leaves them unchanged if it is positive, and enters an input 7 of a two input adder 6, having an internal carry loop formed by a unit-delay 10 and a gate 11, where it has unity added to it if its sign is negative or zero if its sign is positive, the " one " which is added if the number is negative actually being the sign digit which is gated by the device 1 via a unit delay 5 to the second input 8 of the adder 6. The number leaves the adder via a terminal 13, passes through a minor cycle delay 14 and re-enters the adder to allow round carry into only the first digit position of the number, carry from the first to second position (i.e. from the sign digit position to the least significant denomination of the binary number) being prevented by a gate 11 which is closed every second digit period by a control pulse. The device has the property that the number - 0 is converted into + 0 by it. An accumulator, Fig. 2, differs sub. stantially from Fig. 1 only in that the adder 6 is replaced by a three input adder. The main storage circulation path for the accumulator is via a delay 14 and one input 23 of the adder. As shown the accumulator of Fig. 2 contains a device 24 in its output lead which could be a further twos complementor. Suitable diode gating circuits and pulse-shaping circuits are described.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1077057T | 1953-03-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB762693A true GB762693A (en) | 1956-12-05 |
Family
ID=9607952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB7959/54A Expired GB762693A (en) | 1953-03-19 | 1954-03-18 | Data processing device |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR1077057A (en) |
GB (1) | GB762693A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2982472A (en) * | 1955-05-02 | 1961-05-02 | Harry D Huskey | Binary digital computer with magnetic drum storage |
-
1953
- 1953-03-19 FR FR1077057D patent/FR1077057A/en not_active Expired
-
1954
- 1954-03-18 GB GB7959/54A patent/GB762693A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR1077057A (en) | 1954-11-04 |
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