GB833781A - Improvements in binary digital parallel adders - Google Patents

Abstract

833,781. Binary parallel adders. SPERRY RAND CORPORATION. April 10, 1957 [April 12, 1956], No. 11670/57. Class 106 (1). [Also in Group XL (c)] In a binary parallel adder, each stage includes transistor gating means for propagating carries. In the binary adder shown in Fig. 1, the addend is applied via terminals 10, 11 ... 12 and delays D1, D2 ... Dn to half-adder accumulator circuits (called half adders ") HA-1, HA-2 ... HA-n which each provide sum outputs 0 and 1 and carry output C. When a new addend is entered, carries are stored on " flip-flops " FF-1, FF-2 ... FF-n (cleared by pulses on line 17) in the next higher stages; each carry allows a subsequent carry gate pulse on line 14 to pass through a corresponding gate G1a, G16 ... G1n to the associated accumulator inputs, and if any accumulator circuit registers 1, an associated gate G2a, G2b ... G2n is opened to allow the carry pulse to be propagated also along line 18 to higher stages. According to the invention, gates G2a &c. comprise transistors such as NPN junction type transistors 20, 21, 22, Fig. 2. Also, the carry storage flip-flops may be replaced by transistors such as 30, Fig. 3A, arranged to be overdriven by a carry input pulse at its base so as to produce, owing to a " charge storage " effect, an extended output pulse which continues for sufficient time to gate the carry pulse on 14. Alternative gates (G2) are described and shown employing PNP type transistors and/or different electrode connections. The PNP transistors 51, 52, 53, Fig. 7, in carry propagation line 50 are connected by pulse-inverting transformers 54, 55, from which the connections to the accumulator inputs are also taken. The delays may comprise saturable inductors. In another gating arrangement (Fig. 8, not shown), NPN and PNP transistors are used alternately.