GB2446839A - Semiconductor heat transfer method - Google Patents

Semiconductor heat transfer method Download PDF

Info

Publication number
GB2446839A
GB2446839A GB0703493A GB0703493A GB2446839A GB 2446839 A GB2446839 A GB 2446839A GB 0703493 A GB0703493 A GB 0703493A GB 0703493 A GB0703493 A GB 0703493A GB 2446839 A GB2446839 A GB 2446839A
Authority
GB
United Kingdom
Prior art keywords
metal substrate
high conductivity
transfer method
insulation layer
semiconductor heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0703493A
Other versions
GB0703493D0 (en
GB2446839A8 (en
Inventor
Tai Yun
Ruey-Feng Tai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to GB0703493A priority Critical patent/GB2446839A/en
Publication of GB0703493D0 publication Critical patent/GB0703493D0/en
Publication of GB2446839A publication Critical patent/GB2446839A/en
Publication of GB2446839A8 publication Critical patent/GB2446839A8/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A heat transfer method for a semiconductor device includes treating a highly conductive metal substrate A through an electrolytic oxidation process to form an insulated oxide layer B on the surface of the substrate. A metallization layer C is formed on the oxide layer at selected locations, and an electronic device, for example an LED A1 is mounted on the metal substrate. Lead wires 111 are bonded to the electronic device and the metallization layer. Heat from the device can be effectively dissipated to the metal substrate during device operation.

Description

SEMICONDUCTOR HEAT-TRANSFER METHOD
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to the fabrication of semiconductor products and more specifically, to a semiconductor heat-transfer method.
2. Description of the Related Art:
A semiconductor heat-transfer material is known by: spray-coating or printing an insulative coating material on the surface of a well-washed metal substrate, and then baking the insulative coating material to a dry status to form an insulative layer on the metal substrate, and then making a conducting layer on the insulative layer. The insulative coating material is prepared by mixing a rock flour with a resin and a solvent. This method still has numerous drawbacks as outlined hereinafter: (1) The insulative layer is not joined to the metal substrate at a zero gap status, and the gap between the insulative layer and the metal substrate imparts a barrier to the transfer of heat energy.
(2) In order to obtain a wick structure in the insulative layer, the insulative layer must be made having a certain thickness, however the thick insulative layer imparts a barrier to the transfer of heat energy.
(3) Because the heat conductivity of the non-metal material is poor, the heat energy produced by the electronic device installed in the conducting layer cannot be quickly transferred to the metal substrate for quick dissipation.
SUMMARY OF THE INVENTION
The present invention has been accomplished under the circumstances in view. The semiconductor heat-transfer method of the present invention includes the steps of (a) treating a high conductivity metal substrate through an electrolytic oxidation process to have an oxidized insulation layer be covered on the surface of the high conductivity metal substrate, (b) covering a metal conducting layer on the oxidized insulation layer at selected locations, and (c) installing an electronic device in the high conductivity metal substrate and bonding lead wires to the electronic device and the metal conducting layer for enabling produced heat to be transferred to the metal substrate for quick dissipation during working of the electronic device. The invention has the following advantages: (1) The zero-gap connection between the oxidized insulative layer improves heat-transfer efficiency.
(2) The heat produced during the operation of the electronic device can efficiently evenly be transferred to the metal substrate for quick dissipation.
(3) The oxidized insulative layer has a thin thickness to facilitate transfer of heat energy.
(4) The oxidized insulative layer has heat and voltage resisting characteristics.
(5) The semiconductor device can be freely processed to fit the contour of the electronic device to be installed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a sectional view of a heat-transfer semiconductor device for LED type lighting fixture according to the present invention.
FIG. 2 is an elevational view of the heat-transfer semiconductor device shown in FIG. 1.
FIG. 3 is a flow chart of the present invention.
FIG. 4 is a sectional view of an alternate form of the heat-transfer semiconductor device according to the present invention.
FIG. 5 is an exploded view of still another alternate form of the heat-transfer semiconductor device according to the present invention.
FIG. 6 is an exploded view of still another alternate form of the heat-transfer semiconductor device according to the present invention.
FIG. 7 is an exploded view of still another alternate form of the heat-transfer semiconductor device according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIGS. 1 and 2, a high conductivity metal substrate A is treated through an electrolytic oxidation process to have an oxidized insulation layer B be covered on the surface thereof. The oxidized insulation layer B has high temperature and high voltage resisting characteristics. Thereafter, a metal conducting layer C is coated on the oxidized insulation layer B at selected locations by electroplating or semiconductor photolithography technology. Lead wires 111 are bonded to the metal conducting layer C and electronic device(s) Al at the high conductivity metal substrate A. During the operation of the electronic device(s) Al, produced heat is quickly transferred to the high conductivity metal substrate A for quick dissipation.
Referring to FIGS. 3 and 4, the aforesaid electrolytic oxidation process is employed to the high conductivity metal substrate A after the high conductivity metal substrate A has been well cleaned with running water. The invention includes the steps of (1) degreasing, (2) primary chemical surface grinding, (3) primary rinsing, (4) neutralization process, (5) electrolytic oxidation, (6) secondary rinsing, (7) sealing, (8) hot water dipping, (9) surface hardening, (10) secondary chemical surface grinding, (11) third rinsing, and (12) drying. If electroplating process is employed to form the metal conducting layer C on the oxidized insulation layer B at the high conductivity metal substrate A, the method of the present invention further includes the steps of (13) conducting fluid dipping, (14) electroplating, (15) final rinsing, and (16) final drying.
The aforesaid metal conducting layer C may be directly printed on the oxidized insulation layer B at the high conductivity metal substrate A at selected locations.
Referring to FIG. 5, the metal conducting layer C may be comprised of a plurality of metal conducting sheet members directly bonded to the oxidized insulation layer B at the high conductivity metal substrate A at selected locations.
Referring to FIG. 6, the aforesaid metal conducting layer C may be comprised of a plurality of metal clamping plates C3 respectively clamped on the oxidized insulation layer B at the high conductivity metal substrate A at selected locations. The metal clamping plates C3 each have a hooked portion C4 hooked in a respective hook hole A2 in the oxidized insulation layer B at the high conductivity metal substrate A. FIG. 7 shows an application example of the present invention in an integrated circuit. As illustrated, the high conductivity metal substrate A has an oxidized insulation layer B covered thereon and a conducting layer, which is comprised of a plurality of conducting lines Cl respectively covered on the oxidized insulation layer B at selected locations and respectively electrically connected to respective pins C2 at the border of the high conductivity metal substrate A, and an electronic device D is mounted in a recessed hole A3 that is formed on the high conductivity metal substrate A and cut through the oxidized insulation layer B. The electronic device D has contacts Dl respectively electrically connected to respective pins C2 at the high conductivity metal substrate A through the conducting lines Cl. During the operation of the electronic device D, produced heat is transferred from the electronic device D through the conducting lines Cl and the pins C2 to the high conductivity metal substrate A for quick dissipation.
Although particular embodiments of the invention have been described in detail for purposes of illustration, various modifications and enhancements may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.

Claims (8)

  1. What the invention claimed is: 1. A semiconductor heat-transfer method
    comprising the steps of: (a) preparing a high conductivity metal substrate and then treating said high conductivity metal substrate through an electrolytic oxidation process to have an oxidized insulation layer be covered on the surface of said high conductivity metal substrate; (b) covering a metal conducting layer on said oxidized insulation layer at selected locations; and (c) installing an electronic device in said high conductivity metal substrate and bonding lead wires to said electronic device and said metal conducting layer.
  2. 2. The semiconductor heat-transfer method as claimed in claim 1, wherein said electrolytic oxidation process includes the steps of: (1) degreasing, (2) primary chemical surface grinding, (3) primary rinsing, (4) neutralization process, (5) electrolytic oxidation, (6)secondary rinsing, (7) sealing, (8) hot water dipping, (9) surface hardening, (10) secondary chemical surface grinding, (11) third rinsing, and (12) drying.
  3. 3. The semiconductor heat-transfer method as claim in claim 1, wherein said metal conducting layer is formed on said oxidized insulation layer at selected locations by an electroplating process, which includes the steps of (a) conducting fluid dipping, (b) electroplating, (c) rinsing, and (d) drying.
  4. 4. The semiconductor heat-transfer method as claimed in claim 1, wherein said metal conducting layer is comprised of a plurality of conducting lines.
  5. 5. The semiconductor heat-transfer method as claimed in claim 1, wherein said metal conducting layer is comprised of a plurality of conducting sheet members respectively bonded to said oxidized insulation layer at selected locations.
  6. 6. The semiconductor heat-transfer method as claimed in claim 1, wherein said metal conducting layer is comprised of a plurality of metal clamps respectively clamped on said oxidized insulation layer at said high conductivity metal substrate at selected locations, said metal clamping plates C3 each having a hooked portion hooked in a respective hook hole in said oxidized insulation layer at said high conductivity metal substrate.
  7. 7. The semiconductor heat-transfer method as claimed in claim 1, wherein said metal conducting layer is directly printed on said oxidized insulation layer at said high conductivity metal substrate at selected locations.
  8. 8. The semiconductor heat-transfer method as claimed in claim 1, wherein said oxidized insulation layer is covered on the whole surface of said high conductivity metal substrate.
GB0703493A 2007-02-22 2007-02-22 Semiconductor heat transfer method Withdrawn GB2446839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0703493A GB2446839A (en) 2007-02-22 2007-02-22 Semiconductor heat transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0703493A GB2446839A (en) 2007-02-22 2007-02-22 Semiconductor heat transfer method

Publications (3)

Publication Number Publication Date
GB0703493D0 GB0703493D0 (en) 2007-04-04
GB2446839A true GB2446839A (en) 2008-08-27
GB2446839A8 GB2446839A8 (en) 2008-09-17

Family

ID=37945580

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0703493A Withdrawn GB2446839A (en) 2007-02-22 2007-02-22 Semiconductor heat transfer method

Country Status (1)

Country Link
GB (1) GB2446839A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1410119A (en) * 1972-12-20 1975-10-15 Smolko G G Thin-film microcircuits
JPS62269342A (en) * 1986-05-19 1987-11-21 Katsusato Fujiyoshi Semiconductor substrate and manufacture of semiconductor substrate
DE3629976A1 (en) * 1986-09-03 1988-04-07 Hueco Gmbh Fabrik Fuer Interna VOLTAGE REGULATOR FOR GENERATORS
EP0880310A1 (en) * 1997-05-20 1998-11-25 Sagem S.A. Process for manufacturing printed circuits on a metallic substrate
DE10042839A1 (en) * 2000-08-30 2002-04-04 Infineon Technologies Ag Electronic component with metal heatsink, comprises chips arranged on substrate with track conductors insulated from metal by layer of oxide formed upon it
DE10339692A1 (en) * 2003-08-28 2005-03-31 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Heat sink with electrically-insulating, thermally-conductive layer on which semiconductor components are mounted, comprises metallic body with surface-oxidation
US20050223551A1 (en) * 2004-04-01 2005-10-13 Ju-Liang He Method for manufacturing a high-efficiency thermal conductive base board

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1410119A (en) * 1972-12-20 1975-10-15 Smolko G G Thin-film microcircuits
JPS62269342A (en) * 1986-05-19 1987-11-21 Katsusato Fujiyoshi Semiconductor substrate and manufacture of semiconductor substrate
DE3629976A1 (en) * 1986-09-03 1988-04-07 Hueco Gmbh Fabrik Fuer Interna VOLTAGE REGULATOR FOR GENERATORS
EP0880310A1 (en) * 1997-05-20 1998-11-25 Sagem S.A. Process for manufacturing printed circuits on a metallic substrate
DE10042839A1 (en) * 2000-08-30 2002-04-04 Infineon Technologies Ag Electronic component with metal heatsink, comprises chips arranged on substrate with track conductors insulated from metal by layer of oxide formed upon it
DE10339692A1 (en) * 2003-08-28 2005-03-31 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Heat sink with electrically-insulating, thermally-conductive layer on which semiconductor components are mounted, comprises metallic body with surface-oxidation
US20050223551A1 (en) * 2004-04-01 2005-10-13 Ju-Liang He Method for manufacturing a high-efficiency thermal conductive base board

Also Published As

Publication number Publication date
GB0703493D0 (en) 2007-04-04
GB2446839A8 (en) 2008-09-17

Similar Documents

Publication Publication Date Title
JP2011139008A (en) Chip-on-board metal substrate structure having heat and electricity conduction paths separated
CN101592322A (en) The LED method for packing of high-power LED lighting fixture
TWI430717B (en) Substrate strcuture, array of semiconductor devices and semiconductor device thereof
US20070092998A1 (en) Semiconductor heat-transfer method
JP3140115U (en) Composite circuit board structure
JP2012146952A (en) Light-emitting device and formation method thereof
JP6277174B2 (en) Coating structure that can improve stress at the interface between aluminum nitride and copper coating layer
GB2446839A (en) Semiconductor heat transfer method
JP2006518553A (en) Method of generating thermal interconnect system and use thereof
CN105895536A (en) Packaging Process Of Electronic Component
JP6722568B2 (en) Method for manufacturing terminal board for mounting semiconductor device
CN105914283B (en) Heat-radiating substrate, power module and the method for preparing heat-radiating substrate
CN101247711A (en) Recirculating loop manufacturing method of high-efficiency heat conduction substrate and high-efficiency heat conduction substrate recirculating loop component
CA2579869A1 (en) Semiconductor heat-transfer method
CN103716980B (en) A kind of power module positive pole oxide-film printed base plate
TWI362774B (en) Lighting device and method for forming the same
CN103327734A (en) Integrated type high-thermal-conductivity circuit board and manufacturing method thereof
KR20180024610A (en) Ceramic board and manufacturing method thereof
TWI429115B (en) Semiconductor bearing structure
CN109728155A (en) Circuit board, ultraviolet LED curing light source and the method for preparing circuit board
NL1033519C2 (en) Semiconductor heat-transfer involves treating high conductivity metal substrate by electrolytic oxidation to provide oxidized insulation layer, covering metal conducting layer, and installing electronic device and bonding lead wires
TW201410083A (en) Circuit board and backlight module using same
JP4088394B2 (en) Insulated circuit board and semiconductor device using the same
TWM502251U (en) LED heat dissipation substrate
KR20080004061U (en) Semiconductor heat-transfer structure

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)