GB2426251A - Sn-Sb-Ge solder alloy - Google Patents
Sn-Sb-Ge solder alloy Download PDFInfo
- Publication number
- GB2426251A GB2426251A GB0601776A GB0601776A GB2426251A GB 2426251 A GB2426251 A GB 2426251A GB 0601776 A GB0601776 A GB 0601776A GB 0601776 A GB0601776 A GB 0601776A GB 2426251 A GB2426251 A GB 2426251A
- Authority
- GB
- United Kingdom
- Prior art keywords
- solder alloy
- germanium
- antimony
- tin
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C13/00—Alloys based on tin
- C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
A conductor pattern 3 on an insulative substrate 10 having a semiconductor chip 4 and a heat sink plate 8 are joined with a Sn-Sb-Ge solder alloy 9 containing 3 to 5 wt% of antimony (Sb), not more than 0.2 wt% of germanium (Ge), and the balance of tin (Sn). The semiconductor chip 4 and a conductor pattern 2 on the insulative substrate 10 may be joined with the same type of solder alloy 5. The semiconductor chip 4 and a wiring conductor 6 may be joined with the same type of solder alloy 7.
Description
Solder Alloy And A Semiconductor Device Using The Solder Alloy This
application is based on, and claims priority from, Japanese Application No. 2005-148730, filed on May 20, 2005, the contents of which are incorporated Ferein by reference.
The preent invention relates to a solder alloy free of lead and a semiconductcr device using the solder alloy, in particular to a solder alloy of tin (Sn) - antimony (Sb) system.
A solder alloy generally requires sufficient bonding performance and corrosion resislance. In power semiconductor devices for power converter application, a solder alloy is used to join the back surface of a semiconductor chip to a conductor pattern disposed on a principal surface (front surface) of an insulative substrate that is a ceramic substrate having conductor patterns on the surfaces thereof. Such a solder alloy needs high strength against thermal fatigue, because large thermal strain develops in the soldering area.
The back surface of the semiconductor chip joins to the conductor pattern on the surface of the insulative substrate in a face-bonding way, and fhermal expansion coefficients are different in a semiconductor chip and in a conductor pattern. In addition, the semiconductor chip generates heat in conducting period. Therefore, the soldering portion suffers from large thermal strain.
In power semiconductor devices installed in a power converter for power conversion in electric vehicles, the conductor pattern disposed on the other principa' surface (a back surface) of an insulative substrate is joined to a heat sink plate made of a metal. Since the soldering area is very wide, the solder alloy used for this joint must exhibit excellent wettability. Further, in the joining area between the heat sink plate and the conductor pattern on the back surface of the insulative substrate, large thermal strain develops caused by the difference in thermal expansion coefficients of the insulative substrate (a ceramic substrate) and the heat sink plate. Since the soldering area in the joint between the heat sink plate and the conductor pattern on the back surface of the insulative substrate is large, the generated strain in the soldering area is larger than the strain that develops in the joint between the semiconductor chip and the conductor pattern on the front surface of the insulative substrate as mentioned earlier.
Recently, a solder alloy that does not contain lead (Pb) is demanded in consideration of the environment. One of known such solder alloys is a fin (Sn) - antimony (Sb) alloy. A known solder alloy (See Patent Document 1, for example) contains tin (Sn) as a principal component, and antimony (Sb) not more than 3.0 wt%, silver (Ag) not more than 3.5 wt%, germanium (Ge) not more than 0.1 wf%, and further, copper not more than 1.0 wt% or nickel not more than 1.0 wt% or the both elements. Another known solder alloy (See Patent Document 2, for example) contains germanium (Ge) in the range of 0.01 to 10 wt%, antimony in the range of 5 to 30 wt%, and tin (Sn) in the range of 65 to 90 wt%.
Patent Document 1 Japanese Unexamined Patent Application Publication No. Hi 1-58066 Patent Document 2 Japanese Unexamined Patent Application Publication No.2003-94194 A fin (Sn) - antimony (Sb) alloy, having a peritectic point at 8.5 wt% of antimony (Sb) and a temperature of 245 C, is generally used with a composition containing antimony (Sb) within 8 wt%. Melting of the tin (Sn) - antimony (Sb) alloy occurs at temperatures between 232 C, the melting point of tin (Sn), and 245 C, the peritectic point. The liquid-solid coexistence region is narrow, the heat resistance is favourable, and mechanically superior performances can be obtained by increasing the antimony (Sb) content.
Large content of antimony (Sb), however, involves a problem of low wettability upon soldering the alloy. Oxidation of a solder component such as tin (Sn) involves another problem of deteriorated bonding performance.
The present invention has been made in view of the above problems, and an object of the invention is to provide a solder alloy of a tin (Sn) antimony (Sb) system exhibiting excellent wettability and satisfactory bonding performance. Another object of the invention is to provide a semiconductor device employing a solder alloy of a tin (Sn) - antimony (Sb) system exhibiting excellent wettability and satisfactory bonding performance.
To solve the problems and accomplish the objects, a solder alloy according to the invention of claim 1 contains antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and a balance of fin.
A solder alloy according to the invention of claim 2 is the solder alloy according to the invention of claim 1, wherein content of the germanium is not more than 0.2 wt%.
A semiconductor device using a solder alloy according to the invention of claim 3 comprises an insulative substrate having conductor patterns on both surfaces thereof, a semiconductor chip joined to a conductor pattern on a front surface of the insulative substrate, and a heat sink plate joined to a conductor pattern on a back surface of the insulafive substrate, wherein the conductor pattern on the back surface of the insulative substrate and the heat sink plate are soldered with a solder alloy that contains antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and the balance of tin.
A semiconductor device using a solder alloy according to the invention of claim 4 is the semiconductor device according to the invention of claim 3, wherein a back surface of the semiconductor chip and the conductor pattern on the front surface of the insulative substrate are soldered with a solder alloy that contains antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and the balance of tin.
A semiconductor device using a solder alloy according to the invention of claim 5 is the semiconductor device according to the invention of claim 3 or claim 4, wherein electrodes disposed on the surfaces of the semiconductor chip and conductors for wiring are soldered with a solder alloy that conlains antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and the balance of tin.
A semiconductor device using a solder alloy according to the invention of claim 6 is the semiconductor device according to the invention of any one of claims 3 through 5, wherein content of the germanium in the solder alloy is not more than 0.2 wt%.
A semiconductor device using a solder alloy according to the invention of claim 7 is the semiconductor device according to the invention of any one of claims 3 through 5, wherein the insulative substrate is a ceramic substrate subsianfially composed of alumina, aluminium nitride, or silicon nitride and having copper patterns on both surfaces of the substrate, and the heat sink plate is made of copper.
By adding antimony (Sb) to tin (Sn) according to the invention as claimed in claims 1 through 7, heat resistance and strength against thermal fatigue of the alloy are improved. The melting temperature rises and heat resistance of the alloy increases. Coarsening of crystal grains of tin (Sn) due to thermal stress is suppressed, improving thermal fatigue characteristic. Here, because the thermal fatigue life is very short if the content of antimony (Sb) is less than 3 wt%, the amount of additive antimony (Sb) is preferably at least 3 wf%. If the contenf of antimony (Sb) is more than 5 wt%, wettability of the solder deteriorates. Accordingly, the amount of additive antimony (Sb) is preferably not more than 5 wt%.
By adding a trace amount of germanium (Ge) to the tin (Sn) - antimony (Sb) solder alloy, a thin oxide film is formed when the solder melts, thereby suppressing oxidation of a solder component such as tin (Sn) and improving bonding performance. Here, an amount of additive germanium (Ge) is preferably at least 0.01 wt% in order to achieve sufficient effect to suppress oxidation. Germanium content more than 0.2 wt% on the other hand, the oxide film with the germanium (Ge) grows too thick, which adversely affects the bonding performance. Accordingly, the amount of additive germanium is appropriately not more than 0.2 wf%. Therefore, the germanium added in an amount in the range of 0.01 to 0.2 wt% provides satisfactory bonding performance as well as excellent thermal fatigue characteristic.
According to the invention, a tin (Sn) - antimony (Sb) solder alloy is obtained that exhibits excellent wettability and satisfactory bonding performance. According to the invention, a semiconductor device is obtained using a solder alloy of tin (Sn) - antimony (Sb) system that exhibits excellent wetlability and satisfactory bonding performance.
Some preferred embodiments of a solder alloy and a semiconductor device using the solder alloy according to the invention will be described in detail in the following with reference to an accompanying drawing.
Figure 1 is a sectional view of an example of a semiconductor device using a solder alloy according to the invention.
A solder alloy is prepared by melting the raw materials of tin (Sn), antimony (Sb), and germanium (Ge) in an electric furnace. Purity of each raw material i 99.99 % or more. Compositions of the materials are antimony 3 to 5 wt%, germanium 0.01 to 0.2 wt%, and the balance of tin (Sn), a main component.
Next, ar example of semiconductor device using the above-described solder alloy is described below. Figure 1 is a sectional view illustrating a structure of th semiconductor device. Referring to Figure 1, an insulative substrate 10 comprises a ceramic substrate 1 and conductor patterns 2 and 3 joined on both surfaces of the ceramic substrate. The ceramic substrate 1 is substantially composed of alumina, aluminium nitride, or silicon nitride. The conductor pattern 2 formed on the front surface of the ceramic substrate 1 is a metallic conductor pattern composing an electric circuit. On the back surface of the ceramic substrate 1 provided is a metallic conductor pattern 3.
The conducto'- patterns 2 and 3 are preferably formed of copper, which is inexpensive and exhibits high thermal conductivity. On the back surface of the semiconductor chip 4 provided are back surface electrodes of metallic films (not shown in the figure). The back surface electrodes are joined to the conductor pattern 2 on the front surface of the insulative substrate 10 with a solder alloy 5 having a composition as described previously.
On the front surface of the semiconductor chip 4 provided are front surface electrodes of metallic films (not shown in the figure). The front surface electrodes are joined to the wiring conductor 6 with a solder alloy 7 having a composition as described previously. The conductor pattern 3 on the back surface of the insulative substrate 10 is joined to the metallic heat sink plate 8 with a solder alloy 9 having a composition as described previously. The heat sink plate 81s a heat conductor to external cooling fins of the semiconductor package not shown in the figure. The heat sink plate 8 is preferably made of copper, which is inexpensive and exhibits high thermal conductivity.
In the joining area between the conductor pattern 3 on the back surface of the insulative substrate 10 and the heat sink plate 8, large thermal strain develops due to the difference in thermal expansion coefficient between the ceramic substrate 1 of the insulative substrate 10 and the heat sink plate 8. Copper in particular, having a large thermal expansion coefficient, exhibits a thermal expansion coefficient considerably different from the ceramic substrate 1. So, large strain is generated in the joining area between the conductor pattern 3 on the back surface of the insulative substrate 10 and the heat sink plate 8. If a heat sink plate 8 is made of a material (for example aluminium or an alloy of copper and molybdenum) having a thermal expansion coefficient smaller than copper, the generation of strain due to the difference in thermal expansion coefficient would be reduced. These materials, however, are expensive and exhibit low thermal conductivity, which deteriorates cooling characteristic of the semiconductor device.
By using a solder alloy with the above-described composition for joining the conductor pattern 3 and the heat sink plate 8, excellent cooling characteristic and satisfactory bonding performance can be achieved employing copper with low cost and high thermal conductivity. A solder material with not the same composition as of the solder alloy 5, 7, 9 may be used for joining the front surface electrodes of the semiconductor chip 4 and the wiring conductor 6, and for joining the back surface electrodes of the semiconductor chip 4 and the conductor pattern 2 on the insulative substrate 10.
Examples
Examples 1 through 4
Solder alloys of tin (Sn) - antimony (Sb) system were prepared in the compositions of antimony (Sb): 5.0 wt%, germanium (Ge): four steps of contents in the range of 0.01 to 0.2 wt%, and the balance of tin (Sn).
Germanium content was 0.01 wt% in Example 1, 0.05 wt% in Example 2, 0.1 wt% in Example 3, and 0.2 wt% in Example 4.
Examples 5 throuh 8
Solder alloys of tin (Sn) - antimony (Sb) system were prepared in the compositions of antimony (Sb): 3.0 wt%, germanium (Ge): four steps of contents in the range of 0.01 to 0.2 wt%, and the balance of tin (Sn).
Germanium content was 0.01 wt% in Example 5, 0.05 wt% in Example 6, 0.1 wt% in Example 7, and 0.2 wt% in Example 8.
ComrDarative Examrles 1 throucTh 4 Solder alloys not containing germanium (Ge) were prepared for comparison. Content of antimony (Sb) was 6.0 wt% in Comparative Example 1, 5.0 wt% in Comparative Example 2,3.0 wt% in Comparative Example 3, 2.0 wt% in Comparative Example 4; the remainder was tin (Sn) in every
Comparative Example.
On each of the thus obtained solder alloys, the weftability (wet strength) was measured using soldering flux (RMA type) by means of a meniscograph method. On each solder alloy, the rate of wetted area and the wetting angle were measured and the generation of an oxide film on the melt was observed. The thermal fatigue life was also evaluated on each solder alloy. In the evaluation of thermal fatigue life, a conjugated body (a combination of the heat sink plate 8 and the insulative substrate 10 having the conductor pattern 3 joined together with the solder alloy 9 as illustrated in Figure 1) was manufactured by joining a metallic conductor pattern on an insulative substrate to a metallic heat sink plate using each solder alloy.
To each of these conjugated bodies, loading of temperature cycles was subjected repeating the temperatures of -40 and 125 C. The length of the crack was measured after 1,000 cycles. Table 1 gives the results. In the column of "oxide film" in Table 1, the marks x and @ represent the generation of oxide film being significant and very scarce, respectively.
Table 1
Sb Ge Sn wet wetting rate of oxide crack (wt%) (wt%) strength angle wetted film length (mN) ( ) area(%) after 1,000cycles _____ ___ _____ _____ _____ _____ ___ (mm) Camp 6.0 - balance - - - - 3.0 Ex_1 ______ ______ _________ Comp 5.0 - balance 14.4 9.7 83.6 x 3.0 Ex_2 ______ ________ ________ Example 5.0 0.01 balance 15.2 3.3 100.0 - Example 5.0 0.05 balance 15.1 3.8 100.0 - 2 ______ __________ Example 5.0 0.1 balance 15.1 4.2 100.0 3 ______ _________ ________ Example 5.0 0.2 balance 15.3 4.3 100.0 - 4 ______ _________ Camp 3.() - balance 14.5 9.5 84.0 x 3.4 Ex_3 _____ ________ ________ _______ _______ Example 3.0 0.01 balance 15.2 3.1 100.0 -
______ _________ _________
Example 3.0 0.05 balance 15.2 3.4 100.0 - 6 _______ ___________ __________ Example 3.0 0.1 balance 15.3 3.5 100.0 - 7 _______ ___________ __________ _________ Example 3.0 0.2 balance 15.3 3.8 100.0 - 8 ______ ______ _________ _________ ________ _________ ______ ____________ Camp 2.0 - balance - - - - 9.1 Ex_4 ______ _____ ________ ________ Table 1 shows the following: With the increase of the added antimony (Sb), the thermal fatigue performance improves, but the increase beyond 5. 0 wt% does not provide further improvement of the thermal fatigue performance. On the other hand, antimony (Sb) content less than 3.0 wt% significantly worsens the thermal fatigue performance. Addition of 0.01 to 0.2 wt% of germanium remarkably suppresses generation of an oxide film on the molten solder and at the same time improves wettability.
The addition of germanium (Ge) is effective for both flow soldering and reflow soldering. Further, the effect of germanium is valid in both cream solder and sheet solder. The addition of germanium (Ge) in the amount more than 0.01 wt% made no significant difference in the wettability and the oxide film formation as increased from the germanium content of 0.01 wt%.
The added germanium (Ge), suppressing oxidation of tin (Sn), is effective not only in the process of soldering but also in the process of preparing a solder alloy, to provide a solder alloy with rare oxidation film and of high quality.
In a process of manufacturing powder of solder alloy for cream solder, for example, each particle of the powder is desired to have a spherical shape. To obtain the powder of spherical particles, the powder is necessarily manufactured under a condition only the surface tension works, which requires suppressing the surface oxidation to the minimum possible degree.
Therefore, germanium (Ge) is beneficially added to suppress the surface oxidation. The rate of oxidation of germanium (Ge) is stable and only a small amount of the additive holds the effect.
As described above, the addition of germanium (Ge) in a tin (Sn) antimony (Sb) alloy provides a solder alloy exhibiting excellent thermal fatigue performance, a solder alloy exhibiting heat resistance, a solder alloy exhibiting high wettability, and a solder alloy exhibiting satisfactory bonding performance. Because the alloy is free of lead (Pb), a solder alloy that does not cause environmental pollution is provided.
As described thus far, a solder alloy and a semiconductor device using the solder alloy according to the invention is beneficially applied to a variety of apparatus having soldered parts, and particularly suited to semiconductor devices for power conversion used in a power conversion apparatus installed in electric vehicles.
Claims (7)
1. A solder alloy containing antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and a balance of tin.
2. The solder alloy according to claim 1, wherein a content of the germanium is not more than 0.2 wt%.
3. A semiconductor device using a solder alloy, the device comprising: an insulative substrate having conductor patterns on both surfaces thereof, a semiconductor chip joined to the conductor pattern on a front surface of the insulative substrate, and a heat sink plate joined to the conductor pattern on a back surface of the insulative substrate, wherein the conductor pattern on the back surface of the insulative substrate and the heat sink plate are soldered with a solder alloy that contains antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and a balance of tin.
4. The semiconductor device using a solder alloy according to claim 3, wherein a back surface of the semiconductor chip and the conductor pattern on the front surface of the insulative substrate are soldered with a solder alloy that contains antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and a balance of tin.
5. The semiconductor device using a solder alloy according to claim 3 or claim 4, wherein electrodes disposed on the surface of the semiconductor chip and conductors for wiring are soldered with a solder alloy that contains antimony in a range of 3 wt% to 5 wt%, a trace amount of germanium, and a balance of tin.
6. The semiconductor device using a solder alloy according to any one of claims 3 through 5, wherein a content of the germanium in the solder alloy is not more than 0.2 wt%.
7. The semiconductor device using a solder alloy according to any one of claims 3 through 5, wherein the insulative substrate is a ceramic substrate substantially composed of alumina, aluminium nitride, or silicon nitride and having copper patterns on both surfaces of the substrate, and the heat sink plate is made of copper.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005148730A JP4635715B2 (en) | 2005-05-20 | 2005-05-20 | Solder alloy and semiconductor device using the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0601776D0 GB0601776D0 (en) | 2006-03-08 |
| GB2426251A true GB2426251A (en) | 2006-11-22 |
| GB2426251B GB2426251B (en) | 2007-10-10 |
Family
ID=36061073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0601776A Expired - Fee Related GB2426251B (en) | 2005-05-20 | 2006-01-30 | Solder alloy and a semiconductor device using the solder alloy |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20060263235A1 (en) |
| JP (1) | JP4635715B2 (en) |
| CN (3) | CN102637662B (en) |
| DE (1) | DE102006005271B4 (en) |
| GB (1) | GB2426251B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008221330A (en) * | 2007-03-16 | 2008-09-25 | Fuji Electric Holdings Co Ltd | Solder alloy |
| US20100328247A1 (en) * | 2008-02-22 | 2010-12-30 | Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.) | Touch panel sensor |
| JP2009283741A (en) * | 2008-05-23 | 2009-12-03 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| TWI541488B (en) * | 2011-08-29 | 2016-07-11 | 奇鋐科技股份有限公司 | Heat dissipation device and method of manufacturing same |
| CN102717201B (en) * | 2012-07-04 | 2015-04-22 | 深圳市斯特纳新材料有限公司 | High-strength high-temperature soldering flux with corrosion resistance |
| EP3112080A4 (en) * | 2014-02-24 | 2017-11-29 | Koki Company Limited | Lead-free solder alloy, solder material, and joined structure |
| CN108428682B (en) * | 2018-04-13 | 2020-08-18 | 江西江铃集团新能源汽车有限公司 | Power module and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62230493A (en) * | 1986-03-31 | 1987-10-09 | Taruchin Kk | Solder alloy |
| US6179935B1 (en) * | 1997-04-16 | 2001-01-30 | Fuji Electric Co., Ltd. | Solder alloys |
| JP2002321084A (en) * | 2001-04-26 | 2002-11-05 | Sumitomo Metal Mining Co Ltd | Soldering alloy for joining electronic parts |
| JP2003094194A (en) * | 2001-07-16 | 2003-04-02 | Uchihashi Estec Co Ltd | Fixing method for soldering material and member of electronic part |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3269745B2 (en) * | 1995-01-17 | 2002-04-02 | 株式会社日立製作所 | Modular semiconductor device |
| JPH09330941A (en) * | 1996-06-13 | 1997-12-22 | Toshiba Corp | High heat-conduction paste solder and semiconductor device |
| JP3226213B2 (en) * | 1996-10-17 | 2001-11-05 | 松下電器産業株式会社 | Solder material and electronic component using the same |
| US6033488A (en) * | 1996-11-05 | 2000-03-07 | Samsung Electronics Co., Ltd. | Solder alloy |
| KR19980068127A (en) * | 1997-02-15 | 1998-10-15 | 김광호 | Lead-Free Alloys for Soldering |
| JP3353662B2 (en) * | 1997-08-07 | 2002-12-03 | 富士電機株式会社 | Solder alloy |
| CA2340393A1 (en) * | 1999-06-11 | 2000-12-21 | Katsuaki Suganuma | Lead-free solder |
| JP2002232022A (en) * | 2001-01-31 | 2002-08-16 | Aisin Seiki Co Ltd | Thermoelectric module and its manufacturing method |
| TW592872B (en) * | 2001-06-28 | 2004-06-21 | Senju Metal Industry Co | Lead-free solder alloy |
| US20030178719A1 (en) * | 2002-03-22 | 2003-09-25 | Combs Edward G. | Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package |
| JP2004017093A (en) * | 2002-06-17 | 2004-01-22 | Toshiba Corp | Lead-free solder alloy and lead-free solder paste using the same |
| CN1230567C (en) * | 2003-07-02 | 2005-12-07 | 中国科学院金属研究所 | Industrial pure tin with resistance to liquid surface oxidizing and application |
-
2005
- 2005-05-20 JP JP2005148730A patent/JP4635715B2/en active Active
-
2006
- 2006-01-30 GB GB0601776A patent/GB2426251B/en not_active Expired - Fee Related
- 2006-02-02 US US11/345,516 patent/US20060263235A1/en not_active Abandoned
- 2006-02-06 DE DE102006005271A patent/DE102006005271B4/en active Active
- 2006-02-28 CN CN201210102888.0A patent/CN102637662B/en active Active
- 2006-02-28 CN CN2006100515427A patent/CN1864909B/en active Active
- 2006-02-28 CN CN2010102407673A patent/CN101905388B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62230493A (en) * | 1986-03-31 | 1987-10-09 | Taruchin Kk | Solder alloy |
| US6179935B1 (en) * | 1997-04-16 | 2001-01-30 | Fuji Electric Co., Ltd. | Solder alloys |
| JP2002321084A (en) * | 2001-04-26 | 2002-11-05 | Sumitomo Metal Mining Co Ltd | Soldering alloy for joining electronic parts |
| JP2003094194A (en) * | 2001-07-16 | 2003-04-02 | Uchihashi Estec Co Ltd | Fixing method for soldering material and member of electronic part |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102006005271B4 (en) | 2012-12-06 |
| GB0601776D0 (en) | 2006-03-08 |
| JP4635715B2 (en) | 2011-02-23 |
| CN1864909B (en) | 2012-05-30 |
| US20060263235A1 (en) | 2006-11-23 |
| CN102637662A (en) | 2012-08-15 |
| CN101905388A (en) | 2010-12-08 |
| DE102006005271A1 (en) | 2006-11-23 |
| CN1864909A (en) | 2006-11-22 |
| GB2426251B (en) | 2007-10-10 |
| CN102637662B (en) | 2014-09-24 |
| JP2006320955A (en) | 2006-11-30 |
| CN101905388B (en) | 2012-05-30 |
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