GB2390742B - Copper silicide passivation for improved reliability - Google Patents
Copper silicide passivation for improved reliabilityInfo
- Publication number
- GB2390742B GB2390742B GB0309476A GB0309476A GB2390742B GB 2390742 B GB2390742 B GB 2390742B GB 0309476 A GB0309476 A GB 0309476A GB 0309476 A GB0309476 A GB 0309476A GB 2390742 B GB2390742 B GB 2390742B
- Authority
- GB
- United Kingdom
- Prior art keywords
- improved reliability
- copper silicide
- passivation
- silicide passivation
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13378202A | 2002-04-26 | 2002-04-26 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0309476D0 GB0309476D0 (en) | 2003-06-04 |
GB2390742A GB2390742A (en) | 2004-01-14 |
GB2390742B true GB2390742B (en) | 2006-07-19 |
Family
ID=22460275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0309476A Expired - Fee Related GB2390742B (en) | 2002-04-26 | 2003-04-25 | Copper silicide passivation for improved reliability |
Country Status (4)
Country | Link |
---|---|
JP (2) | JP2003347302A (en) |
KR (1) | KR101005434B1 (en) |
GB (1) | GB2390742B (en) |
TW (1) | TWI278963B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8344509B2 (en) | 2009-01-19 | 2013-01-01 | Kabushiki Kaisha Toshiba | Method for fabricating semiconductor device and semiconductor device |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101028811B1 (en) * | 2003-12-29 | 2011-04-12 | 매그나칩 반도체 유한회사 | Method of forming a dual damascene pattern in a semiconductor device |
US7229911B2 (en) * | 2004-04-19 | 2007-06-12 | Applied Materials, Inc. | Adhesion improvement for low k dielectrics to conductive materials |
US20050233555A1 (en) * | 2004-04-19 | 2005-10-20 | Nagarajan Rajagopalan | Adhesion improvement for low k dielectrics to conductive materials |
JP2007109736A (en) * | 2005-10-11 | 2007-04-26 | Nec Electronics Corp | Semiconductor device and method of manufacturing same |
US8884441B2 (en) | 2013-02-18 | 2014-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process of ultra thick trench etch with multi-slope profile |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04192527A (en) * | 1990-11-27 | 1992-07-10 | Toshiba Corp | Semiconductor device |
US5447887A (en) * | 1994-04-01 | 1995-09-05 | Motorola, Inc. | Method for capping copper in semiconductor devices |
JPH1187499A (en) * | 1997-09-04 | 1999-03-30 | Sony Corp | Semiconductor device and its manufacture |
US6303505B1 (en) * | 1998-07-09 | 2001-10-16 | Advanced Micro Devices, Inc. | Copper interconnect with improved electromigration resistance |
US20020155702A1 (en) * | 2001-02-21 | 2002-10-24 | Nec Corporation | Manufacturing method of semiconductor device |
US6515367B1 (en) * | 2000-09-30 | 2003-02-04 | Advanced Micro Devices, Inc. | Sub-cap and method of manufacture therefor in integrated circuit capping layers |
EP1282168A2 (en) * | 2001-08-01 | 2003-02-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and its fabrication method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01103840A (en) * | 1987-10-16 | 1989-04-20 | Sanyo Electric Co Ltd | Dry etching |
JPH11191556A (en) * | 1997-12-26 | 1999-07-13 | Sony Corp | Manufacture of semiconductor device and forming method of copper or copper alloy pattern |
JP2000058544A (en) * | 1998-08-04 | 2000-02-25 | Matsushita Electron Corp | Semiconductor device and manufacture of the same |
JP2000195820A (en) * | 1998-12-25 | 2000-07-14 | Sony Corp | Forming method of metal nitride film and electronic device using the same |
JP2001185549A (en) * | 1999-12-24 | 2001-07-06 | Toshiba Corp | Method for manufacturing semiconductor device |
JP3643540B2 (en) * | 2000-02-21 | 2005-04-27 | 株式会社日立製作所 | Plasma processing equipment |
-
2003
- 2003-04-25 KR KR1020030026307A patent/KR101005434B1/en active IP Right Grant
- 2003-04-25 JP JP2003120807A patent/JP2003347302A/en active Pending
- 2003-04-25 GB GB0309476A patent/GB2390742B/en not_active Expired - Fee Related
- 2003-04-25 TW TW092109732A patent/TWI278963B/en not_active IP Right Cessation
-
2010
- 2010-06-17 JP JP2010137862A patent/JP2010232676A/en not_active Withdrawn
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04192527A (en) * | 1990-11-27 | 1992-07-10 | Toshiba Corp | Semiconductor device |
US5447887A (en) * | 1994-04-01 | 1995-09-05 | Motorola, Inc. | Method for capping copper in semiconductor devices |
JPH1187499A (en) * | 1997-09-04 | 1999-03-30 | Sony Corp | Semiconductor device and its manufacture |
US6303505B1 (en) * | 1998-07-09 | 2001-10-16 | Advanced Micro Devices, Inc. | Copper interconnect with improved electromigration resistance |
US6515367B1 (en) * | 2000-09-30 | 2003-02-04 | Advanced Micro Devices, Inc. | Sub-cap and method of manufacture therefor in integrated circuit capping layers |
US20020155702A1 (en) * | 2001-02-21 | 2002-10-24 | Nec Corporation | Manufacturing method of semiconductor device |
EP1282168A2 (en) * | 2001-08-01 | 2003-02-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and its fabrication method |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8344509B2 (en) | 2009-01-19 | 2013-01-01 | Kabushiki Kaisha Toshiba | Method for fabricating semiconductor device and semiconductor device |
US8536706B2 (en) | 2009-01-19 | 2013-09-17 | Kabushiki Kaisha Toshiba | Method for fabricating semiconductor device and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TW200408055A (en) | 2004-05-16 |
JP2010232676A (en) | 2010-10-14 |
GB0309476D0 (en) | 2003-06-04 |
GB2390742A (en) | 2004-01-14 |
KR20030084761A (en) | 2003-11-01 |
KR101005434B1 (en) | 2011-01-05 |
JP2003347302A (en) | 2003-12-05 |
TWI278963B (en) | 2007-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1483804A4 (en) | Push-in wire connector | |
AU2003249187A8 (en) | On chip network | |
AU2003226646A8 (en) | Semiconductor device | |
AU2003282394A8 (en) | Chip antenna | |
GB0222649D0 (en) | Passivation layer | |
SG121883A1 (en) | Integration film scheme for copper/low-k interconnect | |
AU2003263737A8 (en) | Pre-aligner | |
TW547858U (en) | Retention mechanism for electrical connector | |
EP1538675A4 (en) | Semiconductor device | |
SG114619A1 (en) | Dielectric having a barrier effect against copper diffusion | |
GB2390742B (en) | Copper silicide passivation for improved reliability | |
SG121927A1 (en) | Advanced copper damascene structure | |
EP1482560A4 (en) | Semiconductor device | |
EP1476609A4 (en) | Trip lever assembly | |
HK1064796A1 (en) | Copper alloy conductor | |
GB0222045D0 (en) | Terminal location | |
AU2002250505A1 (en) | Beol process for cu metallizations free from al-wirebond pads | |
GB2385215B (en) | Electrical spurs | |
AU2003241087A8 (en) | Device for transferring wire pieces | |
TW568355U (en) | Improved leadframe structure for integrated circuit | |
GB0304668D0 (en) | Circuit breaker | |
GB2396357B (en) | Copper phthalocyanine compounds | |
GB0229981D0 (en) | Copper phthalocyanine compounds | |
TW543608U (en) | Protective pin for conductive terminal | |
GB0222602D0 (en) | Tan shirt |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20160425 |