GB2221777A

GB2221777A - Data processor

Info

Publication number: GB2221777A
Application number: GB8916773A
Authority: GB
Inventors: Takahiko Yamamuro
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1988-07-22
Filing date: 1989-07-21
Publication date: 1990-02-14
Also published as: GB8916773D0; JPH0233645A; DE3923759A1; DE3923759C2

Description

1 1 1 DATA PROCESSOR 2221777 The present invention relates to a data

processor f or use in a computer or the like having a DMA controller.

Fig. 1 of the accompanying drawings is a block diagram of a conventional personal computer, wherein numeral 1 designates a computer body. The computer body 1 consists of a main memory 11, a central processing unit (CPU) 12 for controlling data transfer between the main memory 11 and an input-output unit, and a DMIA controller 13 for controlling the data transfer between the main"' memory 11 and the input-output unit instead of the CPU 12 in order to reduce load on CPU 12 or to obtain a high-speed transfer of data. Each of these elements is connected to an internal bus 14 having both a data bus and an address bus, respectively, throligh which the data is to be transferred to each element. The internal bus 14 is further connected to a man-machine interface 2 such as a keyboard 21, and a display monitor 22 and the like, an image scanner 3 for reading an image, and a display device 4 f or diplaying the image being read by the image scanner 3, respectively, thereby, the data transfer to or from the main memory 11 is to be controlled by the CPU 12 or the DMA controller 13.

Operation of the data transfer will now be described below. In the computer body 1, data is transferred to or from the main memory 11 according to the control -of the CPU 12 while an operator operates the man-machine interface 2 such as the keyboard 21 and the display monitor 22 or the like. When the image being read by the image scanner 3 is to be displayed on the display 2 device 4, or the displayed image on the display device 4 is to be stored in the main memory 11, the image data being read by the image scanner 3 is transferred to the display device 4 so as to be displayed thereon through the internal bus 14 and then the displayed image data is transferred fron'the display device 4 to the main memory 11 through the internal bus 14 so as to be stored according to the control of the DMA controller 13 instead of the CPU 12 by putting the CPU 12 in a HOLD status.

A personal computer having such a construction as described above has a disadvantage in that its operation can not' be effectively performed since if a large quantity of data is to be transferred under the control of the DHA controller, the CPU must be put in a HOLD status while the data is being transferred, and as a result the data being inputted from the man-machine interface such as the keyboard, and the display monitor and the like during that time becomes invalid.

A first object of the present invention is to provide a data processor capable of data input by an operator even while data is being transferred under the control of a DMA controller. A second object of the invention is to provide a data processor separately provided with a first bus for transferring data under the control of a DMA controller and a second bus for transferring data under the control of a CPU. A third object of the invention is to provide a data processor wherein two buses separately provided therein are connected to each other through a buffer. A fourth object of the invention is to provide a data processor capable of transferring data in one bus to the other bus through a buffer.

3 Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Fig. 1 is a block diagram of a conventional personal computer; and Fig. 2 is a block diagram of an embodiment of a personal computer according to the present invention.

Fig. 2 is a block diagram of an embodiment of a personal computer of the present invention, in which numeral 1 designates a computer body. The computer body 1 consists of a main memory 11, a CPU 12 for controlling data transfer between a main memory 11 and an input-output unit, and a DMA controller 13 for reducing load on the CPU 12 or obtaining a high- speed transfer of data and for controlling data transfer instead of the CPU 12,. between the main memory 11 and the input-output unit. As regards an internal bus thereof, a CPU bus and a DNA bus, separately provided with both an address bus and a data bus respectively, are provided for transferring data each under control of the CPU 12 or the DMA controller 13, and are connected to each other through a buffer 17. The CPU bus 15 is for connection to a man-machine interface 2 such as a keyboard 21 and a display monitor 22 and the like, and the DMA bus 16 is connected to the main memory 11. The DMA bus 16 is also connected to both an image scanner 3 for reading an image and a display device 4 for displaying the image being read by the image scanner 3.

operation of the data transfer will now be described below. When the image being read by the image scanner 3 is to be displayed on the display device 4, or the displayed image data is 4 to be stored in the main memory 11, the read image data is transferred to the display device 4 through the DMA bus 16 or the displayed image data is transferred from the display device 4 through the DNA bus 16 to the main memory 11 under the control of the DMA controller 13. In other words, since the CPU bus 15 is not used when transferring the image data, it is not necessary to put the CPU 12 in a HOLD status, and even while data is being transferred between the main memory and the other input- output unit by use of the DMA bus under the control of the DMA controller 13, an operator can input data by operating the keyboard 21 or the display monitor 22.

on the other hand, when the DMA bus 16 is not used, it is possible to access the main memory 11 and the other input-output unit connected to the DMA bus 16, by transferring data from the CPU bus 15 through the buffer 17 to the DMA bus 16.

If the DMA controller 13 uses the CPU bus 15, data will be transferred from the DMA bus 16 through the buffer 17 to the CPU bus 15 by putting the CPU 12 in a HOLD status.

Although in this embodiment, a keyboard and a display monitor are described as a man-machine interface, there may be an equal effect by connecting a mouse, every kind of interface board for a network and the like thereto.

In addition, although in this embodiment an image scanner and a display device are described as being connected to the DMA bus, there may be an equal effect by connecting a printer, a speech synthesis board, an extended memory and the like thereto.

As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiment is therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within the meets and bounds of the claims, or equivalence of such meets and bounds thereof are therefore intended to be embraced by the claims.

11 1 6

Claims

CLAIMS a data processor comprising: main memory for storing data, central

processing unit being able to control access to said main memory, DNA controller being able to control direct access to said main memory without said central processing unit control, first bus for transferring data to or from said main memory from or to at least one external peripheral connected WittemeL= 94sr-age 4.5-# thereto under control of said DMA controller, second bus for transferring data to or from at least one external peripheral connected thereto under said central processing unit control, and buffer for connecting said first and second bus.
2. A data processor as set forth in claim 1 wherein said main memory is accessible by said central processing unit through said buffer while said first bus not busy.
3. A data processor as set forth in claims 1 or 2 wherein said external peripherals connected to said first bus are accessible by said central processing unit through said buffer while said first bus not busy.
4. A data processor as set forth in any preceding claim 1 wherein said DMA controller is able to transfer data by means of C 1 1 7 said second bus by outputting a hold command to said central processing unit.
5. A data processor as set f orth in any preceding claim wherein said data is image data.
6. A data processor as set forth in any preceding claim.wherein said at least one external peripheral connected to said first bus comprises a display device.
7. A data processor as set forth in any preceding claim wherein said at least one external peripheral connected to said first bus is an image scanner.
8. A data processor as set f orth in any preceding claim wherein said at least one external peripheral connected to said first bus is a printer.
9. A data processor as set forth in any preceding claim wherein said at least one external peripheral connected to said first bus is a speech synthesis board.
10. A data processor as set forth in any preceding claim wherein said at least one external peripheral connected to said first bus is an extended memory.
11. A data processor as set forth in any preceding claim 1 wherein said at least one external peripheral connected to said 1 8 second bus is a keyboard.
12. A data processor as set forth in any preceding claim wherein said at least one external peripheral connected to said second bus is a display monitor.

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13. A data processor as set forth in any preceding claim wherein said at least one external peripheral connected to said second bus is a mouse.

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14. A data processor as set forth in any preceding claim wherein said at least one external peripheral connected to said second bus is an interface board for a network.
15. A data processor substantially as herein described with reference to Figure 2 of the accompanying drawings.

1 Published 1990 athe PatentOtice, State House, 86171 High Holborn, London WC1R 4TP. Further copies maybe obtainedfromThe Patentomce. Sales Branch. St Mary Cray. Orpingtor. Weiot BR5 3RD. Printed by Multiplex techniques ltd. St Mary Cray, Kent. Con. 1187