GB2150779A

GB2150779A - Leakage current compensation method and structure for integrated circuits

Info

Publication number: GB2150779A
Application number: GB08417443A
Authority: GB
Inventors: Robert Mark Stitt; Rodney Thomas Burt
Original assignee: Burr Brown Corp
Current assignee: Texas Instruments Tucson Corp
Priority date: 1983-12-05
Filing date: 1984-07-09
Publication date: 1985-07-03
Also published as: FR2556133A1; GB2150779B; GB8417443D0; JPH0556660B2; DE3444376A1; JPS60124861A

Abstract

A multi-collector transistor Q1 in a tub region T1 having one collector (1) coupled to its base, a second collector (2) coupled to a first PN junction-isolated tub region T2 and a third collector (3) coupled to a second PN junction-isolated tub region T3 permits effective cancellation of the substrate leakage of the tub regions T2, T3 which may contain one or more active semiconductor devices Q2, Q3. Tub T1 has a leakage current from collector 1 which is mirrored at the other collectors and fed to the other tubs to provide compensation for leakage from them. <IMAGE>

Description

SPECIFICATION Leakage Current Compensation Method and Structure for Integrated Circuits This invention relates generally to leakage current compensation in integrated circuits, and, more specifically, to a method and structure to permit leakage current compensation of a plurality of semiconductor devices individually isolated in a PN junction-isolated integrated circuit.

Most bipolar monolithic integrated circuits that are presently being manufactured employ PN junction isolation to electrically isolate or separate various semiconductor devices used to provide each integrated circuit. Typically, a common substrate region is reverse-biased with respect to the semi-conductor regions or tubs in which the component semiconductor devices are fabricated.

The semiconductor devices may include vertical bipolar transistors, lateral bipolar transistors, diodes, and junction field-effect transistors (JFETs).

However, a problem associated with manufacturing integrated circuit products is that a leakage current flows into each tub across the reverse-biased isolation PN junction. At room temperature this leakage is usually small and does not adversely impact circuit operation. However, at elevated temperatures, or in the presence of optical or nuclear radiation, the leakage may become sufficient to degrade or destroy circuit operation.

Even though an integrated circuit may function properly at room temperature, it may fail at an elevated temperature because of an increase in the tube to substrate leakage current. Thus, since integrated circuits are usually required to operate over a fairly large or wide range of temperatures, including room temperature, it is imperative to be able to control or compensate for an undesired increase in leakage current because of higher temperature or other factors. Substrate leakage current is sensitive to such factors as tub area and voltage besides temperature and radiation. The problem is particularly acute in the case of circuits operating at very low current levels, such as highimpedance operational amplifiers.

In the past, additional devices have been used to compensate for the effects of parasitic leakage in PN junction isolated bipolar integrated circuits. In general, these compensation techniques have required at least one additional device for each device to be compensated. This resulted in increased complexity and substantially larger area requirements for the integrated circuit. Thus, a need has existed for a leakage current compensation technique which reduces circuit complexity and area, and which allows compensation of multiple devices in an integrated circuit, particularly where the multiple devices employ low current circuitry.

Since, for example, there is a parasitic leakage to the underlying semiconductor substrate from either the collector of a vertical NPN transistor device or the base of a lateral PNP transistor device, there was a need to provide a leakage current compensation technique for these devices especially when the collector of the vertical NPN transistor device or the base of the lateral PNP transistor device were operating at low current levels which would usually make these devices degrade from a performance viewpoint because of substrate leakage.

In accordance with one embodiment of this invention, it is an object thereof to provide an improved structure and method for substrate leakage compensation in an integrated circuit.

It is another object of this invention to provide leakage current compensation for a plurality of mutually-isolated semiconductor devices by means of a single compensation device.

It is still another object of this invention to provide leakage current compensation for mutually-isolated devices having disparate tub areas by means of a single compensation device.

It is yet another object of this invention to provide substrate leakage current compensation for a plurality of devices of different types by means of a single compensation device.

It is still another object of this invention to provide substrate leakage current compensation for an integrated circuit device by using a smaller compensating device.

In accordance with one embodiment of this invention, a method is provided for compensating tub-to-substrate leakage current in a PN junction isolated integrated circuit having at least one tub region in contact with a substrate region comprising providing a multi-conductor transistor device electrically coupling one collector of the multicollector transistor to the tub region to be compensated, and electrically coupling another collector of the multi-collector transistor to the base of the multi-collector transistor. Substrate leakage current compensation is provided by the multicollector transistor having collectors which may be of different sizes, one of which collectors is coupled to the base of the multi-collector device and another of which collectors is coupled to the tub region or device to be compensated.The multi-collector transistor may be implemented in a tub which is smaller than the tub of the device to be compensated.

In accordance with another embodiment of this invention, a PN junction isolated integrated circuit structure is provided which comprises first and second PN junction-isolated tub regions in contact with a substrate region; a transistor having at least a first collector and a second collector, and a base located in the first tub region; means for electrically coupling the first collector to the base of the transistor; and means for electrically coupling the second collector to the second tub region to permit compensation for the substrate-to-tub leakage in the second tub region. Substrate leakage current compensation is provided by the multi-collector transistor having collectors of different sizes and having one collector coupled to the base of the multi-collector device and other collectors coupled to the plurality of tub regions or devices to be compensated.The tub area of the multi-collector compensating device is desirably less than the total area of devices to be compensated. The compensated devices may also be operated at different voltage levels.

The foregoing and other objects, features and advantages of the invention will be apparent from the following, more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawing:~ Figure 1 is a schematic representation of a substrate leakage compensation circuit arrangement for a current mirror; Figure 2 is a schematic representation of a substrate leakage compensation circuit arrangement for a variety of integrated circuit devices which uses a single multi-collector transistor; Figure 3 is illustrative of a multi-collector compensation device for an operational amplifier having devices with different collector voltage levels.

Referring now to Figure 1, there is schematically shown a current mirror of conventional construction comprising PNP bipolar transistors Q.,Q2 and 03.

Input current 1, establishes a voltage across the base-emitter junction of the transistor 02. When the transistors Q, and Q2 are matched, the collector current flowing out of the transistor Q, must be the same as the collector current flowing out of the transistor 03, i.e. Io=l1. The transistor Q3 buffers the Qa~Q2 electrically connected base line so that base current errors are not added to the input current Ii.

In a typical low-current application It may be 500 nA.

Assuming a Q,~ Q2 beta of 50, 10 nA will flow out of the bases of each of the transistors Q1 and Q2. This current will be supplied by the transistor Q3 to maintain the match between 1o and I1,thus permitting the current mirror to operate properly.

The transistors Q, and Q2 may be implemented in a common tub T,2 located in an integrated circuit structure which has a leakage 1S,2 to the reversebiased substrate that is in physical contact with the common tub T,2 (the substrate is not specifically shown or designated, but can be considered to be the region, for example, under the tub T,2). As the temperature of the tub region T,2 increases, the leakage current 1s12 will increase.At some temperature, the leakage current 1S,2 will exceed the nominal 20 nA base bias current of the transistors Q, and 02. Above this temperature, the transistor Q3 will be turned off and the transistor Q2 will saturate, causing lo to exceed I, so that the mirror action fails.

It will now be explained how PNP transistor Q4 compensates for the substrate leakage current Ski 2 The transistor Q, is a dual-collector lateral PNP transistor fabricated in its own PN junction isolated tub T4 which is also in contact with a substrate region (not shown specifically, but can be considered to bethe region, for example, underthe tub T4).If the tub T4 has the same area as the tub T,2, the same amount of substrate leakage current that flows from the combined base region of the transistors Q, and Q2 also flows from the base region of the transistor Q4, i.e. 154 (which is the substrate leakage current that flows from the base region of the transistor Q4)=lS,2. If the beta of the transistor Q, is large, and one of its collectors is connected to its base, then the substrate leakage current 154 will flow almost entirely from that collector.The second collector of the transistor Q, is used to mirror the current 154 into the common base region of the transistors Q, and Q2, in the case where the two collectors of the transistor Q4 are of equal size. Since the current in any collector of a multi-collector device will be determined by its relative size (or split ratio), the compensation could be alternatively provided, for example, by making the tub T4 (and hence the leakage current IS4) one-half the size of the hub T,2 and making the second collector of the transistor Q4 twice the size of the collector connected to the base of the transistor 04. Thus, in general, the area required by the compensating device (the transistor 4) could be less than that of the device or devices to be compensated.A positive voltage source V+ is connected in common to each of the emitter regions of the transistors Or, 02 and Q4 while a negative voltage source is connected to the collector of the transistor 02.

Referring now to Figure 2, there are several devices Q2~Q4 of different types to be compensated for substrate leakage. In this embodiment, for example Q2 may be a vertical NPN bipolar transistor, Q3 a lateral PNP bipolar transistor, and Q4 a P-channel JFET. These devices are constructed in separate tubs T2-T4 which may in general have different areas and hence different substrate leakage currents. T5 is a tub which may contain another type of an element, for example, a resistor whose substrate leakage is critical. Q,, in Figure 2, is a multi-collector lateral PNP transistor having one more collector than the number of tubs to be compensated. The substrate leakage of the tub T, is coupled to the transistor Q, by a connection from the base of the transistor Q, to collector 1.The current which flows in each of the other collectors 2-5 of the transistor Q, is in the ratio of the split collector ratio of the respective collector to that of collector 1. The respective ratios are selected to be the same as the ratio of the tub area to be compensated to the area of tub T,. Thus, the area of the tub T, may be less than the sum of the areas of the tubs T2-T5, and is potentially less than any one of them. The lower limit on the area of the tub T1 is set by tolerances and by the necessity to provide a tub large enough to accommodate the required configuration for the transistor Q, with the desired collector contacts or conductor leads. Accordingly, the respective conductor lead providing an electrical coupling or contact between the collector of the transistor device Q, and the desired tub region(s) T2, etc., serves to provide or permit each coupled device in the desired tub region(s) to be compensated for substrate leakage currents.

Yet another embodiment of the instant invention is illustrated in Figure 3, which is a schematic representation of a portion of an operational amplifier configured for integrated circuit implementation. In this circuit PNP transistors Q,, Q2, and Q4 operate at one voltage level and PNP transistors 0,, 0, and Q8 operate at a different voltage level. Multi-collector transistor Q40 has a first collector coupled to its base, and also has two additional collectors one of which is coupled to the common bases of the transistors Qr,Q2 and Q4 and the second of which is coupled to the common bases of the transistors 0,,0, and 0,to compensate for the substrate leakage current.By providing a separate collector for each operating voltage level, numerous voltage levels (and the device connected or coupled to each voltage level) may be compensated. The collector split levels are determined by the tub ratios as described hereinbefore; it may additionally be advantageous to adjust the tub area ratios to compensateforthe slow variation in substrate leakage current with operating voltage level. A resistor R1 is connected between a V+ voltage supply source and the collector of a NPN transistor Q, which has its emitter connected to the emitter of NPN transistor Q10. The collector of the transistor 0,, its connected to resistor R2 which is (like the resistor R1) connected to the V+ voltage supply source.A 240 pA current source is connected to the emitter of the transistors 0, and Qro and to a V- voltage supply source. The input to the circuit (of Figure 3) is connected to both the base of the transistor Q10 and collector of 0, and to both the base of the transistor 0, and to the collector of the transistor 0,. A PNP transistor Q3 has its emitter connected to the common base connection of the transistors Q,, Q4 and Q2, its base connected to the collector of the transistor Q2 and to the emitter of the transistor 0,, and its collector connected to the collector of a PNP transistor 07.

The emitter of the transistor Q, is connected to the common base connection of the transistors 0,, 0, and 06, while the base of the transistor 07 is connected to the collector of the transistor Q6 and to the collector of a NPN transistor Q". The collector of the transistor Q, is also connected to the V- voltage supply source. The base of the transistor Q,, is connected to the 240 pA current source and the emitter of the transistor Q,, is connected to the base of a NPN transistor 012. The collector of the transistor 0,, is connected to the V+ voltage supply source while the emitter of the transistor 012 is connected to a 120 pA current source which is also connected to the V- voltage supply source.

While the invention has been partially shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the spirit and scope of the invention.

Claims

1. Amethod for compensating tub-to-substrate leakage current in a PN junction isolated integrated circuit having at least one tub region in contact with a substrate region comprising the steps of: providing a multi-collector transistor device; electrically coupling one collector of said multicollector transistor to the tub region to be compensated; and electrically coupling another collector of said multi-collector transistor to the base of said multi-collector transistor.

2. A method for compensating the substrate-totub leakage current of a first PN junction isolated integrated circuit tub region in an integrated circuit structure, comprising the steps of: providing a second PN junction isolated tub region in said integrated circuit structure; forming a transistor having a base and at least a first collector and a second collector in said second tub region; electrically coupling said first collector of said transistor to said base of said transistor; and electrically coupling said second collector of said transistor to said first tub region to permit compensation for the substrate-to-tub leakage in said first tub region.

3. The method of claim 2, where said first tub region has a larger area than said second tub region.

4. The method of claim 2, further including providing more than two collectors for said transistor in order to permit an electrical connection from said transistor to compensate each one of a plurality of tub regions in said integrated circuit structure.

5. The method of claim 2, further including making the split collector ratio of said first and said second collectors substantially the same as the ratio of the areas of said first and said second tub regions.

6. A PN junction isolated integrated circuit structure comprising first and second PN junction isolated tub regions in contact with a substrate region; a transistor having at least a first collector and a second collector and a base located in said first tub region; means for electrically coupling said first collector to said base of said transistor; and means for electrically coupling said second collector to said second tub region to permit compensation for the substrate-to-tub leakage in said second tub region.

7. The integrated circuit structure of claim 6, wherein the area of said second tub region is larger than the area of said first tub region.

8. The integrated circuit structure of claim 6, further including at least a third collector for said transistor and a third PN junction isolated tub region, and electrical means for coupling said third collector to said third tub region to permit compensation for the substrate-to-tub leakage in said third tub region.

9. The integrated circuit structure of claim 8, wherein the area of said first tub region is less than the sum of the areas of said second tub region and said third tub region.

10. The integrated circuit structure of claim 6, wherein the split collector ratio of said first collector and said second collector is substantially the same as the area ratio of said first tub region and said second tub region.

11. The integrated circuit structure of claim 8, further including first conductive means for electrically coupling said second tub region to a first voltage level, and second conductive means for electrically coupling said third tub region to a second voltage level different from said first voltage level.

12. In an operational amplifier, a PN junctionisolated integrated circuit structure comprising: first and second PN junction-isolated tub regions in contact with a substrate region; a transistor having at least a first collector and a second collector and a base located in said first tus region; means for electrically coupling said first collector to said base of said transistor; and means for electrically coupling said second collector to said second tub region to permit compensation for the substrate-totub leakage in said second tub region.

13. A method for compensating tub-to-substrate leakage current in a PN junction-isolated integrated circuit substantially as hereinbefore described with reference to Figure 1, 2 or 3 of the accompanying drawings.

14. A method for compensating the substrate-totub leakage current of a first PN junction-isolated integrated circuit tub region in an integrated circuit structure substantially as hereinbefore described with reference to Figure 1, 2 or 3 of the accompanying drawings.

15. APN junction-isolated integrated circuit structure substantially as hereinbefore described with reference to Figure 1, 2 or 3 of the accompanying drawings.

16. An operational amplifier comprising a PN junction-isolated integrated circuit substantially as hereinbefore described with reference to Figure 3 of the accompanying drawings.