GB2125973A

GB2125973A - Self-test method and apparatus

Info

Publication number: GB2125973A
Application number: GB08319574A
Authority: GB
Inventors: Keith Wayne Parker
Original assignee: Tektronix Inc
Current assignee: Tektronix Inc
Priority date: 1982-08-23
Filing date: 1983-07-20
Publication date: 1984-03-14
Also published as: CA1198775A; GB8319574D0; NL8302920A; DE3330270A1; JPS5965270A; FR2532056A1

Abstract

A self-test system is disclosed wherein a microprocessor controlled system 10 under test, including a ROM 10c and a microprocessor 10d, may generate a raise-to-maximum signal. In response to this raise-to- maximum signal, a power supply generates a supply voltage having a magnitude equivalent to the maximum rated voltage of the power supply. A self-test program encoded in the ROM 10c directs the microprocessor 10d to interrogate the components of the system under test 10a when energized by the maximum rated supply voltage. The microprocessor controlled system under test 10 then generates a lower-to-minimum signal. In response to this lower-to-minimum signal, the power supply generates a supply voltage having a magnitude equivalent to the minimum rated voltage of the power supply. The microprocessor 10d, under the instructions of the self-test program, interrogates the components of the system under test 10a when energized by the minimum rated supply voltage. When the raise-to- maximum signal and the lower-to- minimum signals are not generated, the power supply develops a nominal power supply voltage for energizing the components of the system under test. The components of the system under test are interrogated when energized by the nominal power supply voltage. Since the components of the system under test are energized by a supply voltage having a magnitude ranging from a minimum to a maximum rated power supply voltage while being interrogated by the microprocessor during the self- test mode, all of the defective or potentially defective components of the system under test will fail during the performance of the self-test interrogation. Replacement thereof will ensure that the system will operate more efficiently and more reliably. <IMAGE>

Description

SPECIFICATION Self-test method and apparatus Background of the invention Field of the invention The present invention relates to a method and apparatus for testing a system when said system is energized by a wide range of supply voltages in addition to a nominal voltage.

Description of the prior art A self-test system in an electronic apparatus is utilized for interrogating the circuits of said apparatus during a self-test mode when energized by a nominal voltage from a power supply and analyzing the response received from said circuits in response to the interrogation. An improper response indicates that a failure has occurred within the circuits of said apparatus.

However, self-test systems of the prior art interrogated the circuits during the self-test mode only when the circuits were energized by the nominal voltage from the power supply. Since the circuits were not interrogated, during the self-test mode, when energized by other voltages from the power supply, which differ, in magnitude, from the nominal voltage, some of the components disposed within the circuits failed during a normal operating mode when energized by said other voltages.

Summary of the invention It is therefore a primary object of the present invention to provide a self-test system for an electronic apparatus which interrogates the circuits disposed within said apparatus, during the self-test mode, when energized by the nominal voltage and by said other voltages ranging in magnitude from a maximum rated magnitude to a minimum rated magnitude.

It is another object of the present invention to provide a first visual indication of the operation of said seif-test system in said self-test mode, said first visual indication indicating that said circuits of said apparatus are being interrogated when energized by a voltage having said maximum rated magnitude.

It is still another object of the present invention to provide a second visual indication of the operation of said self-test system in said self-test mode, said second visual indication indicating that said circuits of said apparatus are being interrogated when energized by a voltage having said minimum rated magnitude.

These and other objects of the present invention are accomplished by developing a selftest system which includes a microprocessor for performing the interrogation of the circuits and a new self-test program for directing the operation of said microprocessor in performing the self-test interrogation. The program directs the microprocessor to perform the self-test interrogation when the circuits are energized by the nominal voltage. Then, the program directs the microprocessor to perform the self-test interrogation when the circuits are sequentially energized by a voltage having said maximum rated magnitude and by a voltage having said minimum rated magnitude. When the program directs the microprocessor to perform the selftest interrogation utilizing the voltage having the maximum rated magnitude, a bit in a register is set.An output signal from the register is developed in response thereto, the output signal energizing a power supply. A voltage regulator in the power supply develops an output signal, the output signal from the voltage regulator being raised from a level corresponding to the nominal voltage to a level corresponding to said maximum rated magnitude in response to the output signal from the register. At this point, the microprocessor performs the interrogation of the circuits in said apparatus when energized by the voltage having said maximum rated magnitude.

Similarly;when the program directs the microprocessor to perform the self-test interrogation utilizing the voltage having the minimum rated magnitude, another bit in the register is set.

Another output signal is developed from the register in response thereto, said another output signal energizing said power supply. The voltage regulator in said power supply develops an output signal, the output signal from the voltage regulator being lowered from the nominal level to a level corresponding to said minimum rated magnitude in response to said another output signal from the register. At this point, the microprocessor performs the interrogation of the circuits when energized by the voltage having said minimum rated magnitude. Since the components of the circuits are tested when energized by a wide range of supply voltages, all of the potentially defective components will be detected. Replacement thereof will ensure a more reliable operation of the circuits of said apparatus.

Further scope of applicability of the present invention will become apparent from the description given hereinafter. However, it should be understood that the details of the description on the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from the detailed description.

Brief description of the drawings A full understanding of the present invention will be obtained from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: Fig. 1 illustrates a basic system block diagram illustrating the principles of the present invention.

Fig. 2 illustrates a more detailed system block diagram illustrating the principles of the present invention.

Fig. 3 illustrates a flow chart representative of the self-test program encoded in a ROMTone of the components of the microprocessor controlled system under test shown in Figs. 1 and 2.

Fig. 4 illustrates an alternative embodiment of a voltage regulator, a component of the system block diagrams shown in Figs. 1 and 2.

Fig. 5 illustrates another alternative embodiment of the voltage regulator, a component of the system block diagrams shown in Figs. 1 and 2.

Detailed description of the drawings Referring to Fig. 1, a basic system block diagram of the present invention is illustrated. A microprocessor controlled system under test 10 includes a system under test, such as in integrated circuit chip, and a microprocessor connected thereto. The microprocessor controlled system under test 10 may be, for example, a single-chip microcomputer, such as an Intel 8748. The microprocessor performs the self-test interrogation of the components of the system under test. The microprocessor interrogates the system under test, during the self-test mode, when the system is energized by the nominal voltage from the power supply. A response is received from the system in response to the interrogation. The response is analyzed.If an improper response is received, associated with one or more of the components of the system under test, the associated components are potentially defective. This represents an error condition, which is so reported.

However, during the normal operating mode, the system may be energized by other voltages from the power supply which differ in magnitude from the nominal voltage. Consequently, the components of the system under test may fail when energized by said other voltages. In order to test the components of the system under test, during the self-test mode, when energized by said other voltages, the microprocessor controlled system under test 10 develops a "raise to maximum" signal and a "lower to minimum" signal. A power supply 1 2 is connected to the microprocessor controlled system under test 10 and receives the "raise to maximum" signal and the "lower to minimum" signal therefrom. More specifically, a voltage regulator 1 2A, within the power supply 1 2 receives the "raise to maximum" signal and the "lower to minimum" signal.When the voltage regulator 12A is energized by the "raise to maximum" signal, a power supply voltage signal is developed therefrom at an output terminal thereof in response thereto representative of the maximum rated voltage of the power supply 12. When the voltage regulator 1 2A, within the power supply 12, receives the "lower to minimum" signal, another power supply voltage signal is developed therefrom at said output terminal thereof in response thereto representative of the minimum rated voltage of the power supply.

The output terminal of the voltage regulator 1 2a is connected, in feedback fashion, to the microprocessor controlled system under test 10.

When the microprocessor controlled system under test 10 is energized by the power supply voltage signal representative of the maximum rated voltage of the power supply 1 2, the microprocessor controlled system under test 1 0, and specifically the microprocessor, performs the selftest interrogation of the system under test, when energized by the power supply voltage signal representative of the maximum rated voltage of the power supply. Further, the microprocessor control system under test 10 performs the selftest interrogation of the system under test when energized by the power supply voltage signal representative of the minimum rated voltage of the power supply.

When the "raise to maximum" signal, and the "lower to minimum" signal is not developed by the microprocessor controlled system under test 10, the voltage regulator 1 2A within the power supply 12, generates a power supply voltage signal equivalent to the nominal voltage of the power supply. The microprocessor controlled system under test 10 then performs the self-test interrogation of the system under test, when energized by the nominal voltage of the power supply. Consequently, the components of the system under test are tested, when energized by the nominal supply voltage, the maximum rated power supply voltage, and the minimum rated power supply voltage. Therefore, an increased number of the potentially defective components of the system under test will be identified.Their replacement thereof will ensure that the system will operate more reliably during the normal operating mode than would otherwise be true had such a wide-range self-test interrogation not been performed.

Referring to Fig. 2, a more detailed system block diagram of the present invention is illustrated. The microprocessor controlled system test 10 further includes a system under test 1 OA.

The system under test 1 OA is connected to a system bus 1 OB. A read-only memory (ROM) 1 OC is connected to the system bus 1 OB. A microprocessor (yap) 1 OD is also connected to the system bus 1 or. An Intel 8086 may be used for the microprocessor 1 OD. A register 1 OE is connected to the system bus 1 OB. A first output terminal 1 0E1 of the register 10E is connected to the voltage regulator 1 2A. A second output terminal 1 OE2 of the register 1 OE is connected to the voltage regulator 1 2A. The voltage regulator 1 2A further includes a first inverter 1 2A1 , the input terminal thereof being connected to the first output terminal 1 OE 1 of the register 1 OE. The output of the inverter 1 2A1 is connected to the base of a transistor 1 2A2. The emitter of the transistor is connected to a ground potential. The collector of the transistor 1 2A2 is connected to a first resistor R 126. A second resistor R 121 is connected in series with the first resistor R126.

The output of the second resistor R1 21 is connected to a negative input terminal of a comparator 1 2A3. The negative input terminal of the comparator 1 2A3 is also connected to the output terminal of a resistor R1 27. The input terminal of the resistor R1 27 is grounded. Further, the negative input terminal of the comparator 1 2A3 is connected to the input terminal of another resistor R1 28, the output of said another resistor R128 being connected to the output terminal of the comparator 1 2A3.

The voltage regulator 1 2A further includes a second inverter 1 2A5, the input terminal thereof being connected to the second output terminal 1 0E2 of the register 1 OE. The output terminal of the inverter 1 2A5 is connected to the base of a second transistor 1 2A4. The emitter of the second transistor 1 2A4 is connected to a ground potential. The collector of the second transistor 1 2A4 is connected to the input terminal of a resistor Ri 41. The output terminal of the resistor R141 is connected to the positive input terminal of the comparator 12A3.The positive input terminal of the comparator 1 2A3 is also connected to the output terminal of a resistor R137.The input terminal of the resistor R137 is connected to a reference voltage source (VREF).

The output terminal of the comparator 1 2A3 generates the power supply voltage signal from the voltage regulator 1 2A within the power supply 1 2 shown in Fig. 1. This output terminal of the comparator 1 2A3 is connected, in feedback fashion to the system under test 1 OA, within the microprocessor control system under test 1 0. The output terminal of the comparator 1 2A3 is also connected to the first output terminal 1 owe 1 of the register 1 0E via the series connection of a resistor R1 and a first light emitting diode (LED) 1 4.

Furthermore, the output terminal of the comparator 1 2A3 is connected to the second output terminal 1 OE2 of the register 1 OE via the series connection of a resistor R2 and a second light emitting diode (LED) 1 6.

Referring to Fig. 3, a flow chart of the self-test program contained within the ROM 1 OC of the microprocessor controlled system under test 10 is illustrated. In Fig. 3, initially, the program sets the power supply to its nominal limit whereby the nominal power supply voltage is generated. The microprocessor 1 OD then performs the self-test interrogation of the system under test 1 OA when energized by the nominal power supply voltage. If an error is detected, the error is so reported. At this point, the self-test program sets the power supply to its high limit whereby the maximum rated power supply voltage is generated. The microprocessor 1 OD then performs the self-test interrogation of the system under test 1 OA, when energized by the maximum rated power supply voltage.Again, if an error is detected, the error is so reported. Finally, the self-test program sets the power supply to its low limit whereby the minimum rated power supply voltage is generated. The microprocessor 1 0D performs the self-test interrogation of the system under test 1 OA when energized by the minimum rated power supply voltage. If an error is detected, the error is so reported.

The operation of the circuit shown in Fig. 2 of the drawings of the present application will now be described in the paragraphs hereinbelow.

The self-test program encoded in the ROM 1 0C, within the microprocessor controlled system under test 10, directs the microprocessor 1 OD to energize the system under test 1 OA with the nominal power supply voltage from the power supply 1 2. In response to this direction, the register 1 OE does not develop an output signal from either the first or the second output terminals, OE1 or 1 OE2, thereof. Therefore, the "raise to maximum" signal and the "lower to minimum" signal is not generated. As a result, the power supply 12 develops the nominal power supply voltage for energizing the system under test.The microprocessor, at this point, interrogates the components of the system under test, soliciting responses in response thereto, analyzing the responses to determine if an erroneous response was received.

The self-test program encoded in the ROM 1 0C then instructs the microprocessor 1 OD to generate an output signal via the system bus 1 OB for energizing the register 1 OE. A bit in the register 10E is changed from "1" to "O". As a result, the "raise to maximum" signal is generated from the register 1 OE. This "raise to maximum" signal is inverted via the inverter 1 2A1 such that a high output signal is developed therefrom. The high output signal from the first inverter 1 2A1 causes the first transistor 1 2A2 to conduct. When the first transistor 1 2A2 conducts, the series connected resistors R1 26 and R121 are connected to ground.This, in turn, causes resistor R127 and the series connected resistors R126 and R121 to be connected in parallel with one another. As a result of the parallel connection of resistor R1 27 and resistors R1 26 and R1 21, the resistance of the lower leg of the feedback loop is reduced. As a consequence of this, the voltage present at the negative input terminal of the comparator 1 2A3 is reduced. As a result, the output signal present at the output terminal of the comparator 1 2A3 is increased, in order to compensate for the reduction in the voltage present at the negative input terminal thereof. The output terminal of the comparator 1 2A3 is connected to the system under test. Since the output voltage of the voltage regulator 1 2A is increased in response to the generation of the "raise to maximum" signal, an increased power supply voltage (the maximum rated voltage of the power supply) energizes the system under test 10A.

The "raise to maximum" signal, generated from the register 1 OE, is a low level signal. As a result, the first light-emitting diode 1 4 conducts.

Current flows through the first light-emitting diode 14 via resistor R1, causing light to be emitted therefrom. This represents a visual indication that the self-test system is operating in a self-test mode, and the components of the system are energized by a voltage having said maximum rated magnitude.

While the system under test 1 OA is eriergized by the increased power supply voltage supplied from the voltage regulator 12A, the self-test program in the ROM 1 0C directs the microprocessor to perform the self-test interrogation, wherein the various components of the system under test will be interrogated in order to solicit responses therefrom in response thereto while energized by the voltage having said maximum rated magnitude. The responses are analyzed to determine if an improper response has been generated from the respective components of the system under test 1 OA. If an-improper response is received, the microprocessor reports the error.

This error indicates that some of the respective components of the system are potentially defective.

At this point, the self-test program encoded in the ROM 1 OC instructs the microprocessor 1 OD to generate an output signal via the system bus 1.0B, to change a bit in the register 1 OE from "1" to "0", such that the "lower to minimum" signal is generated therefrom. This "lower to minimum" signal is applied to the input of the second inverter 12A5, which inverts the signal applied thereto. A high output signal is generated therefrom, the high output signal being applied to the base of the second transistor 12A4. As a result, the second transistor 1 2A4 conducts.

When the transistor 1 2A4 conducts, resistor R141 is connected to a ground potential. This, effectively, creates a voltage divider network comprising resistors R1 41 and R1 37. A voltage reference (VREF) is applied to an input terminal of R1 37. As a result of this voltage divider network, the voltage applied to the positive input terminal of the comparator 1 2A3 is reduced in magnitude from VREF to (R141) (VREF)/-(R141 +R137).

As a result of the reduction in the magnitude of the voltage applied to the positive input terminal of the comparator 1 2A3, the voltage present at the output terminal of the comparator 12A3 is also reduced in magnitude. Again, since the output of the comparator 12A3 is connected to the system under test, a reduced power supply voltage (the minimum rated voltage of the power supply) is applied to the system under test 1 OA.

At this point, the microprocessor 1 OD, in accordance with the instructions of the self-test program encoded in the ROM 1 0C, performs the self-test interrogation once again, wherein the individual components of the system under test are interrogated when energized by the reduced power supply voltage. The response received by the microprocessor 1 OD, as a result of this interrogation, is analyzed to determine if a proper response has been received. If an improper response has been received, the microprocessor reports the error.

When the "lower to minimum" signal is generated from the register 1 OE, a low level signal is generated. This low level signal causes the second light-emitting diode 16 to conduct.

Current then flows from the output terminal of the comparator 12A3, through the resistor R2, and through the light-emitting diode 16 for generating light in response thereto. This represents a visual indication that the self-test system is operating in a self-test mode, and the components of the system under test are energized by a voltage having said minimum rated magnitude.

Referring to Fig. 4, one alternative embodiment of the voltage regulator 12a, as shown in Figs. 1 and 2, is illustrated. If the raise to maximum signal is received by the voltage regulator 12 as shown in Fig. 4, there are four different methods for raising the output voltage (tout) in response thereto.Four switches are shown in Fig. 4, switches SF1X SF2X, S1X SR2X. If switches SF1X and SR2X are normally open, assuming the other switches remain in their open position as shown in Fig. 4, closing either switch SF1X or switch SR2X will raise the output voltage (tout). If switches SF2X and SR1X are normally closed, assuming the other switches remain in their open position as shown in Fig. 4, opening either switch SF2X or switch SR1X will raise the output voltage (tout).

Similarly, there are four different methods for lowering the output voltage (tout) of the voltage regulator 12a shown in Fig. 4 in response to the lower to minimum signal received thereby. If the switches SF2X and SR1X are normally open, assuming the other switches remain in their open position as shown in Fig. 4, closing either switch SF2X or SR1X will lower the output voltage (tout).

Similarly, if switches SF1X and SR2X are normally closed, assuming the other switches remain in their open position, as shown in Fig. 4, opening either switch SF1X or switch SR2X will lower the output voltage (Vout).

In the above description, it is assumed that the "raise to maximum" signal would close either one of the normally open switches SF1X or SR2X- Alternatively, the raise to maximum signal would open either one of the normally closed switches SF2X or SR1X Similarly, the lower to minimum signal would close either one of the normally open switches SF2X or SR1X Alternatively, the lower to minimum signal would open either one of the normally closed switches SF1X or SR2X In Fig. 5, another alternative embodiment of the voltage regulator 12a, shown in Figs. 1 and 2, is illustrated.In Fig. 5, two switches are illustrated, switches Svx and S,x. If the raise to maximum signal is received, if normally open switch Svx is closed, assuming that the other switch remains in its open position as shown in Fig. 5, the output voltage (tout) is raised. If the switch S,x is normally closed, and if switch S,x is opened, the output voltage (tout) is raised. If the lower to minimum signal is received, and if the normally open switch S,x is closed, assuming that the other switch remains in its open position as shown in Fig. 5, the output voltage (tout) will be lowered. Similarly, if the switch Svx is normally closed, and if switch Svx is opened, assuming that the other switch remains in its open position as shown in Fig. 5, the output voltage (tout) will be lowered In Fig. 5, an adjustable three-terminal voltage regulator 12awl is utilized.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims

1. A self-test system, comprising: first means connected to a system under test for developing a first output signal and a second output signal; second means connected to said first means and to said system under test and responsive to said first and second output signals from said first means for developing a nominal signal when not energized by said first and said second output signals, said second means developing a maximum signal having a magnitude greater than the magnitude of said nominal signal when energized by said first output signal, said second means developing a minimum signal having a magnitude lower than the magnitude of said nominal signal when energized by said second output signal, said nominal signal, said maximum signal, and said minimum signal energizing said system under test, said first means interrogating the components of said system under test while energized by said nominal signal, said first means interrogating the components of said system under test while energized by said maximum signal, said first means interrogating the components of said system under test while energized by said minimum signal.

2. The self-test system of claim 1 further comprising: first indication means for providing a first indication that said first output signal is generated from said first means.

3. The self-test system of claim 1 further comprising: second indication means for providing a second indication that said second output signal is generated from said first means.

4. A method of testing the components of a system under test, comprising the steps of: energizing the components of said system under test with a nominal voltage; interrogating said components while energized by said nominal voltage and analyzing a response received as a result of the interrogation; energizing said components with a maximum voltage having a magnitude greater than the magnitude of said nominal voltage; repeating the interrogating and analyzing steps while said components are energized by said maximum voltage; energizing said components with a minimum voltage having a magnitude less than the magnitude of said nominal voltage; and repeating the interrogating and analyzing steps while said components are energized by said minimum voltage.

5. A self-test system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

6. A method of testing the components of a system under test substantially as hereinbefore described.