GB2123251A - Timer-controlled audio component system - Google Patents

Abstract

In a multiple-component audio system the components (1,2....m) are connected to a common amplifier (D) and speaker (E) and are arranged in an order of priority. Control circuits in each of the components are linked in a cascade arrangement corresponding to the order of priority. When one of the components is turned on, the associated circuit produces a signal (A1... Am-1, Am) which inhibits the operation of lower-ordered ones of the components. A timer (T) contained in one of the control circuits can reset either the control circuits of all components in the system, or only the control circuit of the highest ordered one of the components. <IMAGE>

Description

SPECIFICATION Timer-controlled audio component system The present invention pertains to a control system for audio components. More particularly, the invention pertains to a timer-based control device for an audio component system composed of a plurality of components.

Timers for turning on and off audio components have widely been used. Recently, such timers have been applied to mobile audio component systems for controlling the operation pf such systems. Tuners equipped with timers have recently been announced. However, such arrangements are limited to controlling the operation of only the tuner, and are not adaptable for controlling the operation of other components within the system such as a tape deck or the like. Accordingly, such a system suffers a drawback in that, while a specific compo nent can be controlled with the timer, the other components in the system may still be energized, even though their audio outputs are defeated.

Hence, the power consumption of such systems is much higher than what it should be. Also, while a tuner is being operated, a tape player may continue to move a tape cassette inserted therein. Thus, when the user wishes to operate the tape player, the tape may not be at the desired starting point.

Also, such a system is disadvantageous in that an audio cutoff circuit must be provided for all components other than the tuner. This is, of course, costly, and the wiring between components needed to effect the scheme is complex.

An object of the present invention is to provide an audio component control system which is controlled by a single timer and in which more than one component is prevented from operating at any one time.

According to the present invention a multiplecomponent audio system comprises a plurality of components being assigned a predetermined order of priority; a plurality of control circuits, each associated with a respective one of the components, the control circuits being cascade connected in the order of priority of the components, and each of the control circuits comprising means for supplying a signal in a state inhibiting operating of components of lower priority when the respective component is actuated; and timer means disposed in one of the control circuits for resetting each of the control circuit means.

Two examples of systems according to the invention will now be described with reference to the accompanying drawings in which: Figure lisa block circuit diagram of an audio system; Figure 2 is a circuit diagram of portions of the system of Figure 1 showing the timer control system of the invention; and Figure 3 is a circuit diagram similar to that of Figure 2, but showing an alternative embodiment.

Figure 1 is a block diagram illustrating an audio component system constructed in accordance with the invention. This audio component system in cludes components 1, 2 . . ., m, m+1. The audio output from each component is applied to an output signal bus B using a so-called "wired-OR" technique.

The signal present on the output signal bus B is amplified by an output amplifier D and then applied to a speaker E.

Each component is assigned a particular order of priority. In the example here under discussion, the order of priority is assumed to descend from component 1 to component m + 1. That is, component 1 has the highest priority and component m + 1 the lowest priority of the components shown in Figure 1.

Each component is provided with a control circuit.

When the corresponding component is turned on by the user, the control circuit of the corresponding components disables a signal Aa, . . ., Am, Am, Am+1, ... which controls the flow of power to the subsequent components in the prioritized sequence.

For instance, if the highest order components is turned on, the signal A, shuts off the power to the components 2,... Am, Am+i..., A timer T is contained within the control circuit of the component m. An output signal from the timer T is conducted by a line C to reset inputs of control circuits of each of the components 1, . . ., Am, Am+1, .

This signal on the line C is used to turn off all components within the system, thereby permitting the user to selectively turn on any of the components.

The system of Figure 1 will be explained in more detail with reference to Figure 2 which is a detailed circuit diagram illustrating the control circuits and related portions of the system of Figure 1. In Figure 2, like reference numerals identify like components in Figure 1. The component 1, which has the highest priority in this system, is assumed to be a tape deck.

This tape deck includes a motor M for driving the tape, a magnetic head H, an amplifier circuit OP1 and associated components.

Assuming that all control circuits of all components have been reset, when a power supply switch S is operated, a differential circuit composed of a resistor R1, diodes D1 and D2, and a capacitor C1 transmits a pulse to the base of the transistor Q, through a diode D3. The transistor Q, is thereby turned on, actuating the coil L1 of a relay. The contact of the relay is switched from the normally closed (NC) position to the normally opened (NO) position. The power supply voltage Vcc is then applied to the motor M, amplifier Opi, and also to the base of the transistor Qs through resistors R2 and R4. Thus, the transistor Q1 is made to hold the on state of the relay.The output signal from the amplifier OP1 can then be passed through the diode D5 to the output signal line B.

On the other hand, if the power switch S, remains in the off state, the relay remains off and the contact of the relay connects the power supply voltage Vcc via the normally closed contact to the line A1.

The control circuit of the second component 2 includes a flip-flop FF1, having an enable switch Sic connected between its trigger input T and the line A1, which supplies power to the component 2 in the case, and only in the case, that the first component 1 is not turned on. The reset input R of the flip-flop FF, is also connected to the line A1 AND gate G1 has one input connected to the Q output from the flip-flop FF and a second input to the line A1. The Q output of the flip-flop FF1 is applied to the base of a transistor Q10, the collector of which receives the signal present on the line A, and the emitter of which is connected to supply power to an amplifier OP2.The output of the amplifier OP2 is connected to the output signal line B through a diode Dlo.

If the component 1 is turned on, no power supply potential will be applied to the line Al. Thus, actuation of the switch S10 in that stage will be ineffective to trigger the flip-flop FF1. Hence, the Q outputfrom the flip-flop FF, remains in a low state, thereby keeping the transistor Q,0 off and denying power to the amplifier OP2. The output of the AND gate G1 will also be low, thereby inhibiting the operation of the lower-priority components in the system. One the other hand, if the component 1 is turned off, the power supply voltage Vcc will be present on the line A1.In that case, actuation of the switch Slo causes the flip-flop FF1 to change states, thereby turning on the transistor Q10 and supplying power to the amplifier OP2. At that time, a low output on the 0 output from the flip-flop FF, will be present, thereby causing the output of the AND gate G1 also to be low. Thus, components of lower priority than component 2 will be prevented from operating.

Further, if both components 1 and 2 are not turned on, the positive voltage on the line Al and the high output from the 0 output terminal of the flip-flop FF, will cause the output of the AND gate G1 to be high.

Thus, a component of lower priority can then be turned on.

The control circuit of the component m, which contains the timer T, includes a flip-flop FF2, the trigger input T of which is connected to the control line Am~1 through a control switch S20. The Q output of the flip-flop FF2, when it is in the high state, closes the contact S21. The contact S23 is closed when the signal on line Am~1 is activated. All of the contacts S21, S22, and S23 are opened when the timer T runs out and closes a switch S24, thereby applying a positive signal to the line C. The upper contacts of the switches S21 and S22 are applied to a base of the transistor Q20, the connector of which is connected .to Vcc and the emitter of which is connected to supply power to an amplifier OP3.As in the previous cases, the output of the amplifier OP3 is supplied through a diode D20 to the output signal line B. The signal on the upper contacts of the switches S21 and S22 is applied through an inverter 11 to on input of an AND gate G2. The other input to the AND gate G2 is supplied by the line Am~1. The output of the AND gate G2 is the control signal Am.

If none of the higher-order components are turned on, Am~1 will be at a high level. In that case, if the switch S20 is closed, the flip-flop FF2 changes stage, thereby setting its Q output in the high state and closing the switch S21, thus supplying power through the transistor Q20 to the amplifier OP3. A low signal is then applied from the output of the inverter Ii to the AND gate G2, thereby placing the control signal Am in the low state. If the component mis not turned on, a high signal will be applied by the inverter Ii to the AND gate G2, thereby setting the control signal Am in the high state.

When the switch S24 is closed by the timer T, all of the control cicuits of all of the components 1 through m + 1 are reset. In the component 1, this is dane by applying a pulse through a differentiator circuit, composed of resistors 5 and R6, a capacitor C2 and a diode 7 to the base of a transistor Q2. This removes the base drive to the transistor Q1, cutting off the current flow through the coil L1 of the relay, and setting the relay contact to the normally closed (NC) position. In the second component 2, the flip-flop FF.

is reset. In the component m, the switches #2i, $22 and S23 are opened.

An alternate embodiment of the invention is shown in the diagram of Figure 3. In this embodiment, the reset line signal C is applied only to the first component 1. With this arrangement, only the first component 1, to which the highest priority has been assigned, can be turned off by actuation of the timer T. After the component 1 has been reset, the other components of lower priority can be actuated as desired.

With the invention, it is possible to operate each component as desired without having to supply power to nonselected components. That is, by assigning priorities to the various components of the system, power which would be wasted in a priqr art system is saved. Moreover, additional components can readily be added to the system without having effect extensive wiring changes.

Claims (5)

1. A multiple-component audio system comprising a plurality of components, the components being assigned a predetermined order of priority; a plurality of control circuits, each associated with. a respective one of the components, the control circuits being cascade connected in the order of priority of the components, and each of the control circuits comprising means for supplying a signal in å state inhibiting operation of components of lower priority when the respective component is actuated; and timer means disposed in one of the control circuits for resetting each of the control circuit means.

2. A system according to claim 1, wherein the timer is coupled to reset all of the contrn.Lcircu,its in the system.

3. A system according to claim 1, wherein the timer is coupled to reset only a control circuit.having a highest priority among said components.

4. A system according to any of claims 1 to 3, wherein audio outputs of all of the components are coupled to a single output signal line.

5. A multiple-component audio system, subataP tially as described with reference to Figures 1 or Figures 1 and 3 of the accompanying drawinRs.