GB1429323A - Special instruction processin g unit and a data processing system embodying the same - Google Patents
Special instruction processin g unit and a data processing system embodying the sameInfo
- Publication number
- GB1429323A GB1429323A GB4734873A GB4734873A GB1429323A GB 1429323 A GB1429323 A GB 1429323A GB 4734873 A GB4734873 A GB 4734873A GB 4734873 A GB4734873 A GB 4734873A GB 1429323 A GB1429323 A GB 1429323A
- Authority
- GB
- United Kingdom
- Prior art keywords
- instruction
- central processor
- class
- module
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Multi Processors (AREA)
Abstract
1429323 Data processing systems DIGITAL EQUIPMENT CORP 10 Oct 1973 [10 Oct 1972] 47348/73 Heading G4A The system includes a central processor and a separate module for processing instructions forming a distinct class. The class may consist of floating point instructions, for example. An instruction processing cycle is initiated on the arrival at the modules of a transfer signal generated by the central processor when it decodes an instruction in the said class. The module includes a control unit which processes each instruction in a series of processing cycles. During each cycle the unit generates control and synchronizing signals and then prevents a further cycle until the next transfer signal is received. The generation of the control signal is inhibited in the final processing cycle. The synchronizing pulse is passed to the central processor which reverts to a normal operating sequence and calls for the next instruction, which may be processed concurrently with the processing cycle occurring in the module. Several modules may be connected to the central processor, each module being pertinent to a respective class of instructions.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US29595272A | 1972-10-10 | 1972-10-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1429323A true GB1429323A (en) | 1976-03-24 |
Family
ID=23139935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4734873A Expired GB1429323A (en) | 1972-10-10 | 1973-10-10 | Special instruction processin g unit and a data processing system embodying the same |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5828609B2 (en) |
CA (1) | CA1013861A (en) |
DE (1) | DE2350871A1 (en) |
GB (1) | GB1429323A (en) |
IE (1) | IE40138B1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3811114A (en) * | 1973-01-11 | 1974-05-14 | Honeywell Inf Systems | Data processing system having an improved overlap instruction fetch and instruction execution feature |
JPS6016647B2 (en) * | 1977-11-30 | 1985-04-26 | 株式会社日立製作所 | Arithmetic control method |
US4229801A (en) * | 1978-12-11 | 1980-10-21 | Data General Corporation | Floating point processor having concurrent exponent/mantissa operation |
JPS59165140A (en) * | 1983-03-10 | 1984-09-18 | Fujitsu Ltd | Two-dimensional arithmetic circuit |
US4947316A (en) * | 1983-12-29 | 1990-08-07 | International Business Machines Corporation | Internal bus architecture employing a simplified rapidly executable instruction set |
JPS637217Y2 (en) * | 1984-11-26 | 1988-03-01 | ||
US5047015A (en) * | 1989-03-17 | 1991-09-10 | Merit Medical Systems, Inc. | Locking syringe |
-
1973
- 1973-10-09 CA CA182,925A patent/CA1013861A/en not_active Expired
- 1973-10-10 DE DE19732350871 patent/DE2350871A1/en not_active Ceased
- 1973-10-10 GB GB4734873A patent/GB1429323A/en not_active Expired
- 1973-10-10 IE IE181473A patent/IE40138B1/en unknown
- 1973-10-11 JP JP48114325A patent/JPS5828609B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2350871A1 (en) | 1974-04-18 |
IE40138B1 (en) | 1979-03-28 |
CA1013861A (en) | 1977-07-12 |
IE40138L (en) | 1974-04-10 |
JPS49100938A (en) | 1974-09-24 |
JPS5828609B2 (en) | 1983-06-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PE20 | Patent expired after termination of 20 years |
Effective date: 19931009 |