JPS5576464A - Common bus control system for multi-processor system - Google Patents
Common bus control system for multi-processor systemInfo
- Publication number
- JPS5576464A JPS5576464A JP14915578A JP14915578A JPS5576464A JP S5576464 A JPS5576464 A JP S5576464A JP 14915578 A JP14915578 A JP 14915578A JP 14915578 A JP14915578 A JP 14915578A JP S5576464 A JPS5576464 A JP S5576464A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- circuit
- common bus
- monitor
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
Abstract
PURPOSE: To secure both the monitor and control for the common bus with a simple constitution by connecting the monitor/control circuit for the common bus to the common bus itself only when the defect is detected, thus preventing the system breakdown.
CONSTITUTION: Plural number of processors 3 are connected to common bus A via bus port 2 each. Bus monitor/control circuit 1 is connected to bus 4, and furthermore bus monitot/control circuit state signal line A6 is provided to bus A. Line A6 is connected to the output side of fault recorgnition circuit 28 in port 2, and thus the instantaneous pulse signals are delivered in case some defect occurs to processor 3, the input/output circuit and port 2 respectively. This pulse signal generated through line A6 of bus A is applied to OR gate 18 of circuit 1 to secure the OR with the fault signal of timing signal monitor circuit 16, and interruption signal E1 is supplied to processor 11. Then the necessary processes are given by processor 11 to prevent the discontinuation of operation for the whole system.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53149155A JPS5853777B2 (en) | 1978-12-04 | 1978-12-04 | Common bus control method in multiprocessor systems |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53149155A JPS5853777B2 (en) | 1978-12-04 | 1978-12-04 | Common bus control method in multiprocessor systems |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5576464A true JPS5576464A (en) | 1980-06-09 |
JPS5853777B2 JPS5853777B2 (en) | 1983-12-01 |
Family
ID=15468980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53149155A Expired JPS5853777B2 (en) | 1978-12-04 | 1978-12-04 | Common bus control method in multiprocessor systems |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5853777B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6190019B1 (en) | 1999-03-08 | 2001-02-20 | Dimplex North America Limited | Display device with visual effect apparatus |
JP2020004206A (en) * | 2018-06-29 | 2020-01-09 | 日本電産サンキョー株式会社 | Information processing device and information processing method |
-
1978
- 1978-12-04 JP JP53149155A patent/JPS5853777B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6190019B1 (en) | 1999-03-08 | 2001-02-20 | Dimplex North America Limited | Display device with visual effect apparatus |
JP2020004206A (en) * | 2018-06-29 | 2020-01-09 | 日本電産サンキョー株式会社 | Information processing device and information processing method |
Also Published As
Publication number | Publication date |
---|---|
JPS5853777B2 (en) | 1983-12-01 |
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