GB1417236A - Double-slope integrating analogue-digital convertors - Google Patents

Abstract

1417236 Analogue-to-digital conversion SOC ANON FRANCAISE DU FERODO 5 April 1973 [5 April 1972] 16344/73 Heading H3H In a dual ramp analogue-to-digital converter, integrating capacitor 12 becomes charged during a preliminary correction phase A with the integrated drift of the amplifiers 13, 14, which is then subtracted from the integration of the input Vx during phase B (e.g. by reversing the connections to the capacitor 12) so as to correct the duration Tx of the final discharge of capacitor 12 for said drift. In Figs. 1 and 2 the durations T of phases A and B are each equal to 10<SP>3</SP> clock pulses from oscillator 21, counted in decades 22. At the end of phase B, switch I 3 shorts amplifier 14 and switches I 4 are closed to allow reference current 18 to discharge capacitor 12, comparator 20 triggering read-out of counter 23 at the end of phase C. Modifications.-A rest period (R 2 ) may be interposed between phases A and B in which amplifier 14 is shorted and capacitor 12 is isolated. An inverting amplifier (30) may replace reversing switches I 5 -I 8 , Fig. 5 (not shown). The reference current may be applied via amplifier 14, a drift correction voltage being applied to the comparator, Figs. 6 and 7 (not shown). Phases A and B need not be of equal duration if appropriate weighting resistors are used. Input Vx may come from a Wheatstone bridge, supplied with D.C. pulses of width equal to the combined duration of phases B and C, switches I 1 , I 2 then being unnecessary. Said D.C. pulses may be derived from the same source (V R ) as the reference current 18, Fig. 8 (not shown).