GB1397288A - Analogue to digital converters - Google Patents

Abstract

1397288 Analogue to digital converter COMARK DATA GROUP 5 Dec 1973 [5 Dec 1972] 56011/72 Heading G4H In an analogue-to-digital converter of the type in which clock pulses are counted during the time taken for a comparison signal to change from an initial value to the value of the input analogue, switches 14, 15 are provided for alternately connecting to the comparator 10 the input analogue Vin and a reference signal Vref which is used for resetting the comparison signal to its starting value which thereby equals Vref plus automatic correction for drift in the comparator 10. If a high gain amplifier (not shown) is included at the input 12, its drift is also compensated. As shown, at the start of a cycle (t 2 in Fig. 2, not shown) Vin is connected to 12, counting gate 33 is enabled, and one of two current generators 20, 21 depending on the sign of Vin, is started, its current being integrated by a capacitor 18 to provide the comparison signal at 11. When this reaches Vin the current generator is stopped and gates 33 disabled. After a delay for settling, which is preferably long enough to obviate the use of latches in the display 37, multivibrator 26, via bistable 27, changes over switches 14, 15 to connect Vref to 12. The other of the current generators 20, 21 is started and the voltage at 11 ramps down until Vref + drift is reached. If Vin is from a thermocouple, non-linearity may be compensated by changing the value of the current from generators 20, 21 when certain counts are reached by counter 35. Multivibrator 26 may be locked on to the clock pulse generator 34. Modifications.-A staircase comparison signal may be used instead of a ramp. The control logic may be formed as a single MOS chip, Fig. 6 (not shown).