GB1400561A - Signal converter apparatus for two level binary signals - Google Patents
Signal converter apparatus for two level binary signalsInfo
- Publication number
- GB1400561A GB1400561A GB2698472A GB2698472A GB1400561A GB 1400561 A GB1400561 A GB 1400561A GB 2698472 A GB2698472 A GB 2698472A GB 2698472 A GB2698472 A GB 2698472A GB 1400561 A GB1400561 A GB 1400561A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- pulses
- bit
- signals
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1411—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol conversion to or from pulse width coding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/01—Details
- G06K7/016—Synchronisation of sensing process
- G06K7/0166—Synchronisation of sensing process by means of clock-signals derived from the code marks, e.g. self-clocking code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Artificial Intelligence (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
Abstract
1400561 Signal conversion R O BARNES 9 June 1972 [1 July 1971 23 March 1972] 26984/72 Headings G4H and G4M A demodulator (Figs. 3, 3A) converts a series binary input signal of two-level non-synchronous binary input bits having a non-uniform bit repetition frequency (e.g. biphase mark, space or level signals 14, 16, 18, Fig. 2) into a series binary output signal in a different code (e.g. a non-return-to-zero signal 70, 72 or 74) by a process which includes the derivation from each input bit of a timing reference signal which is compared with the width of the succeeding input bit to determine whether it is a binary 1 or 0, the amplitude of the signal being automatically corrected for each bit to compensate for changes in the input bit width. Signals of varying bit width may arise as the outputs of binary information readers (Fig. 1, not shown) used in a supermarket checkout system, the readers being used to read data from coded strips on goods or credit cards, changes in the speed of relative movement between reader and record giving rise to different bit rates. In the embodiment of Fig. 3, a biphase input A is converted to pulses C and D representing positive- and negative-going transitions (see Fig. 4), which are then combined into a pulse train E. The first two E pulses (corresponding to a preamble bit, Fig. 2) are gated through 118 to an OR-gate 130 to form the first two of a sequence of pulses I: they are inverted and applied to a gate 140 to block pulses from an oscillator 142, so that a time reference counter 80 stops counting. The I pulses also go via 144 to bit and word-end counters 82, 84 to cause the transfer thereto of the complement of the count in 80 (there is, however, no output from 82 and 84 since their final stage flip-flops are maintained zero). Pulses I also go to a circuit 132 to produce delayed pulses I<SP>1</SP> which reset counter 80 to zero and generate further delayed pulses I<SP>11</SP> which reset flip-flops 88, 96 in a discriminator circuit 86. Pulses I<SP>11</SP> also go via 146 to cause flip-flops 122, 126 in an input memory circuit 124 to terminate a "counter reset" signal J and allow counters 80-84 to begin counting. The abovementioned signals and apparatus also combine to produce "in process" and "begin" signals K, L. Between the first two I<SP>1</SP> pulses counter 80 counts pulses at a frequency ¥f 0 to produce a signal whose value is shown symbolically as Q 0 <SP>1</SP> which reaches a maximum 214 corresponding to the time width of the preamble bit. The complement of 214 is transferred to counters 82, 84 by the second I pulse for comparison with the width of the next bit of signal A: 82 and 84 output signals M 0 <SP>1</SP>, N 0 <SP>1</SP> which start firstly at zero, and subsequently at the level of the transferred count corresponding to the width of the preceding bit (so as to compensate for a varying bit rate if this should occur). Signal K enables gate 120 to pass post-preamble E pulses as G pulses (data transition) to gate 148 which is enabled by a signal R from a circuit 86 to give a bit sync signal H corresponding to the transitions 232 at the beginning and end of each bit. Signal H provides further signals I, I<SP>1</SP>, I<SP>11</SP>. When output value M 0 <SP>1</SP> (218) exceeds output value Q 0 <SP>1</SP> (214) a bit counter output signal M<SP>11</SP> appears at the output of 82 and causes flipflops 88, 98 to produce signal R, this signal being terminated by the successive reset pulses I<SP>11</SP> which reset 88 to close gate 148 so that signal G is blocked until the next M<SP>11</SP> output-thus data transition pulses 228<SP>1</SP> are blocked and counter 80 counts during the entire time period between the beginning and end of each bit. Signal R is inverted to give a signal T which enables a gate 94 between R-pulses: thus only data transition pulses U (228<SP>1</SP>) pass through 94, these then triggering a flip-flop 96 whose output provides return-to-zero signals S or (via another flip-flop 98) NRZ signals V. Finally, a long termination pulse causes end counter 84 to produce an end pulse Y which causes the production of signal J and the termination of signal K. A similar demodulator circuit is described for dealing with pulse width modulated signals having varying bit widths (Figs. 5-6, not shown).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15879971A | 1971-07-01 | 1971-07-01 | |
US23725672A | 1972-03-23 | 1972-03-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1400561A true GB1400561A (en) | 1975-07-16 |
Family
ID=26855397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2698472A Expired GB1400561A (en) | 1971-07-01 | 1972-06-09 | Signal converter apparatus for two level binary signals |
Country Status (7)
Country | Link |
---|---|
CA (1) | CA955685A (en) |
DE (1) | DE2230067A1 (en) |
ES (1) | ES404459A1 (en) |
FR (1) | FR2143920A1 (en) |
GB (1) | GB1400561A (en) |
NL (1) | NL7209003A (en) |
SE (1) | SE383950B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2216316A (en) * | 1988-02-16 | 1989-10-04 | Mr Sensors Ltd | Decoding recorded data |
GB2276262A (en) * | 1990-09-07 | 1994-09-21 | Mitsubishi Heavy Ind Ltd | Recording/reproducing circuits for toll road tickets |
GB2306033A (en) * | 1995-10-02 | 1997-04-23 | Pitney Bowes Inc | Bar code decoding with speed compensation |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2443170A1 (en) * | 1974-11-08 | 1980-06-27 | Ibm | METHOD FOR ENCODING DATA IN F2F CODE, AND METHOD AND APPARATUS FOR INTERPRETATION OF SUCH DATA |
FR2446561A1 (en) * | 1974-12-31 | 1980-08-08 | Ibm | Reader for distorted two-frequency bar code data - compensates for print speed and acceleration e.g. of hand-held probe |
-
1972
- 1972-06-02 CA CA143,760A patent/CA955685A/en not_active Expired
- 1972-06-09 GB GB2698472A patent/GB1400561A/en not_active Expired
- 1972-06-20 DE DE19722230067 patent/DE2230067A1/en active Pending
- 1972-06-29 NL NL7209003A patent/NL7209003A/xx unknown
- 1972-06-30 FR FR7223701A patent/FR2143920A1/fr not_active Withdrawn
- 1972-07-01 ES ES404459A patent/ES404459A1/en not_active Expired
- 1972-07-03 SE SE871472A patent/SE383950B/en unknown
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2216316A (en) * | 1988-02-16 | 1989-10-04 | Mr Sensors Ltd | Decoding recorded data |
GB2216316B (en) * | 1988-02-16 | 1992-05-13 | Mr Sensors Ltd | Reading and decoding recorded data |
GB2276262A (en) * | 1990-09-07 | 1994-09-21 | Mitsubishi Heavy Ind Ltd | Recording/reproducing circuits for toll road tickets |
GB2276262B (en) * | 1990-09-07 | 1995-03-22 | Mitsubishi Heavy Ind Ltd | Recording circuits for toll road tickets |
US5455408A (en) * | 1990-09-07 | 1995-10-03 | Mitsubishi Jukogyo Kabushiki Kaisha | Magnetic recording circuit for toll road ticket |
GB2306033A (en) * | 1995-10-02 | 1997-04-23 | Pitney Bowes Inc | Bar code decoding with speed compensation |
GB2306033B (en) * | 1995-10-02 | 2000-06-07 | Pitney Bowes Inc | Bar code decoding with speed compensation |
Also Published As
Publication number | Publication date |
---|---|
DE2230067A1 (en) | 1973-01-11 |
SE383950B (en) | 1976-04-05 |
ES404459A1 (en) | 1976-03-01 |
NL7209003A (en) | 1973-01-03 |
FR2143920A1 (en) | 1973-02-09 |
CA955685A (en) | 1974-10-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |