ES404459A1 - Signal converter apparatus for two level binary signals - Google Patents

Signal converter apparatus for two level binary signals

Info

Publication number
ES404459A1
ES404459A1 ES404459A ES404459A ES404459A1 ES 404459 A1 ES404459 A1 ES 404459A1 ES 404459 A ES404459 A ES 404459A ES 404459 A ES404459 A ES 404459A ES 404459 A1 ES404459 A1 ES 404459A1
Authority
ES
Spain
Prior art keywords
input
signal
bits
ramp signal
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES404459A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ROLAND O BARNES
Original Assignee
ROLAND O BARNES
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ROLAND O BARNES filed Critical ROLAND O BARNES
Publication of ES404459A1 publication Critical patent/ES404459A1/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1411Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol conversion to or from pulse width coding
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/01Details
    • G06K7/016Synchronisation of sensing process
    • G06K7/0166Synchronisation of sensing process by means of clock-signals derived from the code marks, e.g. self-clocking code

Landscapes

  • Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Refinements in asynchronous demodulating apparatus, of the type comprising input means for supplying the demodulator input with a serial binary input signal of two-level asynchronous binary input bits having a repetition rate of uneven bits, whose input bits they have transition parts that extend between two levels of amplitude; and timing reference means for measuring the length of the successive bits of said input bits and for producing a time reference signal corresponding to the length of each input bit, characterized in that said timing reference means comprises means for producing a first ramp signal, of predetermined inclination during the period of each input bit length, to provide a ramp signal amplitude level at the end of said period, from which the timing reference signal is derived, such that the value of said reference signal automatically changes in response to changes in the length of said input bits, due to variations in the bit rate or rhythm, and comparing means to produce a second predetermined tilt ramp signal corresponding to the time between the transition parts of said input bits to compare dich a second ramp signal with the time reference signal, derived from said first ramp signal from the input bit immediately coming to determine whether the compared input bit is a binary one or a binary zero, and to produce an output signal binary serial corresponding to said input signal but of different code, said comparing means also comprising means for producing a third predetermined tilt ramp signal corresponding to the space time between successive input bits and for comparing said third bit ramp signal time reference signal derived from said first input bit ramp signal immediately proceeding to produce a stop pulse indicating the end of the input signal. (Machine-translation by Google Translate, not legally binding)
ES404459A 1971-07-01 1972-07-01 Signal converter apparatus for two level binary signals Expired ES404459A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15879971A 1971-07-01 1971-07-01
US23725672A 1972-03-23 1972-03-23

Publications (1)

Publication Number Publication Date
ES404459A1 true ES404459A1 (en) 1976-03-01

Family

ID=26855397

Family Applications (1)

Application Number Title Priority Date Filing Date
ES404459A Expired ES404459A1 (en) 1971-07-01 1972-07-01 Signal converter apparatus for two level binary signals

Country Status (7)

Country Link
CA (1) CA955685A (en)
DE (1) DE2230067A1 (en)
ES (1) ES404459A1 (en)
FR (1) FR2143920A1 (en)
GB (1) GB1400561A (en)
NL (1) NL7209003A (en)
SE (1) SE383950B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2443170A1 (en) * 1974-11-08 1980-06-27 Ibm METHOD FOR ENCODING DATA IN F2F CODE, AND METHOD AND APPARATUS FOR INTERPRETATION OF SUCH DATA
FR2446561A1 (en) * 1974-12-31 1980-08-08 Ibm Reader for distorted two-frequency bar code data - compensates for print speed and acceleration e.g. of hand-held probe
GB8803504D0 (en) * 1988-02-16 1988-03-16 Mr Sensors Ltd Method of decoding recorded data
MY106779A (en) * 1990-09-07 1995-07-31 Mitsubishi Heavy Ind Ltd Magnetic recording method and circuit for toll road ticket.
US5708261A (en) * 1995-10-02 1998-01-13 Pitney Bowes Inc. Bar code decoding with speed compensation

Also Published As

Publication number Publication date
DE2230067A1 (en) 1973-01-11
SE383950B (en) 1976-04-05
NL7209003A (en) 1973-01-03
FR2143920A1 (en) 1973-02-09
GB1400561A (en) 1975-07-16
CA955685A (en) 1974-10-01

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