GB1216185A - Improvements in analogue multipliers - Google Patents

Abstract

1,216,185. Multiplying and dividing circuits. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. 1 Dec., 1967 [2 Dec., 1966], No. 54136/66. Heading G4G. A multiplier/divider analogue circuit comprises an integrating operational amplifier and capacitor circuit A 1 , C 1 receiving a constant voltage + V S over temperature compensating resistances R1a, R1b; the capacitor being shunted by transistor TR 1 switchable by bi-stable BS. With transistor open, linear integration produces a negative going output increasing with time which is applied to inverting unity gain operational amplifier A 2 together with multiplying voltage V A , to produce output increasing with time from -V A to 0, applied to a level detector circuit comprising operational amplifier A 3 having feedback path containing resistances R6 to R9, oppositely poled diodes D 1 , D 2 , and variable resistance VR 1 setting trigger level to 0. An output positive to earth (logic 0) is developed until the output of A 2 reaches trigger level, at which the output switches to negative (logic 1) and the output of pulse shaper PS1 changes from negative (logic 1) to positive (logic 0) for application over diode D 3 of a three input AND gate also receiving over diodes D4, D5 the outputs of monostables MS1 and MS2 which are logic 1 in stable states. Thus the AND gate output switches to logic 0 to produce logic 1 from pulse shaper PS2, setting bi-stable BS to its SET state, closing transistor TR1, and opening TR2. Integrator A1 is reset after time proportional to VA. Similarly, the input of integrator A4, C2 receiving multiplier voltage Vb over variable resistance VR 2 is cut off by TR2 after time proportional to VA. Bi-stable BS on assuming SET state triggers monostable MS1 to close transistor TR4 to transmit the final output of A4, C2 to storage capacitor C 3 , and after a suitable readout time MS1 reverts, opens TR4, and triggers monostable MS2 to close TR3 for a suitable time to discharge A4, C2. MS2 reverts and triggers bi-stable BS to RESET for repetition of the cycle. The AND gate remains at logic 0 while either MS1 or MS2 are in unstable states, thus maintaining bi-stable BS at SET for the required interval. The stored signal on C 3 is applied to a high input impedance unity gain non inverting operational amplifier A5 whose output is shown mathematically to be proportional to V A V B /V S . Squaring may be effected by holding V A = V B and V S constant, while square rooting (Fig. 2, not shown) is effected by feeding back the output V M over an inverting unity gain operational amplifier to input V S , so that V M is proportional to #V A V B or to #V A if V B is held constant. The apparatus is applicable to a mass spectrometer as described in Specifications 1,167,341, 1,215,293 and 1,215,293 cog.