GB967671A - Improvements relating to analogue to digital converters - Google Patents

Abstract

967, 671. Electric selective signalling. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. Aug. 15,1962 [May 16, 1961],No. 17817/61. Heading G4H. [Also in Division H3] In an analogue-to-digital converter, in which pulses are fed to a counter for a time period proportional to the analogue sample quantity, a recurrent sweep voltage and the sample voltage are both applied to an amplifier the input A to which has upper and lower limit clamping devices, D3, D4, and a feedback such that the input voltage tends to assume one of the limiting values, and to change from one to the other when the sweep voltage reaches the sample value thereby producing an amplified output pulse which terminates or starts the time period. In Fig. 4, sample and sweep voltages are D.C. restored to be position and negative respectively, and applied through cathode follower valves Vl, V2 and resistors R5, R6 (a) to the input of a pentode amplifier V3 the output of which is fed through a cathode follower valve V4 &c. to a differentiating circuit C2,R15 5 preceding a blocking oscillator and also (b)to a resistor chain R7,R8,R10 associated with input clamping diodes D3,D4. At the beginning of the sweep, diode D3 conducts and clamps input A. As the sweep voltage approaches the sample voltage in magnitude, the voltage of input A tends to fall until diode D3 ceases to conduct, when a fall takes place which is amplified and fed back to make diode D4 conduct thereby clamping input A against further fall in voltage. The amplifier output rise consequent to cut-off of diode D3 is differentiated and triggers the blocking oscillator to produce a pulse which is delayed and then resets a gating pulse generator. This terminates a gating pulse which was allowing counting pulses to enter a binary counter and which was initiated at or soon after the start of the sweep by a delayed timing pulse. The blocking oscillator pulse also closes an inhibit gate through which the delayed timing pulse passes, so if the sample voltage is too small, the inhibit gate will be closed when the delayed timing pulse arrives and no counting will take place. To prevent overrun of the counter an AND gate receives counter outputs and resets the gating pulse generator if necessary.