FR3109466B1 - Dispositif de support d’une puce électronique et procédé de fabrication correspondant - Google Patents

Dispositif de support d’une puce électronique et procédé de fabrication correspondant Download PDF

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Publication number
FR3109466B1
FR3109466B1 FR2003845A FR2003845A FR3109466B1 FR 3109466 B1 FR3109466 B1 FR 3109466B1 FR 2003845 A FR2003845 A FR 2003845A FR 2003845 A FR2003845 A FR 2003845A FR 3109466 B1 FR3109466 B1 FR 3109466B1
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France
Prior art keywords
electronic chip
supporting
mounting face
support substrate
corresponding manufacturing
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FR2003845A
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FR3109466A1 (fr
Inventor
Fabien Quercia
Jean-Michel Riviere
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STMicroelectronics Grenoble 2 SAS
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STMicroelectronics Grenoble 2 SAS
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Priority to FR2003845A priority Critical patent/FR3109466B1/fr
Priority to US17/229,710 priority patent/US11916353B2/en
Publication of FR3109466A1 publication Critical patent/FR3109466A1/fr
Priority to US18/408,149 priority patent/US20240146019A1/en
Application granted granted Critical
Publication of FR3109466B1 publication Critical patent/FR3109466B1/fr
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    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/02345—Wire-bonding
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    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Led Device Packages (AREA)
  • Die Bonding (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

Dispositif électronique (DIS) comprenant un substrat de support (SS) comportant une face de montage (FM) et une puce électronique (PE) comportant une face arrière (FAR) collée sur la face de montage (FM) par un volume de colle (C), dans lequel le substrat de support (SS) comprend une pluralité d’éléments de calage (EC1A) faisant saillie sur la face de montage (FM) de façon à maintenir la puce en appui sur des zones de contact des éléments de calage (EC1A) dans une position parallèle à la face de montage (FM) du substrat de support (SS). Figure pour l’abrégé : Fig 1A
FR2003845A 2020-04-16 2020-04-16 Dispositif de support d’une puce électronique et procédé de fabrication correspondant Active FR3109466B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2003845A FR3109466B1 (fr) 2020-04-16 2020-04-16 Dispositif de support d’une puce électronique et procédé de fabrication correspondant
US17/229,710 US11916353B2 (en) 2020-04-16 2021-04-13 Electronic chip support device and corresponding manufacturing method
US18/408,149 US20240146019A1 (en) 2020-04-16 2024-01-09 Electronic chip support device and corresponding manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2003845A FR3109466B1 (fr) 2020-04-16 2020-04-16 Dispositif de support d’une puce électronique et procédé de fabrication correspondant
FR2003845 2020-04-16

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FR3109466A1 FR3109466A1 (fr) 2021-10-22
FR3109466B1 true FR3109466B1 (fr) 2024-05-17

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FR2003845A Active FR3109466B1 (fr) 2020-04-16 2020-04-16 Dispositif de support d’une puce électronique et procédé de fabrication correspondant

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US (2) US11916353B2 (fr)
FR (1) FR3109466B1 (fr)

Family Cites Families (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207645A (ja) 1982-05-28 1983-12-03 Fujitsu Ltd 半導体装置
JPH02146757A (ja) 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体装置
JPH03149864A (ja) 1989-11-07 1991-06-26 Matsushita Electron Corp リードフレーム
US5214307A (en) 1991-07-08 1993-05-25 Micron Technology, Inc. Lead frame for semiconductor devices having improved adhesive bond line control
JPH0547988A (ja) 1991-08-21 1993-02-26 Sony Corp 半導体装置
JPH05267362A (ja) 1992-03-19 1993-10-15 Hitachi Ltd 半導体装置の実装構造
US7008301B1 (en) * 1999-08-26 2006-03-07 Advanced Micro Devices, Inc. Polishing uniformity via pad conditioning
US7388294B2 (en) * 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
US7547978B2 (en) * 2004-06-14 2009-06-16 Micron Technology, Inc. Underfill and encapsulation of semiconductor assemblies with materials having differing properties
US7148560B2 (en) * 2005-01-25 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process
JP2007142176A (ja) * 2005-11-18 2007-06-07 Seiko Epson Corp 光モジュールの製造方法
JP4827851B2 (ja) * 2005-11-22 2011-11-30 ソニー株式会社 半導体装置および半導体装置の製造方法
JP2007194383A (ja) * 2006-01-19 2007-08-02 Hitachi Lighting Ltd 光学部材およびバックライト
JP2008091714A (ja) * 2006-10-03 2008-04-17 Rohm Co Ltd 半導体装置
JP5084829B2 (ja) * 2007-06-28 2012-11-28 パナソニック株式会社 半導体素子の実装構造体の製造方法、半導体素子の実装方法、及び加圧ツール
US8461672B2 (en) * 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8063474B2 (en) * 2008-02-06 2011-11-22 Fairchild Semiconductor Corporation Embedded die package on package (POP) with pre-molded leadframe
JP5043743B2 (ja) * 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP4971243B2 (ja) * 2008-05-15 2012-07-11 新光電気工業株式会社 配線基板
JP5210839B2 (ja) * 2008-12-10 2013-06-12 新光電気工業株式会社 配線基板及びその製造方法
FR2943849B1 (fr) * 2009-03-31 2011-08-26 St Microelectronics Grenoble 2 Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur
CN102484080B (zh) * 2009-06-18 2015-07-22 罗姆股份有限公司 半导体装置
KR20110041301A (ko) * 2009-10-15 2011-04-21 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
KR101715761B1 (ko) * 2010-12-31 2017-03-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
US8268677B1 (en) * 2011-03-08 2012-09-18 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer
ITTO20120154A1 (it) * 2012-02-21 2013-08-22 Stmicroelectronics Malta Ltd Procedimento di assemblaggio di un dispositivo integrato a semiconduttore
CN103426780A (zh) 2012-05-14 2013-12-04 万国半导体(开曼)股份有限公司 焊球阵列用作高度垫块及焊料固定物
JP6157998B2 (ja) * 2013-09-03 2017-07-05 ルネサスエレクトロニクス株式会社 半導体装置
US11469215B2 (en) * 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10461034B2 (en) * 2017-07-26 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US11417569B2 (en) * 2017-09-18 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having integrated circuit component with conductive terminals of different dimensions
US10497690B2 (en) * 2017-09-28 2019-12-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly
US11152295B2 (en) * 2018-04-13 2021-10-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method for manufacturing the same
JP2019204906A (ja) * 2018-05-24 2019-11-28 ルネサスエレクトロニクス株式会社 半導体装置
US10916488B2 (en) * 2018-06-29 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having thermal conductive pattern surrounding the semiconductor die
US11101214B2 (en) * 2019-01-02 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dam structure and method for forming the same
JP7298195B2 (ja) * 2019-03-05 2023-06-27 富士通オプティカルコンポーネンツ株式会社 光モジュール及びその製造方法
US11282791B2 (en) * 2019-06-27 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a heat dissipation structure connected chip package
US11410897B2 (en) * 2019-06-27 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a dielectric layer edge covering circuit carrier
US11456287B2 (en) * 2019-08-28 2022-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11610864B2 (en) * 2019-09-09 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method of forming the same
US11251119B2 (en) * 2019-09-25 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, package-on-package structure and method of fabricating the same
US11289399B2 (en) * 2019-09-26 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
US11282779B2 (en) * 2019-09-27 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and fabricating method thereof
US11315860B2 (en) * 2019-10-17 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing process thereof
KR102676063B1 (ko) * 2019-10-22 2024-06-18 삼성전자주식회사 패키지 기판 및 그의 제조 방법, 및 패키지 기판을 포함하는 반도체 패키지 및 그의 제조 방법
US11322453B2 (en) * 2019-11-26 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having channels formed between through-insulator-vias
US11462418B2 (en) * 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11315862B2 (en) * 2020-01-31 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US11557568B2 (en) * 2020-02-26 2023-01-17 Taiwan Semiconductor Manufacturing Company. Ltd. Package and manufacturing method thereof
US11574857B2 (en) * 2020-03-23 2023-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11373946B2 (en) * 2020-03-26 2022-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11410982B2 (en) * 2020-03-30 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacturing
US11609562B2 (en) * 2020-04-27 2023-03-21 Deere & Company Using generated markings for vehicle control and object avoidance
US11581281B2 (en) * 2020-06-26 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of forming thereof
US11355454B2 (en) * 2020-07-30 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
US11450581B2 (en) * 2020-08-26 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11521905B2 (en) * 2020-10-21 2022-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11557559B2 (en) * 2021-02-26 2023-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US11574861B2 (en) * 2021-03-25 2023-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package

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US20210328403A1 (en) 2021-10-21

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