FR3084520B1 - Procede de protection d'un circuit integre, et dispositif correspondant - Google Patents
Procede de protection d'un circuit integre, et dispositif correspondant Download PDFInfo
- Publication number
- FR3084520B1 FR3084520B1 FR1856886A FR1856886A FR3084520B1 FR 3084520 B1 FR3084520 B1 FR 3084520B1 FR 1856886 A FR1856886 A FR 1856886A FR 1856886 A FR1856886 A FR 1856886A FR 3084520 B1 FR3084520 B1 FR 3084520B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- protection method
- corresponding device
- charges
- different
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Circuit intégré (CI) comprenant des moyens de protection dudit circuit intégré (CI) comportant un corps électriquement conducteur à potentiel flottant (PC) situé dans le circuit intégré (CI) et ayant une quantité initiale de charges électriques, des moyens de détection (MD) configurés pour détecter une quantité de charges électriques (AC) sur ledit corps (PC) différente de la quantité initiale de charges, et des moyens de commande (MCMD) configurés pour déclencher une action de protection si la quantité de charges détectée (AC) est différente de la quantité initiale.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1856886A FR3084520B1 (fr) | 2018-07-25 | 2018-07-25 | Procede de protection d'un circuit integre, et dispositif correspondant |
US16/518,755 US10886240B2 (en) | 2018-07-25 | 2019-07-22 | Method for protecting an integrated circuit, and corresponding device |
US17/113,645 US11329011B2 (en) | 2018-07-25 | 2020-12-07 | Method for protecting an integrated circuit, and corresponding device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1856886 | 2018-07-25 | ||
FR1856886A FR3084520B1 (fr) | 2018-07-25 | 2018-07-25 | Procede de protection d'un circuit integre, et dispositif correspondant |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3084520A1 FR3084520A1 (fr) | 2020-01-31 |
FR3084520B1 true FR3084520B1 (fr) | 2020-08-14 |
Family
ID=65685435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1856886A Active FR3084520B1 (fr) | 2018-07-25 | 2018-07-25 | Procede de protection d'un circuit integre, et dispositif correspondant |
Country Status (2)
Country | Link |
---|---|
US (2) | US10886240B2 (fr) |
FR (1) | FR3084520B1 (fr) |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6856581B1 (en) | 2000-10-31 | 2005-02-15 | International Business Machines Corporation | Batteryless, oscillatorless, binary time cell usable as an horological device with associated programming methods and devices |
US6541792B1 (en) | 2001-09-14 | 2003-04-01 | Hewlett-Packard Development Company, Llp | Memory device having dual tunnel junction memory cells |
FR2844090A1 (fr) | 2002-08-27 | 2004-03-05 | St Microelectronics Sa | Cellule memoire pour registre non volatile a lecture rapide |
EP1400887A1 (fr) | 2002-09-20 | 2004-03-24 | EM Microelectronic-Marin SA | Dispositif de protection pour puce électronique comportant des informations confidentielles |
EP1586016A1 (fr) | 2003-01-10 | 2005-10-19 | Philips Intellectual Property & Standards GmbH | Agencement de circuit et procede de protection des composants electroniques contre une manipulation illicite |
JP4462903B2 (ja) * | 2003-11-18 | 2010-05-12 | パナソニック株式会社 | 半導体ウェハ |
US7202782B2 (en) * | 2004-08-04 | 2007-04-10 | Agere Systems Inc. | Method and apparatus for disabling an integrated circuit (IC) when an attempt is made to bypass security on the IC |
US8304313B2 (en) | 2004-08-23 | 2012-11-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and its manufacturing method |
US8022460B2 (en) | 2006-03-31 | 2011-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
FR2938953B1 (fr) | 2008-11-21 | 2011-03-11 | Innova Card | Dispositif de protection d'un boitier de circuit integre electronique contre les intrusions par voie physique ou chimique. |
CN103348251B (zh) * | 2011-01-31 | 2014-12-17 | 株式会社日立高新技术 | 自动分析装置 |
FR2978867B1 (fr) | 2011-08-01 | 2014-03-21 | St Microelectronics Rousset | Resistance ajustable |
US8378710B1 (en) * | 2011-09-20 | 2013-02-19 | Nxp B.V. | Secure device anti-tampering circuit |
JP2013114729A (ja) | 2011-11-30 | 2013-06-10 | Toshiba Corp | 不揮発性プログラマブルスイッチ |
FR2985059B1 (fr) | 2011-12-21 | 2014-01-10 | Oberthur Technologies | Dispositif de securisation d'un document electronique |
DE102012200168A1 (de) * | 2012-01-06 | 2013-07-11 | Technische Universität Berlin | Ladungsmesseinrichtung |
FR2986356B1 (fr) | 2012-01-27 | 2014-02-28 | St Microelectronics Rousset | Dispositif de protection d'un circuit integre contre des attaques en face arriere |
FR2991083A1 (fr) | 2012-05-24 | 2013-11-29 | St Microelectronics Grenoble 2 | Procede et dispositif de protection d'un circuit integre contre des attaques par sa face arriere |
EP2680184A1 (fr) | 2012-06-27 | 2014-01-01 | EM Microelectronic-Marin SA | Circuit intégré protégé contre des intrusions d'un pirate |
JP2014022507A (ja) | 2012-07-17 | 2014-02-03 | Toshiba Corp | 不揮発プログラマブルスイッチ |
US10216965B2 (en) | 2014-01-08 | 2019-02-26 | Stc.Unm | Systems and methods for generating physically unclonable functions from non-volatile memory cells |
US9965652B2 (en) | 2014-08-06 | 2018-05-08 | Maxim Integrated Products, Inc. | Detecting and thwarting backside attacks on secured systems |
FR3084492A1 (fr) | 2018-07-30 | 2020-01-31 | Stmicroelectronics (Rousset) Sas | Procede de detection d'une attaque par un faisceau de particules electriquement chargees sur un circuit integre, et circuit integre correspondant |
-
2018
- 2018-07-25 FR FR1856886A patent/FR3084520B1/fr active Active
-
2019
- 2019-07-22 US US16/518,755 patent/US10886240B2/en active Active
-
2020
- 2020-12-07 US US17/113,645 patent/US11329011B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR3084520A1 (fr) | 2020-01-31 |
US11329011B2 (en) | 2022-05-10 |
US20210091015A1 (en) | 2021-03-25 |
US10886240B2 (en) | 2021-01-05 |
US20200035623A1 (en) | 2020-01-30 |
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